Address access method, device and electronic device

Abstract

Embodiments of the present application relate to the field of computer technologies, and disclose an address access method, apparatus, and electronic device. The method includes: receiving a memory access request; in response to the memory access request, obtaining a bus address of an external memory, where the external memory is communicatively connected to a processor through a data control bus; the bus address is pre-allocated for the external memory; and accessing the bus address through the data control bus. Embodiments of the present application solve the problem in the prior art that a computer is prone to memory shortage during operation.

Description

Technical Field

[0001] This application relates to the field of computer technologies. Specifically, this application relates to an address access method, apparatus, and electronic device. Background Art

[0002] Memory is one of the important components of a computer device, also known as internal memory or main memory, which is used to temporarily store the operation data in the processor, such as the data exchanged with the hard disk. Usually, the operation of all programs in the computer is carried out in the memory; when the program starts to run, the operating system transfers the data to be operated from the memory into the Central Processing Unit (CPU) for operation, and when the operation is completed, the CPU outputs the operation result.

[0003] The storage capacity of the memory is usually limited, and when the computer is running, a large amount of data needs to be read and written. Therefore, it is easy to cause a situation of insufficient memory, affecting the normal operation of the computer. Summary of the Invention

[0004] Embodiments of this application provide an address access method to solve the problem of insufficient memory that easily occurs in the prior art when a computer is running.

[0005] Correspondingly, embodiments of this application also provide an address access apparatus, an electronic device, and a storage medium to ensure the implementation and application of the above method.

[0006] To solve the above problems, embodiments of this application disclose an address access method, and the method includes:

[0007] Receiving a memory access request;

[0008] In response to the memory access request, obtaining the bus address of an external memory; wherein, the external memory is communicatively connected to the processor through a data control bus; the bus address is pre-allocated for the external memory;

[0009] Accessing the bus address through the data control bus.

[0010] Embodiments of this application also disclose an electronic device, including: a processor and an external memory communicatively connected to the processor through a data control bus;

[0011] Wherein, the processor is used for:

[0012] Receiving a memory access request;

[0013] In response to the memory access request, obtain the bus address of the external memory; wherein, the external memory is communicatively connected to the processor via a data control bus; the bus address is pre-allocated for the external memory;

[0014] Access the bus address via the data control bus.

[0015] An embodiment of the present application also discloses an address access device, which includes:

[0016] A request receiving module, configured to receive a memory access request;

[0017] An address obtaining module, configured to obtain the bus address of the external memory in response to the memory access request; wherein, the external memory is communicatively connected to the processor via a data control bus; the bus address is pre-allocated for the external memory;

[0018] An address access module, configured to access the bus address via the data control bus.

[0019] An embodiment of the present application also discloses an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the address access method described in the present application when executing the program.

[0020] An embodiment of the present application also discloses a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in one or more of the embodiments of the present application is implemented.

[0021] The beneficial effects brought by the technical solution provided in the embodiment of the present application are:

[0022] In the embodiment of the present application, a memory access request is received, and in response to the memory access request, the bus address of the external memory is obtained; wherein, the bus address is pre-allocated for the external memory, and subsequently, the bus address is accessed via the data control bus to perform data read and write operations, realizing the expansion of the memory capacity; the embodiment of the present application solves the problem that the computer is prone to memory shortage during operation in the prior art.

[0023] Additional aspects and advantages of the embodiments of the present application will be given in part in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. Description of the Drawings

[0024] The above and / or additional aspects and advantages of the present application will become apparent and understandable from the following description of the embodiments in conjunction with the drawings, where:

[0025] Figure 1 One of the flowcharts of the address access method provided by the embodiment of the present application;

[0026] Figure 2 Schematic diagram of the first example provided by the embodiment of the present application;

[0027] Figure 3 Another flowchart of the address access method provided by the embodiment of the present application;

[0028] Figure 4 Schematic diagram of the second example provided by the embodiment of the present application;

[0029] Figure 5 Flowchart of the second example provided by the embodiment of the present application;

[0030] Figure 6 Schematic diagram of the structure of the address access device provided by the embodiment of the present application;

[0031] Figure 7 Schematic diagram of the structure of the electronic device provided by the embodiment of the present application. Detailed implementation manners

[0032] The embodiments of the present application will be described below with reference to the accompanying drawings in the present application. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions of the embodiments of the present application.

[0033] Those skilled in the art of the present technology can understand that unless specifically stated otherwise, the singular forms "a", "an", "the" and "said" used herein may also include the plural forms. It should be further understood that the terms "comprising" and "including" used in the embodiments of the present application mean that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements, and / or components (the agent should adapt according to the actual solution), but do not exclude the implementation of other features, information, data, steps, operations, elements, components, and / or their combinations supported by the art of the present technology. It should be understood that when we say an element is "connected" or "coupled" to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used here can include wireless connection or wireless coupling. The term "and / or" used here indicates at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or implemented as "B", or implemented as "A and B".

[0034] To make the objectives, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0035] See Figure 1 , an embodiment of the present application provides an address access method. Optionally, the method is applied to an electronic device or a processor of the electronic device. The processor may be a CPU or a Graphics Processing Unit (GPU), etc. For the convenience of description, the following takes the method applied to the processor as an example to introduce the embodiment of the present application. However, it can be understood that this does not limit the application scenario of the embodiment of the present application.

[0036] The method may include the following steps:

[0037] Step 101, receive a memory access request.

[0038] Among them, the processor receives a memory access request, and the memory access request includes a data read request and a data write request, etc.

[0039] As a first example, see Figure 2 , the electronic device includes a processor 201 and a plurality of external memories (external memory 1, external memory 2,..., external memory n). The processor 201 is connected to the external memories through a data control bus.

[0040] Step 102, in response to the memory access request, obtain the bus address of the external memory; among them, the external memory is communicatively connected to the processor through a data control bus; the bus address is pre-allocated for the external memory.

[0041] After the processor receives the memory access request, it obtains the bus address of the external memory; among them, the external memory is communicatively connected to the processor through a data control bus, and the bus address is used to access the external memory through the data control bus.

[0042] Optionally, the bus protocol supported by the data control bus may be an Advanced Extendible Interface (AXI) protocol or other bus protocols; in the AXI protocol, the address phase, the control phase, and the data phase are separated, and it supports unaligned data transmission; in burst transmission, only the first address is required for transmission; the read and write data channels are separated at the same time, and it supports significant transmission access and out-of-order access, and it is easy to perform timing convergence.

[0043] Optionally, the external memory can be in the form of a component, or in the form of an RDIMM (Registered Dual In-line Memory Module), SODIMM (Small Outline Dual In-line Memory Module), etc.; specifically, the external memory is, for example, a Synchronous Dynamic Random Access Memory (SDRAM) or a Double Data Rate SDRAM (DDR SDRM); taking DDR SDRM as an example, DDR SDRM has high integration, high density, high interface bandwidth, and low price, and is widely used in some high-speed application scenarios with high requirements for memory performance.

[0044] Among them, the bus address is pre-allocated for the external memory. For example, as Figure 2 shown, when the processor detects that an external memory is plugged or placed in the memory slot and the external memory is in the enabled state, it configures bus address information for the external memory. The configuration process can be based on the capacity of the external memory or the memory space required for data read and write operations.

[0045] Step 103, access the bus address through the data control bus.

[0046] After determining the bus address information of the external memory, access the bus address through the data control bus, perform data read and write operations, and realize the expansion of the memory capacity. Exemplarily, as Figure 2 shown, for external memory 1, after the processor address allocation module pre-allocates a bus address for it, it accesses the external memory through data control bus 1.

[0047] In the embodiment of the present application, a memory access request is received, and in response to the memory access request, the bus address of the external memory is obtained; among them, the bus address is pre-allocated for the external memory, and subsequently, the bus address is accessed through the data control bus, and data read and write operations are performed to realize the expansion of the memory capacity; the embodiment of the present application solves the problem that the computer is prone to memory shortage during operation in the prior art.

[0048] See Figure 3 , the embodiment of the present application also provides an address access method. Optionally, the method is applied to a processor, and the processor can be a CPU, a GPU, etc.

[0049] Step 301: Obtain the memory information of the external memory; the memory information includes working state information and storage capacity information.

[0050] Among them, the external memory is communicatively connected to the processor through a data control bus; as an example, see Figure 2 , the processor 201 is respectively connected to multiple external memories through a data control bus, and the memory slot is used to place various types of external memories; optionally, a detection circuit for detecting the memory information of the external memory in the memory slot can be set in the electronic device.

[0051] The memory information includes working state information and storage capacity information; among them, the working state information is the information indicating whether the external memory is in a working state, and the working state information is, for example, the enable state and the disable state, and the disable state is, for example, the failure state. The storage capacity information is the storage capacity of the external memory.

[0052] Step 302: Allocate the bus address for the external memory according to the memory information.

[0053] The processor configures the bus address for the external memory; for example, according to the working state information of the external memory, select the external memory in the enabled state; then, according to the storage capacity information of the external memory in the enabled state or the memory space required for data read / write operations, allocate the bus address for it. It can be understood that if the bus address is allocated according to the memory space required for data read / write operations, the memory space corresponding to the bus address allocated for the external memory should not be greater than the storage capacity of the external memory.

[0054] In this way, the processor can flexibly configure the bus address according to the memory information of the external memory, match the storage space for the external memory, and improve the performance of the electronic device.

[0055] Step 303: Receive a memory access request.

[0056] After configuring the bus address for the external memory, the processor receives a memory access request, and the memory access request includes a data read request, a data write request, etc.

[0057] Step 304: In response to the memory access request, obtain the bus address of the external memory.

[0058] After the processor receives the memory access request, it obtains the bus address of the external memory.

[0059] Step 305: Access the bus address through the data control bus.

[0060] After determining the bus address information of the external memory, access the bus address through the data control bus, perform data read and write operations, and realize the expansion of the memory capacity.

[0061] In an alternative embodiment, the allocating the bus address for the external memory according to the memory information includes:

[0062] Determine the external memory in the enabled state according to the working state information; optionally, as Figure 2 shown, a detection circuit for memory information can be provided in the memory slot, and the detection circuit can transmit the memory information of the external memory through a hardware pin, a general interface such as an interface adopting a Serial Peripheral Interface (SPI) protocol, an Inter Integrated-Circuit (I2C) protocol, and a Universal Asynchronous Receiver / Transmitter (UART) protocol, or a preset dedicated protocol.

[0063] Allocate a bus address for the external memory in the enabled state according to the storage capacity information. The allocation process can be based on the capacity configuration of the external memory or the memory space required for data read and write operations.

[0064] In an alternative embodiment, the data control bus executes at least one of the following data protocols:

[0065] On-chip communication protocol, Serial Peripheral Interface (SPI) protocol, Inter Integrated-Circuit (I2C) protocol, and Universal Asynchronous Receiver / Transmitter (UART) protocol; among them, the on-chip communication protocol such as the Advanced eXtensible Interface (AXI) protocol, the Advanced High-performance Bus (AHB) protocol in AMBA (Advanced Microcontroller Bus Architecture), or the Advanced Peripheral Bus (APB) protocol, Wishbone protocol, Avalon protocol, etc.

[0066] As a second example, refer to Figure 4 taking the processor as the CPU, the external memory as DDR, and the data control bus adopting the AXI protocol as an example. Figure 4A specific example of Embodiment 1 of the present application is shown. Among them, the electronic device includes a CPU and multiple DDRs (DDR1 to DDRn), and the processor is connected to the external memory through a data control bus; the electronic device also includes an AXI address allocation module, an AXI S2M module, a DDR CTRL module, an AXI data control bus, an external memory detection circuit (labeled 2 in the figure), and an address access configuration circuit (labeled 1 in the figure).

[0067] Specifically, the CPU is used to: cooperate with the external memory detection circuit to obtain the storage information of the external memory; configure the AXI address allocation information; read and write the external memory through the AXI data control bus.

[0068] The AXI address allocation module is used to: enable or disable the AXI SLV interfaces corresponding to the external memory according to the AXI address information configured by the CPU, and allocate different address access spaces for these enabled AXI SLV interfaces.

[0069] The AXI S2M module is used to perform operations such as adaptation of different AXI protocols (such as AXI3 and AXI4), data bit-width conversion, and clock domain conversion.

[0070] The DDR CTRL module is used to perform operations such as interface control of the external DDR chip.

[0071] In addition, the memory slot is a slot for placing memory chips.

[0072] The AXI data control bus is the data path for the CPU to read and write the external memory.

[0073] The external memory detection circuit is used to detect memory information such as the presence and storage capacity of the external memory.

[0074] The address access configuration circuit is the information path for the CPU to configure the enabling or disabling of the AXI SLV interfaces and the access address space for the AXI address allocation module.

[0075] Combined with Figure 5 , the address access process mainly includes the following steps:

[0076] Step 501, the power-on initialization of the electronic device system is completed;

[0077] Step 502, the CPU obtains information such as whether there is a DDR memory in the memory slot and the memory size through the memory detection circuit;

[0078] Step 503, the CPU calculates the AXI SLV bus address information based on the obtained DDR memory information.

[0079] Take memory slot 1 and memory slot 2 as examples; among them, the storage capacity of external memory 1 is 1G, and it is a memory in the form of a component; the storage capacity of external memory 2 is 2G, and it is a memory in the form of a SODIMM, and the remaining slots are empty.

[0080] After the system is powered on and initialized, the CPU obtains the above memory information through the memory detection circuit;

[0081] Then, the addresses in the range of 0x4000_0000 to 0x3FFF_FFFF, with a size of 1G, are assigned to external memory 1; the addresses in the range of 0x8000_0000 to 0x7FFF_FFFF, with a size of 2G, are assigned to external memory 2.

[0082] Step 504, the CPU sends the above information to the AXI address allocation module through the configuration circuit, and this module performs address allocation;

[0083] Step 505, after the configuration is completed, the CPU can access the external DDR through the AXI data control bus.

[0084] In the embodiment of the present application, a bus address is allocated to the external memory. Subsequently, when receiving a memory access request, the bus address of the external memory is obtained, and through the data control bus, the bus address is accessed to perform data read and write operations, realizing the expansion of the memory capacity; according to the memory information of the external memory, the bus address is flexibly configured to match the storage space for the external memory, improving the performance of the electronic device.

[0085] Based on the same principle as the method provided in the embodiment of the present application, the embodiment of the present application also provides an electronic device, as Figure 2 shown, the electronic device includes:

[0086] A processor 201 and external memories (external memory 1, external memory 2,..., external memory n) communicatively connected to the processor through a data control bus;

[0087] Wherein, the processing 201 is used for:

[0088] Receiving a memory access request, the memory access request includes a data read request, a data write request, etc.;

[0089] In response to the memory access request, obtaining the bus address of the external memory; wherein, the external memory is communicatively connected to the processor 201 through a data control bus;

[0090] The bus address is pre-allocated for the external memory; after the processor 201 receives a memory access request, it obtains the bus address of the external memory; wherein, the external memory is communicatively connected to the processor 201 via a data control bus, and the bus address is used to access the external memory via the data control bus.

[0091] Optionally, the bus protocol supported by the data control bus may be the AXI protocol or other bus protocols; in the AXI protocol, the address phase, control phase, and data phase are separated, and it supports unaligned data transmission; in burst transmission, only the first address is required for transmission; the read and write data channels are separated simultaneously, and it supports significant transmission access and out-of-order access, making it easy to perform timing convergence.

[0092] Optionally, the external memory may be in the form of a Component, or in the form of RDIMM, SODIMM, etc.; specifically, the external memory is, for example, SDRAM or DDR SDRM; taking DDR SDRM as an example, DDR SDRM has high integration, high density, high interface bandwidth, and low price, and is widely used in some high-speed application scenarios with high requirements for memory performance.

[0093] Wherein, the bus address is pre-allocated for the external memory, for example, as Figure 2 shown, when the processor 201 detects that an external memory is plugged into the memory slot and the external memory is in the enabled state, it configures the bus address information for the external memory. The configuration process can be based on the capacity of the external memory, or on the memory space required for data read and write operations.

[0094] Access the bus address via the data control bus.

[0095] After determining the bus address information of the external memory, access the bus address via the data control bus, perform data read and write operations, and achieve the expansion of the memory capacity. Exemplarily, as Figure 2 shown, for the external memory 1, after the processor 201 address allocation module pre-allocates a bus address for it, it accesses the external memory via the data control bus 1.

[0096] Optionally, in the embodiments of the present application, the processor 201 is further configured to:

[0097] Before receiving a memory access request, obtain the memory information of the external memory; the memory information includes working state information and storage capacity information;

[0098] Allocate the bus address for the external memory according to the memory information.

[0099] The memory information includes working state information and storage capacity information; wherein, the working state information is the information indicating whether the external memory is in a working state, and the working state information is, for example, the enable state and the disable state, and the disable state is, for example, the failure state. The storage capacity information is the storage capacity of the external memory.

[0100] The processor 201 configures a bus address for the external memory; for example, according to the working state information of the external memory, it selects the external memory in the enable state; then, according to the storage capacity information of the external memory in the enable state or the memory space required for data read / write operations, it allocates a bus address for it. It can be understood that if the bus address is allocated according to the memory space required for data read / write operations, the memory space corresponding to the bus address allocated for the external memory should not be greater than the storage capacity of the external memory.

[0101] Optionally, in the embodiment of the present application, the processor 201 is communicatively connected to at least two of the external memories. In this way, the processor 201 can flexibly configure the bus address according to the memory information of the external memory, match the storage space for the external memory, and improve the performance of the electronic device; and the external memories can be of different types. In this way, unified control of different interfaces of different types of external memories can be achieved through the data control bus.

[0102] Optionally, in the embodiment of the present application, the electronic device includes: a memory slot connected to the external memory; the memory slot is a slot for placing a memory chip;

[0103] The memory slot is communicatively connected to the processor 201 through an external memory detection circuit, and the external memory detection circuit is used to detect memory information such as the presence and storage capacity size of the external memory.

[0104] In the embodiment of the present application, the processor 201 allocates a bus address for the external memory. When receiving a memory access request subsequently, it obtains the bus address of the external memory, accesses the bus address through the data control bus, and performs data read / write operations to realize the expansion of the memory capacity; according to the memory information of the external memory, it flexibly configures the bus address, matches the storage space for the external memory, and improves the performance of the electronic device.

[0105] Based on the same principle as the method provided in the embodiment of the present application, the embodiment of the present application also provides an address access device, as Figure 6 shown, the device includes:

[0106] A request receiving module 601, configured to receive a memory access request;

[0107] An address acquisition module 602, configured to acquire a bus address of an external memory in response to the memory access request; wherein, the external memory is communicatively connected to the processor via a data control bus; the bus address is pre-allocated for the external memory;

[0108] An address access module 603, configured to access the bus address via the data control bus.

[0109] Optionally, in an embodiment of the present application, the apparatus further includes:

[0110] An information acquisition module, configured to acquire memory information of the external memory; the memory information includes working state information and storage capacity information;

[0111] An address allocation module, configured to allocate the bus address for the external memory according to the memory information.

[0112] Optionally, in an embodiment of the present application, the address allocation module is configured to:

[0113] Determine the external memory in an enabled state according to the working state information;

[0114] Allocate a bus address for the external memory in the enabled state according to the storage capacity information.

[0115] Optionally, in an embodiment of the present application, the data control bus executes at least one of the following data protocols:

[0116] On-chip communication protocol, Serial Peripheral Interface (SPI) protocol, Inter-Integrated Circuit (I2C) protocol, and Universal Asynchronous Receiver / Transmitter (UART) protocol.

[0117] The address access apparatus provided in the embodiment of the present application can implement Figures 1 to 5 each process implemented in the method embodiment, and for the sake of brevity, details are not described herein again.

[0118] In the address access apparatus provided in the present application, the address allocation module allocates a bus address for the external memory. When the subsequent request receiving module 601 receives a memory access request, the address acquisition module 602 acquires the bus address of the external memory, and the address access module 603 accesses the bus address via the data control bus to perform data read and write operations, thereby realizing the expansion of the memory capacity; according to the memory information of the external memory, the bus address is flexibly configured to match a storage space for the external memory, improving the performance of the electronic device.

[0119] The address access device according to the embodiment of the present application can execute the address access method provided by the embodiment of the present application, and their implementation principles are similar. The actions performed by each module and unit in the address access device in each embodiment of the present application correspond to the steps in the address access method in each embodiment of the present application. For the detailed function descriptions of each module of the address access device, reference can specifically be made to the descriptions in the corresponding address access method shown above, and details will not be repeated here.

[0120] Based on the same principle as the method shown in the embodiment of the present application, the embodiment of the present application further provides an electronic device, which may include, but is not limited to: a processor and a memory; the memory is used to store a computer program; the processor is used to execute the address access method shown in any optional embodiment of the present application by calling the computer program. Compared with the prior art, when receiving a memory access request, in response to the memory access request, obtaining the bus address of an external memory; wherein, the bus address is pre-allocated for the external memory, and subsequently accessing the bus address through the data control bus to perform data read and write operations to realize the expansion of the memory capacity; the embodiment of the present application solves the problem that a computer is prone to memory shortage during operation in the prior art.

[0121] In an optional embodiment, an electronic device is further provided, as Figure 7 shown Figure 7 The electronic device 7000 shown includes: a processor 7001 and a memory 7003. Among them, the processor 7001 and the memory 7003 are connected, such as through a bus 7002. Optionally, the electronic device 7000 may further include a transceiver 7004, and the transceiver 7004 may be used for data interaction between this electronic device and other electronic devices, such as data sending and / or data receiving, etc. It should be noted that in practical applications, the transceiver 7004 is not limited to one, and the structure of the electronic device 7000 does not constitute a limitation to the embodiment of the present application.

[0122] The processor 7001 can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules, and circuits described in connection with the disclosure of this application. The processor 7001 can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0123] The bus 7002 can include a path for transmitting information between the above components. The bus 7002 can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus 7002 can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 7 only a thick line is used to represent it herein, but it does not mean that there is only one bus or one type of bus.

[0124] The memory 7003 can be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can also be an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, which is not limited herein.

[0125] The memory 7003 is used to store the computer program for implementing the embodiments of the present application, and is controlled by the processor 7001 to execute. The processor 7001 is used to execute the computer program stored in the memory 7003 to implement the steps shown in the foregoing method embodiments.

[0126] Among them, the electronic device includes but is not limited to: mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The illustrated electronic device is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present application.

[0127] The embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps and corresponding contents shown in the foregoing method embodiments can be implemented.

[0128] The embodiments of the present application also provide a computer program product, including a computer program. When the computer program is executed by a processor, the steps and corresponding contents shown in the foregoing method embodiments can be implemented.

[0129] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than the illustrated or textually described order.

[0130] It should be understood that although the flowchart in the embodiments of the present application indicates each operation step by an arrow, the execution order of these steps is not limited by the order indicated by the arrow. Unless clearly stated in this article, in some implementation scenarios of the embodiments of the present application, the implementation steps in each flowchart can be executed in other orders according to requirements. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage among these sub-steps or stages can also be executed at different times. In the scenario where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and the embodiments of the present application do not limit this.

[0131] The above are only optional implementation manners of some implementation scenarios of the present application. It should be noted that for those of ordinary skill in the art, without departing from the technical concept of the solution of the present application, other similar implementation means based on the technical idea of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. An address access method, characterized in that, including: Receiving a memory access request; In response to the memory access request, obtaining a bus address of an external memory; wherein, the external memory is communicatively connected to the processor via a data control bus; the bus address is pre-allocated for the external memory; Accessing the bus address via the data control bus; Wherein, before receiving the memory access request, the method includes: Obtaining memory information of the external memory; the memory information includes working state information and storage capacity information; wherein, the working state information indicates that the external memory is in an enabled state or a disabled state; Allocating the bus address for the external memory according to the memory information; Wherein, allocating the bus address for the external memory according to the memory information includes: Determining the external memory in the enabled state according to the working state information; Allocating a bus address for the external memory in the enabled state according to the storage capacity information.

2. The address access method according to claim 1, characterized in that The data control bus executes at least one of the following data protocols: On-chip communication protocol, Serial Peripheral Interface (SPI) protocol, Inter-Integrated Circuit (I2C) protocol, and Universal Asynchronous Receiver / Transmitter (UART) protocol.

3. An electronic device, characterized in that, including: A processor and an external memory communicatively connected to the processor via a data control bus; Wherein, the processor is configured to: Receive a memory access request; In response to the memory access request, obtain a bus address of the external memory; wherein, the external memory is communicatively connected to the processor via a data control bus; the bus address is pre-allocated for the external memory; Access the bus address via the data control bus; Wherein, the processor is further configured to: Before receiving the memory access request, obtain memory information of the external memory; the memory information includes working state information and storage capacity information; wherein, the working state information indicates that the external memory is in an enabled state or a disabled state; Allocate the bus address for the external memory according to the memory information; Wherein, the processor is further configured to: Determine the external memory in the enabled state according to the working state information; Allocate a bus address for the external memory in the enabled state according to the storage capacity information.

4. The electronic device according to claim 3, characterized in that, The processor is communicatively connected to at least two of the external memories.

5. The electronic device according to claim 3, characterized in that, The electronic device includes: a memory slot connected to the external memory; The memory slot is communicatively connected to the processor via an external memory detection line.

6. An address access device, characterized in that, including: A request receiving module, configured to receive a memory access request; An address obtaining module, configured to obtain a bus address of an external memory in response to the memory access request; wherein, the external memory is communicatively connected to the processor via a data control bus; the bus address is pre-allocated for the external memory; An address accessing module, configured to access the bus address via the data control bus; Wherein, the apparatus further includes: An information acquisition module, configured to acquire memory information of the external memory; the memory information includes working state information and storage capacity information; wherein, the working state information indicates that the external memory is in an enabled state or a disabled state; An address allocation module, configured to allocate the bus address for the external memory according to the memory information; Wherein, the address allocation module is configured to: Determine the external memory in the enabled state according to the working state information; Allocate a bus address for the external memory in the enabled state according to the storage capacity information.

7. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the method according to claim 1 or 2 is implemented.

Images