An inductance layout generation method and device

Abstract

The application discloses an inductor layout generation method and device, relates to the technical field of inductor design, and mainly aims to realize inductor self-customization and improve inductor layout generation efficiency. The main technical scheme comprises the following steps: selecting a planar spiral structure corresponding to the inductor type of a to-be-designed inductor; setting the number of spiral turns of the planar spiral structure and layout design parameter values; calling N layout design models corresponding to the number of spiral turns to process the layout design parameter values, so as to obtain layout drawing coordinate data, wherein different numbers of spiral turns each have a corresponding layout design model, and N is an integer greater than or equal to 1; and generating an inductor layout of the to-be-designed inductor based on the layout drawing coordinate data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of inductance design, and in particular to an inductance layout generation method and device. BACKGROUND

[0002] On-chip inductance is a key device in the design of radio frequency integrated circuit chips. In the design of most radio frequency chips, various design requirements are proposed for the on-chip inductance inside the chips. Such various design requirements often cannot be met by the on-chip inductance produced by each manufacturer, and the on-chip inductance needs to be customized according to the various design requirements.

[0003] The key point of on-chip inductance customization lies in the generation of inductance layout. In the current inductance layout generation process, the inductance layout needs to be adjusted constantly, and each adjustment is basically manually drawn based on the layout drawing experience of the designer. Such a way of manually generating inductance layout by the designer is not only limited by the layout drawing experience of the designer, but also consumes a lot of time, resulting in low efficiency of inductance layout generation. SUMMARY

[0004] Therefore, the present application provides an inductance layout generation method and device, which aims to realize inductance customization and improve the efficiency of inductance layout generation.

[0005] In order to achieve the above purpose, the present application mainly provides the following technical solutions:

[0006] In a first aspect, the present application provides an inductance layout generation method, which comprises:

[0007] selecting a planar spiral structure corresponding to the inductance type of a to-be-designed inductance;

[0008] setting the number of spiral turns and layout design parameter values of the planar spiral structure;

[0009] calling N layout design models corresponding to the number of spiral turns to process the layout design parameter values, to obtain layout drawing coordinate data, wherein different numbers of spiral turns each have a corresponding layout design model, and N is an integer greater than or equal to 1;

[0010] generating an inductance layout of the to-be-designed inductance based on the layout drawing coordinate data.

[0011] In a second aspect, the present application provides an inductance layout generation device, which comprises:

[0012] a selection unit configured to select a planar spiral structure corresponding to the inductance type of a to-be-designed inductance;

[0013] The setting unit is configured to set the number of turns of the planar spiral structure and a layout design parameter value;

[0014] The calling unit is configured to call N layout design models corresponding to the number of turns to process the layout design parameter value, to obtain layout drawing coordinate data, wherein different numbers of turns each have a corresponding layout design model, and N is an integer greater than or equal to 1.

[0015] The generating unit is configured to generate an inductance layout of the inductance to be designed based on the layout drawing coordinate data.

[0016] In a third aspect, the present application provides a computer readable storage medium, the storage medium comprising a stored program, wherein the program controls a device where the storage medium is located to execute the inductance layout generation method of the first aspect when the program is running.

[0017] In a fourth aspect, the present application provides an electronic device, the electronic device comprising:

[0018] A memory is configured to store a program;

[0019] A processor is coupled to the memory and configured to run the program to execute the inductance layout generation method of the first aspect.

[0020] According to the above technical solution, the inductance layout generation method and device provided by the present application, when there is a demand to generate an inductance layout for an inductance to be designed, a planar spiral structure corresponding to the inductance type of the inductance to be designed is selected, and the number of turns of the planar spiral structure and a layout design parameter value are set. Then, N layout design models corresponding to the number of turns are called to process the layout design parameter value, to obtain layout drawing coordinate data. Finally, the inductance layout of the inductance to be designed is generated based on the layout drawing coordinate data. As can be seen, in the scheme provided by the present application, when it is necessary to generate an inductance layout for an inductance to be designed, a layout design model corresponding to the number of turns of the inductance to be designed is called to process the layout design parameter value of the inductance to be designed, so that the layout drawing coordinate data of the generated inductance layout can be obtained, and the inductance layout can be generated according to the layout drawing coordinate data. The degree of human intervention in the entire inductance layout generation process is low, and therefore, the scheme provided by the present application can realize inductance customization while improving the inductance layout generation efficiency.

[0021] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described below. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0023] Figure 1 A flow chart of a method for generating an inductor layout according to an embodiment of the present application is shown;

[0024] Figure 2 A processing sequence diagram of a layout design model according to an embodiment of the present application is shown;

[0025] Figure 3 A schematic diagram of an inductor layout of a differential inductor according to an embodiment of the present application is shown;

[0026] Figure 4 A flow chart of a method for generating an inductor layout according to another embodiment of the present application is shown;

[0027] Figure 5 A structural schematic diagram of an inductor layout generation device according to an embodiment of the present application is shown;

[0028] Figure 6 A structural schematic diagram of an inductor layout generation device according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] Exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0030] With the rapid development of radio frequency communication technology, radio frequency integrated circuit design has become one of the most important branches in chip design. On-chip inductors are the key devices in the design of radio frequency integrated circuit chips. In the design of most radio frequency chips, various design requirements are proposed for the internal on-chip inductors. Such diversified design requirements often cannot be met by the finished on-chip inductors produced by each manufacturer, and the on-chip inductors need to be customized according to the diversified design requirements.

[0031] The in-chip inductor self-designing focuses on the generation of the inductor layout. At present, the existing inductor layout generation process is basically as follows: a designer manually draws a preliminary inductor layout according to the design requirements of the inductor and based on the layout drawing experience of the designer. Then, electromagnetic simulation is performed on the current inductor to determine the characteristic parameters such as inductance value and quality factor of the current inductor. Then, it is determined whether the characteristic parameters of the current inductor meet the expected requirements. In the case where the characteristic parameters meet the expected requirements, the current inductor is used as the inductor for the circuit chip. In the case where the characteristic parameters do not meet the expected requirements, the designer redesigns based on the preliminary inductor layout and updates the new inductor layout based on the experience of the designer. Then, electromagnetic simulation is performed on the current inductor again to determine the characteristic parameters such as inductance value and quality factor of the current inductor, and it is determined whether the characteristic parameters of the current inductor meet the expected requirements, until the characteristic parameters of the current inductor meet the expected requirements.

[0032] It can be seen that in the current inductor layout generation process, the inductor layout needs to be adjusted constantly, and each adjustment is basically manually drawn based on the layout drawing experience of the designer. This way of manually generating the inductor layout by the designer is not only limited by the layout drawing experience of the designer, but also consumes a lot of time, resulting in low inductor layout generation efficiency.

[0033] In order to realize inductor self-designing while improving the inductor layout generation efficiency, the embodiments of the present application provide an inductor layout generation method and device, which will be described in detail below.

[0034] As shown in Figure 1 The embodiments of the present application provide an inductor layout generation method, which mainly includes:

[0035] 101、Select a planar spiral structure corresponding to the inductor type of the inductor to be designed.

[0036] In actual application, any on-chip inductor that needs to be deployed in the chip of the radio frequency integrated circuit can be used as the inductor to be designed. The on-chip inductors of different inductor types have different planar spiral structures, so after determining the inductor to be designed, a planar spiral structure corresponding to the inductor type of the inductor to be designed needs to be selected.

[0037] The inductance type of the on-chip inductor includes single-ended inductance and differential inductance. The on-chip inductors of the two inductance types have different planar spiral structures. When generating the inductance layout of the designed inductor, the planar spiral structure corresponding to the inductance type of the inductor needs to be generated. In addition, it should be noted that the specific planar shape of the planar spiral structure can be determined based on business needs, which is not limited in the embodiment. Optionally, the planar spiral structure is a planar octagonal planar spiral structure.

[0038] 102. Set the number of spiral turns of the planar spiral structure and the layout design parameter value.

[0039] After selecting the planar spiral structure, the number of spiral turns of the planar spiral structure and the layout design parameter value need to be set. The number of spiral turns of the planar spiral structure and the layout design parameter value are the basis for generating the inductance layout.

[0040] The number of spiral turns is used to define the number of turns of the planar spiral structure, and the specific value can be determined based on business needs, which is not limited in the embodiment. Optionally, the number of spiral turns can be 1, 1.5, 2, 2.5, etc.

[0041] The layout design parameter value includes at least one of the following: the line width of each spiral turn, the inner diameter of the planar spiral structure, the outer diameter of the planar spiral structure, the spacing between adjacent two spiral turns, the line width step value of the spiral turn, the spacing step value of the spiral turn, the width-length ratio of the planar spiral structure, and the length of at least one target side of the planar spiral structure. It can be seen that the layout design parameter value is related to the number of spiral turns.

[0042] For example, the number of spiral turns is set to 2. The layout design parameter value includes: the line width of the first spiral turn, the line width of the second spiral turn, the inner diameter of the planar spiral structure, the spacing between the two spiral turns, and the width-length ratio of the planar spiral structure.

[0043] In order to improve the convenience of generating the inductance layout, the designer can be prompted to input the number of spiral turns and the layout design parameter value through an interactive interface, and the number of spiral turns and the layout design parameter value obtained by the interactive interface are set as the number of spiral turns and the layout design parameter value of the planar spiral structure.

[0044] It should be noted that when the inductance layout is generated for the first time, the number of spiral turns and the layout design parameter value can be set based on the number of spiral turns and the layout design parameter value input by the designer in the interactive interface. When the inductance layout is generated for the second time, the number of spiral turns and the layout design parameter value can be set in the following three ways: first, the number of spiral turns and the layout design parameter value can be set based on the number of spiral turns and the layout design parameter value input by the designer in the interactive interface; second, adjust the number of spiral turns and the layout design parameter value used to generate the inductance layout last time, and set the adjusted number of spiral turns and the layout design parameter value as the number of spiral turns and the layout design parameter value of the planar spiral structure; third, adjust the number of spiral turns and the layout design parameter value used to generate the inductance layout last time, and display the adjusted number of spiral turns and the layout design parameter value for the designer to modify and confirm, and set the number of spiral turns and the layout design parameter value modified and confirmed by the designer as the number of spiral turns and the layout design parameter value of the planar spiral structure.

[0045] 103. Call N layout design models corresponding to the number of spiral turns to process the layout design parameter value, and obtain layout drawing coordinate data.

[0046] In order to reduce the intervention of manual inductance layout generation and improve the efficiency of inductance layout generation, a plurality of layout design models are constructed in advance, each of which is used to determine the layout drawing coordinate data of at least one drawing object in the planar spiral structure, and different layout design models correspond to different drawing objects. Here, N is an integer greater than or equal to 1. The drawing object described herein includes but is not limited to the inductance angle, the line intersection point, the hole, and the joint in the planar spiral structure.

[0047] For example, the pre-constructed layout design model includes an inductance angle design model, a cross position design model, a punching design model, and an inductance joint design model. The drawing object of the inductance angle design model is the inductance angle, which is used to determine the layout drawing coordinate data of the inductance angle of each spiral turn in the planar spiral structure. The drawing object of the cross position design model is the line intersection position, which is used to determine the layout drawing coordinate data of the line intersection position of each spiral turn in the planar spiral structure. The drawing object of the punching design model is the hole, which is a hole for the line connection position, and the hole is used to realize the line connection of the line intersection position, and is used to determine the layout drawing coordinate data of the hole of each spiral turn in the planar spiral structure. The drawing object of the inductance joint design model is the plug, which is used to determine the layout drawing coordinate data of the inductance joint in the planar spiral structure.

[0048] Different numbers of spiral turns each have a corresponding layout design model. That is, different numbers of spiral turns involve different drawing objects in the planar spiral structure, so N layout design models corresponding to the number of spiral turns are called to process the layout design parameter value.

[0049] Exemplarily, the pre-constructed layout design models include an inductance angle design model, a crossing position design model, a punching design model, and an inductance joint design model. As shown in Figure 2 the inductance to be designed is a differential inductance, the inductance angle design model and the inductance joint design model need to be called when the number of spiral turns is 1. The inductance angle design model, the crossing position design model, the punching design model, and the inductance joint design model need to be called when the number of spiral turns is an odd number not equal to 1. The inductance angle design model, the crossing position design model, the punching design model, and the inductance joint design model need to be called when the number of spiral turns is an even number.

[0050] After determining the layout design models that need to be called, N layout design models corresponding to the number of spiral turns are called to process the layout design parameter values to obtain layout drawing coordinate data. The process of calling N layout design models corresponding to the number of spiral turns to process the layout design parameter values to obtain layout drawing coordinate data is described below, which includes the following steps one to four:

[0051] Step one, determining the processing order of the N layout design models and the target layout design parameter values corresponding to each layout design model in the layout design parameter values.

[0052] Since the processing process of some layout design models needs to use the data processed by other layout design models, the processing order of the N layout design models needs to be determined. Exemplarily, the inductance angle design model processes the layout design parameter values to obtain inductance angle coordinate data, and this inductance angle coordinate data is the prerequisite data for the crossing position design model to calculate the line crossing position. Therefore, the processing order of the inductance angle design model needs to be set before the crossing position design model.

[0053] Since some layout design models do not use all the set layout design parameter values in the processing process, in order to enable the layout design model to process the layout design parameter values in a targeted manner, the target layout design parameter values corresponding to each layout design model in the layout design parameter values are needed.

[0054] Exemplarily, as shown in Figure 2 the processing order of the layout design models corresponding to various numbers of spiral turns is shown by arrows in Figure 2 . For example, for a differential inductance, the order of each model from front to back in the processing order is: the inductance angle design model, the crossing position design model, the punching design model, and the inductance joint design model when the number of spiral turns is an odd number.

[0055] Step two, the first layout design model in the processing sequence processes the corresponding target layout design parameter value to obtain the target coordinate data of the first layout design model in the processing sequence.

[0056] Figure 2 For each layout design model in the case of differential electric inductance and odd number of spiral turns that is not 1, the first layout design model is an inductance angle design model, which processes the image layout design parameter values: the line width of the first spiral region, the line width of the second spiral turn, the inner diameter of the planar spiral structure, the spacing between the two spiral turns, and the width-length ratio of the planar spiral structure. The target layout design parameter value corresponding to the inductance angle design model is determined as the line width of the first spiral region, the line width of the second spiral turn, the inner diameter of the planar spiral structure, the spacing between the two spiral turns, and the width-length ratio of the planar spiral structure. The layout drawing coordinate data of the inductance angle is obtained, wherein the layout drawing coordinate data of the inductance angle includes coordinate points corresponding to each inductance angle of each spiral turn, and based on the layout drawing coordinate data of the inductance angle, the overall framework of the planar spiral structure can be drawn. As shown in Figure 3 For example, the inductance angle design model processes the corresponding target layout design parameter value to obtain data including coordinate points corresponding to angles a and b.

[0057] Step three, the layout design models other than the first in the processing sequence process their respective target layout design parameter values and the target coordinate data of the layout design models before them in the processing sequence to obtain the target coordinate data of the layout design models other than the first in the processing sequence.

[0058] Figure 2 For each layout design model in the case of differential electric inductance and odd number of spiral turns that is not 1, after the inductance angle design model obtains the layout drawing coordinate data of the inductance angle, the intersection position design model processes the layout drawing coordinate data of the inductance angle to obtain coordinate points corresponding to the line intersection position. As shown in Figure 3 For example, the intersection position design model processes the corresponding target layout design parameter value to obtain data including coordinate points corresponding to c and d. After the intersection point is determined, the hole design model determines the coordinate corresponding to the hole based on the coordinate points corresponding to the line intersection position and the line width, wherein the hole design model can determine the number of holes based on the line width, and then determine the coordinate points corresponding to the holes based on the coordinate points corresponding to the line intersection position. The function of the hole is to realize the connection of the intersecting lines. As shown in Figure 3 For example, the hole design model processes the corresponding target layout design parameter value to obtain data including coordinate points corresponding to e1-e4. Finally, the inductance joint design model determines the coordinate corresponding to the joint based on the coordinate position of the hole, and the joint realizes the connection between the on-chip inductance and other elements in the chip. As shown inFigure 3 As shown, the data obtained by the inductance joint design model processing its corresponding target layout design parameter value includes the corresponding coordinate point of f.

[0059] Step four, the target coordinate data of the N layout design models is summarized to obtain the layout drawing coordinate data.

[0060] In the process of summarizing the target coordinate data of each layout design model, the corresponding coordinate points of each drawing object are mainly summarized to draw the inductance layout using each drawing object and the corresponding coordinate points of each drawing object.

[0061] 104, based on the layout drawing coordinate data, the inductance layout of the inductance to be designed is generated.

[0062] In practical application, the specific process of generating the inductance layout of the inductance to be designed based on the layout drawing coordinate data includes the following steps one to two:

[0063] Step one, the coordinate points of the drawing objects included in the layout drawing coordinate data are calibrated.

[0064] The coordinates corresponding to the coordinate points of the drawing objects included in the layout drawing coordinate data should all be integer multiples of the grid points, otherwise the manufacturing factory will not be able to realize the on-chip inductance according to the layout drawing coordinate data, so the preset grid points are needed to correct the coordinate points of the drawing objects included in the layout drawing coordinate data.

[0065] The specific correction process is: for each coordinate point in the layout drawing coordinate data, the quotient of the coordinate of the coordinate point and the preset grid point is taken, and the product between the grid point and the integer result is determined. Specifically, the preset grid point can be determined based on business needs, for example, the grid point is 0.1, that is, the corrected coordinates should all be integer multiples of 0.1.

[0066] Step two, based on the coordinate points of the drawing objects in the calibrated layout drawing coordinate data, the inductance layout is generated.

[0067] In the process of generating the inductance layout, the position relationship between the coordinate points of the same drawing object and the position relationship between the coordinate points of different drawing objects are mainly used to draw the inductance layout.

[0068] Exemplarily, Figure 2 The layout drawing coordinate data obtained by each layout design model in the case of differential inductance and the number of spiral turns being an odd number other than 1 is drawn to form an inductance layout as shown in Figure 3

[0069] ​The inductor layout generation method provided by the embodiment of the present application, when there is a demand for generating an inductor layout for a to-be-designed inductor, selects a planar spiral structure corresponding to the inductance type of the to-be-designed inductor, and sets the number of spiral turns of the planar spiral structure and the layout design parameter value. Then, N layout design models corresponding to the number of spiral turns are called to process the layout design parameter value, and layout drawing coordinate data is obtained. Finally, the inductor layout of the to-be-designed inductor is generated based on the layout drawing coordinate data. It can be seen that, in the scheme provided by the embodiment of the present application, when it is necessary to generate an inductor layout for a to-be-designed inductor, the layout design model corresponding to the number of spiral turns of the to-be-designed inductor is called to process the layout design parameter value of the to-be-designed inductor, so that the layout drawing coordinate data of the generated inductor layout can be obtained, and the inductor layout can be generated according to the layout drawing coordinate data. The degree of human intervention in the entire inductor layout generation process is low, and therefore, the scheme provided by the embodiment of the present application can realize inductor customization while improving the inductor layout generation efficiency.

[0070] Further, according to the method shown in FIG. 8, another embodiment of the present application further provides an inductor layout generation method, as shown in FIG. 9, which mainly includes the following steps. Figure 1 Figure 4

[0071] 201, constructing at least one layout design model.

[0072] Each layout design model is respectively used to determine the layout drawing coordinate data of at least one drawing object involved in the planar spiral structure. The layout design model includes at least one of the following models: an inductance angle design model, a cross position design model, a punching design model, and an inductor joint design model; wherein the inductance angle design model is used to determine the layout drawing coordinate data of the inductance angle of each spiral turn in the planar spiral structure, the cross position design model is used to determine the layout drawing coordinate data of the cross position of each spiral turn in the planar spiral structure, the punching design model is used to determine the layout drawing coordinate data of the hole of each spiral turn in the planar spiral structure, and the inductor joint design model is used to determine the layout drawing coordinate data of the inductor joint in the planar spiral structure.

[0073] 202, detecting whether there is a demand for inductor layout design for a to-be-designed inductor, if there is, executing step 203, otherwise, continuing to execute the present step.

[0074] 203, selecting a planar spiral structure corresponding to the inductance type of the to-be-designed inductor.

[0075] 204, setting the number of spiral turns of the planar spiral structure and the layout design parameter value.

[0076] 205, detecting whether the layout design parameter value exceeds a preset value range; if it exceeds, executing step 206; otherwise, executing step 207. ​​

[0077] In the process of generating the inductor layout, since each layout design model only processes the layout design parameter values within the preset value range, once the layout design parameter values exceed the preset value range, the processing process of the layout design model will report an error, affecting the generation progress of the inductor layout. Therefore, in order to avoid the error report of calling each layout design model and interrupting the generation process of the inductor layout, it is necessary to detect whether the layout design parameter values exceed the preset value range.

[0078] It should be noted that each layout design parameter value has its corresponding preset value range. In the process of monitoring whether the layout design parameter values exceed the preset value range, it is actually a process of whether each layout design parameter value exceeds its corresponding preset value range. If each layout design parameter value does not exceed its corresponding preset value range, step 207 is executed. If at least one of the layout design parameter values exceeds its corresponding preset value range, it means that these layout design parameter values are abnormal, and step 206 needs to be executed.

[0079] 206, issuing a prompt that the layout design parameter values are invalid, and ending the current process.

[0080] 207, calling N layout design models corresponding to the number of spiral turns to process the layout design parameter values to obtain layout drawing coordinate data.

[0081] Wherein, different numbers of spiral turns each have a corresponding layout design model, and N is an integer greater than or equal to 1;

[0082] 208, generating an inductor layout of the inductor to be designed based on the layout drawing coordinate data.

[0083] In the scheme provided by the embodiment of the application, when it is necessary to generate an inductor layout for an inductor to be designed, a layout design model corresponding to the number of spiral turns of the inductor to be designed is called to process the layout design parameter values of the inductor to be designed, so that the layout drawing coordinate data of the generated inductor layout can be obtained, and the inductor layout can be generated according to the layout drawing coordinate data. The degree of human intervention in the entire generation process of the inductor layout is low. Therefore, the scheme provided by the embodiment of the application can realize inductor customization while improving the inductor layout generation efficiency. In addition, the layout design parameters are checked before the layout design model is called, and the layout design model is called only after the detection is passed, so that the error report of calling each layout design model and the interruption of the generation process of the inductor layout can be avoided.

[0084] Further, according to the above-mentioned method embodiment, another embodiment of the application further provides an inductor layout generation device, as shown in Figure 5 The device comprises:

[0085] The selecting unit 51 is configured to select a planar spiral structure corresponding to an inductance type of the inductance to be designed;

[0086] The setting unit 52 is configured to set a number of spiral turns of the planar spiral structure and a layout design parameter value;

[0087] The calling unit 53 is configured to call N layout design models corresponding to the number of spiral turns to process the layout design parameter value, to obtain layout drawing coordinate data, wherein different numbers of spiral turns each have a corresponding layout design model, and N is an integer greater than or equal to 1;

[0088] The generating unit 54 is configured to generate an inductance layout of the inductance to be designed based on the layout drawing coordinate data.

[0089] The inductance layout generation device provided in the embodiment of the present application, when there is a demand to generate an inductance layout for an inductance to be designed, selects a planar spiral structure corresponding to an inductance type of the inductance to be designed, and sets a number of spiral turns of the planar spiral structure and a layout design parameter value. Then, the calling unit 53 calls N layout design models corresponding to the number of spiral turns to process the layout design parameter value, to obtain layout drawing coordinate data. Finally, the generating unit 54 generates an inductance layout of the inductance to be designed based on the layout drawing coordinate data. It can be seen that, in the scheme provided in the embodiment of the present application, when it is needed to generate an inductance layout for an inductance to be designed, the layout design model corresponding to the number of spiral turns of the inductance to be designed is called to process the layout design parameter value of the inductance to be designed, so that the layout drawing coordinate data of the generated inductance layout can be obtained, and the inductance layout can be generated according to the layout drawing coordinate data. The degree of human intervention in the whole process of generating the inductance layout is low, and therefore, the scheme provided in the embodiment of the present application can realize inductance customization while improving the inductance layout generation efficiency.

[0090] Optionally, as shown in Figure 6 The calling unit 53 includes:

[0091] The determining module 531 is configured to determine a processing order of the N layout design models and target layout design parameter values corresponding to each layout design model in the layout design parameter value;

[0092] The first calling module 532 is configured to call a layout design model located at the first position in the processing order to process a target layout design parameter value corresponding to the layout design model, to obtain target coordinate data of the layout design model located at the first position in the processing order;

[0093] The second calling module 533 is configured to sequentially call each layout design model in the processing sequence other than the first one to process the target layout design parameter value corresponding to the layout design model and the target coordinate data of each layout design model in the processing sequence before the layout design model, to obtain the target coordinate data of each layout design model in the processing sequence other than the first one.

[0094] The summary module 534 is configured to summarize the target coordinate data of the N layout design models to obtain the layout drawing coordinate data.

[0095] Optionally, as shown in Figure 6 The generation unit 54 includes:

[0096] The calibration module 541 is configured to calibrate the coordinate point of the drawing object included in the layout drawing coordinate data.

[0097] The generation module 542 is configured to generate the inductance layout based on the coordinate point of the drawing object in the calibrated layout drawing coordinate data.

[0098] Optionally, as shown in Figure 6 The calibration module 541 is specifically configured to, for each coordinate point, perform: integer division of the coordinate of the coordinate point by a preset grid point, to determine a product between the grid point and the integer result.

[0099] Optionally, as shown in Figure 6 The device further includes:

[0100] The detection unit 55 is configured to detect whether the layout design parameter value exceeds a preset value range, and if the layout design parameter value does not exceed the preset value range, trigger the calling unit 53 to call the N layout design models corresponding to the spiral turns to process the layout design parameter value, and if the layout design parameter value exceeds the preset value range, issue a prompt that the layout design parameter value is invalid.

[0101] Optionally, as shown in Figure 6 The device further includes:

[0102] The construction unit 56 is configured to construct at least one layout design model, wherein each layout design model is used to determine the layout drawing coordinate data of at least one drawing object involved in the planar spiral structure.

[0103] Optionally, as shown in Figure 6As shown, the at least one layout design model built by the building unit 56 comprises at least one of the following models: an inductance angle design model, a crossing position design model, a punching design model, and an inductance joint design model; wherein the inductance angle design model is used to determine layout drawing coordinate data of an inductance angle of each spiral turn in the planar spiral structure, the crossing position design model is used to determine layout drawing coordinate data of a crossing position of each spiral turn in the planar spiral structure, the punching design model is used to determine layout drawing coordinate data of a hole of each spiral turn in the planar spiral structure, and the inductance joint design model is used to determine layout drawing coordinate data of an inductance joint in the planar spiral structure.

[0104] Optionally, as shown in Figure 6 The layout design parameter value set by the setting unit 52 comprises at least one of the following: a line width of each spiral turn, an inner diameter of the planar spiral structure, an outer diameter of the planar spiral structure, a spacing between adjacent two spiral turns, a line width step value of the spiral turn, a spacing step value of the spiral turn, and an aspect ratio of the planar spiral structure.

[0105] Optionally, as shown in Figure 6 The planar spiral structure selected by the selecting unit 51 is a planar octagonal planar spiral structure.

[0106] In the inductance layout generation device provided by the embodiment of the present application, the method used in the running process of each functional module can be referred to the corresponding method detailed description of the above-mentioned inductance layout generation method embodiment, which will not be described here.

[0107] Further, according to the above-mentioned embodiment, another embodiment of the present application further provides a computer readable storage medium, the storage medium comprises a stored program, wherein, when the program runs, the device where the storage medium is located executes Figure 1 and Figure 4 The inductance layout generation method.

[0108] Further, according to the above-mentioned embodiment, another embodiment of the present application further provides an electronic device, the electronic device comprises:

[0109] a memory, configured to store a program;

[0110] a processor, coupled to the memory, configured to run the program to execute Figure 1 and Figure 4 The inductance layout generation method.

[0111] In the above-mentioned embodiments, the description of each embodiment has its own emphasis, and the part not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0112] It can be understood that the related features in the above method and device can be mutually referred. In addition, "first", "second", and the like in the above embodiments are used to distinguish each embodiment, and do not represent the advantages and disadvantages of each embodiment.

[0113] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0114] The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description above. In addition, the present application is not intended to be limited to a particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the application as described herein, and any references below to specific languages are provided for disclosure of enablement of the best mode of the application.

[0115] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order not to obscure the understanding of this description.

[0116] Similarly, it is to be understood that the mechanical details of the application sometimes are presented in terms of certain spatially-related or geometrical configurations and / or descriptions. It will be apparent, however, to those skilled in the art that structures according to the present application can be

[0117] Those skilled in the art can understand that the modules in the device in the embodiments can be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and furthermore can be divided into multiple sub-modules or sub-units or sub-components. All the features disclosed in the specification (including the claims, abstract and drawings) and all the processes or units of any method or device disclosed in the specification can be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless explicitly stated otherwise, each feature disclosed in the specification (including the claims, abstract and drawings) can be replaced by alternative features providing the same, equivalent or similar functionality.

[0118] Furthermore, those skilled in the art will recognize that, while certain embodiments described herein include certain features that are not included in other embodiments, combinations of features of the different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims below, any of the claimed embodiments can be used in any combination.

[0119] Various component embodiments of the present application can be implemented in hardware, or as software modules running in one or more processors, or combinations thereof. Those skilled in the art will appreciate that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the method, apparatus and framework for running a deep neural network model according to embodiments of the present application. The present application can also be implemented as a program (e.g., computer program and computer program product) for executing any or all of the methods described herein on a device or apparatus. Such a program implementing the present application can be stored on a computer readable medium, or can be in the form of one or more signals. Such a signal can be downloaded from an Internet website, or can be available for

[0120] It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that one skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of elements or steps other than those listed in a claim. The word 'a' or 'an' preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unitary claim, several of the devices mentioned in the groups of devices can be embodied by one and the same thing or element. The usage of the words 'first','second' and 'third', etc. do not denote any order. These words are to be interpreted as names.

Claims

1. A method for generating an inductor layout, characterized in that, The method includes: Select a planar spiral structure that corresponds to the inductance type of the inductor to be designed; Set the number of spiral turns and layout design parameters of the planar spiral structure; The layout design parameter values ​​are processed by calling N layout design models corresponding to the number of spiral turns to obtain layout drawing coordinate data. Each spiral turn number has its own corresponding layout design model, and N is an integer greater than or equal to 1. Each layout design model is used to determine the layout drawing coordinate data of at least one drawing object involved in the planar spiral structure. Different layout design models correspond to different drawing objects, including inductance angles, line intersections, holes, and joints in the planar spiral structure. The process of calling N layout design models corresponding to the number of spiral turns to process the layout design parameter values ​​to obtain layout drawing coordinate data includes: determining the processing order of the N layout design models and the layout design parameters in each layout design model. The target layout design parameter values ​​corresponding to the N layout design models are calculated; the layout design model at the beginning of the processing order is called to process its corresponding target layout design parameter values ​​to obtain the target coordinate data of the layout design model at the beginning of the processing order; the layout design models not at the beginning of the processing order are called sequentially to process their respective target layout design parameter values ​​and the target coordinate data of each layout design model preceding them in the processing order to obtain the target coordinate data of each layout design model not at the beginning of the processing order; the target coordinate data of the N layout design models are summarized to obtain the layout drawing coordinate data; the layout drawing coordinate data summarizes the drawing objects of the N layout design models and the coordinate points corresponding to each drawing object; Based on the layout, coordinate data is plotted to generate the inductor layout of the inductor to be designed.

2. The method according to claim 1, characterized in that, Based on the layout, coordinate data is plotted to generate the inductor layout of the inductor to be designed, including: The coordinate points of the drawing objects included in the layout drawing coordinate data are calibrated; The inductor layout is generated based on the coordinate points of the objects drawn in the calibrated layout coordinate data.

3. The method according to claim 2, characterized in that, The coordinate points of the drawing objects included in the plot drawing coordinate data are calibrated, including: For each of the coordinate points, the following is performed: the quotient of the coordinate point and the preset grid point is rounded down, and the product between the grid point and the rounded result is determined.

4. The method according to any one of claims 1-3, characterized in that, After setting the number of spiral turns and layout design parameter values ​​of the planar spiral structure, and before calling N layout design models corresponding to the number of spiral turns to process the layout design parameter values, the method further includes: Detect whether the layout design parameter values ​​exceed the preset range; If the layout design parameter value does not exceed the preset value range, N layout design models corresponding to the number of spiral turns are called to process the layout design parameter value; If the layout design parameter value exceeds the preset value range, an invalid layout design parameter value prompt will be issued.

5. The method according to any one of claims 1-3, characterized in that, The method further includes: Construct at least one layout design model, wherein each layout design model is used to determine the layout drawing coordinate data of at least one drawing object involved in the planar spiral structure.

6. The method according to claim 5, characterized in that, The at least one layout design model includes at least one of the following models: an inductance angle design model, a crossover position design model, a hole punching design model, and an inductor connector design model; wherein, the inductance angle design model is used to determine the layout drawing coordinate data of the inductance angle of each spiral coil in the planar spiral structure, the crossover position design model is used to determine the layout drawing coordinate data of the line crossover position of each spiral coil in the planar spiral structure, the hole punching design model is used to determine the layout drawing coordinate data of the hole in each spiral coil in the planar spiral structure, and the inductor connector design model is used to determine the layout drawing coordinate data of the inductor connector in the planar spiral structure.

7. The method according to any one of claims 1-3, characterized in that, The layout design parameter values ​​include at least one of the following: the line width of each spiral loop, the inner diameter of the planar spiral structure, the outer diameter of the planar spiral structure, the spacing between two adjacent spiral loops, the line width step value of the spiral loop, the spacing step value of the spiral loop, the width-to-length ratio of the planar spiral structure, and the side length of at least one target side in the planar spiral structure. And / or, The planar spiral structure is a planar octagonal spiral structure.

8. An inductor layout generation apparatus, characterized in that, The device includes: The selection unit is used to select a planar spiral structure that corresponds to the inductance type of the inductor to be designed. The setting unit is used to set the number of spiral turns and layout design parameter values ​​of the planar spiral structure; The calling unit is used to call N layout design models corresponding to the number of spiral turns to process the layout design parameter values ​​and obtain layout drawing coordinate data. Each spiral turn number has its own corresponding layout design model, and N is an integer greater than or equal to 1. Each layout design model is used to determine the layout drawing coordinate data of at least one drawing object involved in the planar spiral structure. Different layout design models correspond to different drawing objects, including inductance angles, line intersections, holes, and joints in the planar spiral structure. Calling the N layout design models corresponding to the number of spiral turns to process the layout design parameter values ​​and obtain layout drawing coordinate data includes: determining the processing order of the N layout design models and the values ​​of each spiral design parameter. The target layout design parameter values ​​corresponding to the layout design model are obtained; the layout design model at the beginning of the processing order is called to process its corresponding target layout design parameter values, thereby obtaining the target coordinate data of the layout design model at the beginning of the processing order; the layout design models not at the beginning of the processing order are called sequentially to process their respective target layout design parameter values ​​and the target coordinate data of each layout design model preceding them in the processing order, thereby obtaining the target coordinate data of each layout design model not at the beginning of the processing order; the target coordinate data of the N layout design models are summarized to obtain the layout drawing coordinate data; the layout drawing coordinate data summarizes the drawing objects of the N layout design models and the coordinate points corresponding to each drawing object; The generation unit is used to draw coordinate data based on the layout and generate the inductor layout of the inductor to be designed.

9. A computer-readable storage medium, characterized in that, The storage medium includes a stored program, wherein, when the program is executed, it controls the device where the storage medium is located to perform the inductor layout generation method according to any one of claims 1 to 7.

10. An electronic device, characterized in that, The electronic device includes: Memory, used to store programs; A processor, coupled to the memory, is configured to run the program to perform the inductor layout generation method according to any one of claims 1 to 7.

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