Semiconductor device and method of forming the same

Abstract

The application provides a semiconductor device and a forming method thereof. The forming method comprises the following steps: providing a substrate, the substrate having a dielectric layer; etching the dielectric layer to form a first through hole and a second through hole, the bottom of the first through hole exposing a top surface of a source-drain plug layer on the substrate, and the bottom of the second through hole exposing a top surface of a gate structure on the substrate; forming an interface layer on the top surfaces of the exposed source-drain plug layer and the gate structure; forming the interface layer on the top surfaces of the source-drain plug layer and the gate structure ensures the uniform rate of an interconnection layer formed on the source-drain plug layer and the gate structure, improves the quality of the formed interconnection layer, and improves the quality of the finally formed source-drain plug layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a forming method thereof. BACKGROUND

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used. The control ability of the traditional planar device on the channel current is weak, and the short channel effect causes the leakage current, which ultimately affects the electrical performance of the semiconductor device.

[0003] In the manufacturing process of the semiconductor device, the conduction of the current is usually realized through the metal connection structure, and then the specific function of the semiconductor device is realized. Generally, there is a metal plug between different semiconductor devices, which is connected with the gate and the source / drain region respectively. After the metal plug is formed, an interconnection layer is formed on the metal plug for connection with the upper metal. However, the forming quality of the metal plug and the interconnection layer is poor at present, which leads to the semiconductor device formed also having poor electrical performance.

[0004] How to form a metal plug and an interconnection layer with high quality to ensure that the semiconductor device formed has good performance is a problem that needs to be solved at present. SUMMARY

[0005] The problem solved by the present application is to provide a semiconductor device and a forming method thereof, so that the metal plug and the interconnection layer formed have good forming quality, and the semiconductor device formed has good performance and yield.

[0006] To solve the above problems, the present application provides a semiconductor device, comprising: a substrate; a source / drain plug layer located in the substrate; a gate structure located in the substrate; a dielectric layer located on the substrate and covering the gate structure and the source / drain plug layer; a first via located in the dielectric layer and exposing a top surface of one of the source / drain plug layers at the bottom; a second via located in the dielectric layer and exposing a top surface of one of the gate structures at the bottom; an interface layer located on the top surface of the source / drain plug layer exposed by the first via and the top surface of the gate structure exposed by the second via.

[0007] Optionally, it further comprises: an interconnection layer located on the top surface of the interface layer and filling the first via and the second via.

[0008] Optionally, the thickness of the interface layer is 15-20 angstroms.

[0009] Optionally, the material of the interface layer is titanium-tungsten alloy, titanium-molybdenum alloy, tantalum-tungsten alloy or tantalum-molybdenum alloy.

[0010] Accordingly, the application provides another method for forming a semiconductor device, comprising: providing a substrate, the substrate having a dielectric layer thereon; etching the dielectric layer to form a first via and a second via, the first via exposing a top surface of a source / drain plug layer in the substrate, the second via exposing a top surface of a gate structure in the substrate; forming an interface layer on the exposed top surfaces of the source / drain plug layer and the gate structure.

[0011] Optionally, the step of forming the interface layer comprises: forming a barrier layer on the exposed top surfaces of the source / drain plug layer and the gate structure; forming a reaction layer on the barrier layer, the reaction layer and the barrier layer reacting to form the interface layer on the surfaces of the source / drain plug layer and the gate structure.

[0012] Optionally, the barrier layer is made of one or more of TiN, Ti, and TaN.

[0013] Optionally, the interface layer has a resistance less than that of the barrier layer.

[0014] Optionally, the process of forming the barrier layer is a selective growth process, an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

[0015] Optionally, the reaction layer is made of tungsten or molybdenum.

[0016] Optionally, the interface layer has a thickness of 15 Å to 20 Å.

[0017] Optionally, the interface layer is made of a titanium-tungsten alloy, a titanium-molybdenum alloy, a tantalum-tungsten alloy, or a tantalum-molybdenum alloy.

[0018] Optionally, after forming the interface layer, the method further comprises: forming an interconnection layer on the interface layer, the interconnection layer filling the first via and the second via respectively.

[0019] Compared with the prior art, the technical scheme of the application has the following advantages:

[0020] In the forming method of the application, the interface layer is formed on the top surface of the source-drain plug layer and the gate structure, so that the source-drain plug layer and the gate structure have the interface layer with the same property, which can ensure the uniform rate of the interconnection layer formed on the source-drain plug layer and the gate structure in the subsequent process of forming the interconnection layer on the top surface of the source-drain plug layer and the gate structure, avoid the existence of holes in the interconnection layer due to the unbalanced growth rate, and improve the quality of the formed interconnection layer. Meanwhile, the top surface of the source-drain plug layer is sealed due to the existence of the interface layer, which can avoid the damage of the source-drain plug layer in the subsequent process, improve the quality of the finally formed source-drain plug layer, and thus improve the performance and yield of the finally formed semiconductor device.

[0021] Further, the resistance of the interface layer is smaller than that of the barrier layer, and the resistance of the bottom of the first via and the second via is reduced due to the existence of the interface layer in the subsequent process of forming the interconnection layer on the interface layer, thereby reducing the contact resistance (Rc) / sheet resistance (Rs) of the formed semiconductor device and improving the electrical performance and use performance of the formed semiconductor device.

[0022] In the device of the application, the interface layer is located on the top surface of the source-drain plug layer exposed by the first via and the top surface of the gate structure exposed by the second via, so that the top surface of the exposed source-drain plug layer and the exposed gate structure has the interface layer with the same material property. In the subsequent process of forming the interconnection layer, the growth of the interconnection layer has the same environment, thereby ensuring the same growth rate of the interconnection layer on the top of the source-drain plug layer and the gate structure, avoiding the existence of holes in the interconnection layer due to the unbalanced growth rate, and improving the performance of the finally formed semiconductor device. Meanwhile, the top surface of the source-drain plug layer is sealed due to the existence of the interface layer, which can avoid the damage of the source-drain plug layer in the subsequent process and improve the quality of the finally formed source-drain plug layer.

[0023] Further, the material of the interface layer is metal alloy, and the resistance of the top surface of the exposed source-drain plug layer and the top surface of the exposed gate structure is reduced, thereby reducing the contact resistance (Rc) / sheet resistance (Rs) of the formed semiconductor device and improving the electrical performance and use performance of the formed semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of the semiconductor device forming process in an embodiment;

[0025] Figures 2 to 7is a structural schematic diagram of a semiconductor device forming process in an embodiment of the present application. DETAILED DESCRIPTION

[0026] At present, in the structure of COAG, an interconnection layer is formed on the source-drain plug layer and the gate structure as a contact plug, so as to realize the electrical connection between the source-drain plug layer and the gate structure and the metal layer formed on the contact plug. However, the source-drain plug layer is easy to be lost in the subsequent process, and the contact resistance (Rc) / sheet resistance (Rs) of the semiconductor device formed is large, which affects the electrical performance and usability of the semiconductor device, limits the use of the semiconductor device, and the specific structure can be referred to in Figure 1 .

[0027] Firstly, referring to Figure 1 , a substrate 100, the substrate 100 includes a substrate 101, a plurality of gate structures 102 arranged in parallel on the substrate 101, a source-drain plug layer 103 between adjacent gate structures 102, the source-drain plug layer 103 is formed on a source-drain doped layer (not shown in the figure), and the source-drain doped layer is formed in the substrate 101 on both sides of the gate structure 102; the gate structure 102 includes a gate dielectric layer (not shown in the figure), a gate layer 104, a protective layer 105 on the top of the gate layer 104, a sidewall 106 on the sidewall of the gate layer 104 and the protective layer 105; a dielectric layer 107 is located on the substrate 100 and covers the source-drain plug layer 103 and the gate structure 102; a first via 108 is located in the dielectric layer 107 and exposes the top surface of one of the source-drain plug layers 103; a second via 109 is located in the dielectric layer 107 and exposes the top surface of the gate layer 104 of one of the gate structures 102; a barrier layer 110 is located on the bottom and sidewall of the first via 108 and the second via 109; an interconnection layer 111 is located on the barrier layer 110 and fills the first via 108 and the second via 109 respectively.

[0028] The inventor found that the use performance of the semiconductor device formed by this method is poor in stability, and is easy to fail, which limits the use of the semiconductor device. This is because, on the one hand, the existence of the barrier layer 110 makes the contact resistance (Rc) / sheet resistance (Rs) of the semiconductor device formed large, which affects the electrical performance of the semiconductor device; on the other hand, in the subsequent etching process or cleaning process, the source-drain plug layer 103 is easy to be lost, which affects the quality of the semiconductor device formed; and the growth rate of the interconnection layer 111 in the first via 108 and the second via 109 is different, which causes the interconnection layer with slow growth rate to be easy to have a hole defect.

[0029] The inventors discovered that a barrier layer is formed on the top surface of the source / drain plug layer exposed at the bottom of the first via and the top surface of the gate structure exposed at the bottom of the second via. A reaction layer is formed on the barrier layer. The reaction between the barrier layer and the reaction layer forms an interface layer on the top surfaces of the source / drain plug layer and the gate structure. This ensures that the top surfaces of the source / drain plug layer and the gate structure have the same interface layer properties. This guarantees that the interconnect layer formation rate is consistent on the top surfaces of the source / drain plug layer and the gate structure during subsequent interconnect layer formation, preventing voids in the interconnect layer due to uneven growth rates and improving the quality of the formed interconnect layer. Simultaneously, the presence of the interface layer on the source / drain plug layer seals its top surface, preventing damage to the source / drain plug layer in subsequent processes and improving the quality of the final source / drain plug layer. Ultimately, this improves the performance and yield of the final semiconductor device.

[0030] The inventors also discovered that the interface layer formed by the reaction between the barrier layer and the reaction layer has a lower resistance than the barrier layer. During the subsequent formation of the interconnect layer on the interface layer, the presence of the interface layer reduces the resistance at the bottom of the first via and the second via, thereby reducing the contact resistance (Rc) / sheet resistance (Rs) of the formed semiconductor device and improving the electrical and performance characteristics of the formed semiconductor device.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figures 2 to 7 This is a schematic diagram of the semiconductor device formation process in one embodiment of the present invention.

[0033] First refer to Figure 2 A substrate 200 is provided, wherein a dielectric layer 201 is provided on the substrate 200.

[0034] In this embodiment, the substrate 200 includes a substrate 202 and a gate structure 203 located on the substrate 202.

[0035] In this embodiment, the substrate 202 is made of single-crystal silicon.

[0036] In other embodiments, the substrate 202 may also be polycrystalline silicon or amorphous silicon. The material of the substrate 202 may also be semiconductor materials such as germanium, silicon germanide, gallium arsenide, silicon-on-insulator (SOI), and germanium-on-insulator (GOI).

[0037] In this embodiment, a plurality of parallel fins (not shown) are also formed on the substrate 202, and the gate structure 203 is formed across the fins and covers part of the sidewalls and bottom surfaces of the fins.

[0038] In other embodiments, the fins can also not be formed on the substrate 202.

[0039] In this embodiment, an isolation structure (not shown) is also formed on the substrate 202, and the isolation structure covers part of the sidewalls of the fins.

[0040] In this embodiment, the isolation structure functions to form electrical isolation.

[0041] In this embodiment, the gate structure 203 includes a gate dielectric layer (not shown), a gate layer 204 on the gate dielectric layer, a protective layer 205 on the gate layer 204, and a sidewall 206 on the sidewalls of the gate layer 204 and the protective layer 205.

[0042] In this embodiment, the material of the gate dielectric layer includes high-K dielectric materials, such as oxides - Al2O3, HfO2, Ta2O5, TiO2, ZrO2, etc.

[0043] In other embodiments, the material of the gate dielectric layer can also include other dielectric materials with a dielectric constant higher than 3.9.

[0044] In this embodiment, the material of the gate layer 204 is metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.

[0045] In this embodiment, the material of the protective layer 205 includes silicon nitride or silicon oxide; in other embodiments, the material of the protective layer 205 can also be one or more combinations of silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonboron nitride (SiCBN), etc.

[0046] In this embodiment, the material of the sidewall 206 is silicon oxide; in other embodiments, the material of the sidewall 206 can also be one or more combinations of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonboron nitride (SiCBN), etc.

[0047] The sidewall 206 is used to define the position of the source / drain doped layer.

[0048] In the embodiment, the process of forming the gate structure 203 is a post-gate process, that is, a dummy gate structure is first formed on the substrate 202, and then the dummy gate structure is removed after forming the source-drain doped layer, and the gate structure 203 is formed at the position of the dummy gate structure.

[0049] In other embodiments, a pre-gate process can also be used, that is, the gate structure 203 is directly formed on the substrate 202, and no dummy gate structure is needed to occupy the position in advance.

[0050] In the embodiment, the process further includes forming a source-drain doped layer (not shown in the figure) in the substrate 202 on both sides of the gate structure 203, and forming a source-drain plug layer 207 on the source-drain doped layer, the source-drain plug layer 207 being used to realize the connection between the source-drain doped layer and an external circuit.

[0051] The material of the source-drain plug layer 207 is metal.

[0052] In the embodiment, the material of the source-drain plug layer 207 is cobalt; in other embodiments, the material of the source-drain plug layer 207 can also be different metal materials such as copper, aluminum, titanium, etc.

[0053] In the embodiment, the gate structure 203 is multiple, and is distributed in a parallel distribution manner on the substrate 202.

[0054] In the embodiment, the source-drain plug layer 207 is also located on both sides of the gate structure 203, and the number of the source-drain plug layer 207 is also multiple.

[0055] In the embodiment, the dielectric layer 201 is formed on the substrate 200, and a patterned layer (not shown in the figure) is formed on the dielectric layer 201, the patterned layer having an opening, and the position of the opening corresponding to the position of a via hole of an interconnection layer which needs to be formed in the dielectric layer in the future.

[0056] In the embodiment, before the dielectric layer 201 is formed on the substrate 200, the process further includes forming a hard mask layer 208 on the top surface of the source-drain plug layer 207, and the top surface of the hard mask layer 208 is flush with the top surface of the protective layer 205.

[0057] In the embodiment, the dielectric layer 201 is used as an intermetallic dielectric isolation material, and the material used is one or a combination of silicon carbide, silicon oxide, or silicon nitride, etc.

[0058] In the embodiment, the process of forming the dielectric layer 201 is a chemical vapor deposition process; in other embodiments, the dielectric layer 201 can also be formed by using a physical vapor deposition or an atomic layer vapor deposition.

[0059] Referring to Figure 3 etching the dielectric layer 201 to form a first via 209 and a second via 210, a bottom of the first via 209 exposes a top surface of a source / drain plug layer 207 on the substrate 200, and a bottom of the second via 210 exposes a top surface of a gate structure 203 on the substrate 200.

[0060] In this embodiment, a patterned layer (not shown in the figure) is formed on the dielectric layer 201, and the dielectric layer 201 is etched to form the first via 209 and the second via 210 using the patterned layer as a mask.

[0061] In this embodiment, the hard mask layer 208 on the top of the source / drain plug layer 207 is also etched and removed during the formation of the first via 209, so as to expose the top surface of the source / drain plug layer 207.

[0062] In this embodiment, the protective layer 205 is also etched and removed during the formation of the second via 210, so as to expose the top surface of the gate layer 204.

[0063] In this embodiment, the process of forming the first via 209 and the second via 210 is a dry etching process; in other embodiments, the process of forming the first via 209 and the second via 210 is a wet etching process, a dry etching process, or a combination of a wet etching process and a dry etching process.

[0064] In this embodiment, the reason for using a dry etching process to form the first via 209 and the second via 210 is that dry etching has strong directionality, and the etching rate in the longitudinal direction is greater than that in the lateral direction, which can ensure that the surrounding devices are not damaged during the formation of the first via 209 and the second via 210.

[0065] In this embodiment, the first via 209 and the second via 210 are not on the same horizontal line, so that part of the source / drain plug layer 207 is covered and not exposed during the formation of the first via 209 and the second via 210.

[0066] In this embodiment, the positions of the first via 209 and the second via 210 are etched according to the actual needs of the pattern design; in other embodiments, other patterns can also be formed, i.e., the positions of the first via 209 and the second via 210 are not fixed.

[0067] An interface layer is formed on the top surface of the exposed source-drain plug layer and the gate structure. The step of forming the interface layer is described in detail in Figures 4 to 5 .

[0068] An interface layer is formed on the top surface of the exposed source-drain plug layer and the gate structure. The step of forming the interface layer is described in detail in Figure 4 A barrier layer 211 is formed on the top surface of the exposed source-drain plug layer 207 and the gate structure 203.

[0069] In this embodiment, the barrier layer 211 is formed on the bottom of the first via 209 and the second via 210 respectively.

[0070] In this embodiment, the material of the barrier layer 211 is TiN.

[0071] In other embodiments, the material of the barrier layer 211 is one or a combination of TiN, Ti or TaN.

[0072] In this embodiment, the purpose of forming the barrier layer 211 is to protect the exposed source-drain plug layer 207 and the gate structure 203, and to prevent the diffusion ions in the interconnection layer from damaging the source-drain plug layer 207.

[0073] In this embodiment, the process of forming the barrier layer 211 is selective growth process; in other embodiments, the atomic layer deposition process, chemical vapor deposition process or physical vapor deposition process can also be used to form the barrier layer 211.

[0074] In this embodiment, the reason for using selective growth process to form the barrier layer 211 is that the barrier layer 211 formed by selective growth is gradually grown from the bottom of the first via 209 and the second via 210, so that the barrier layer 211 will not be formed on the sidewall of the first via 209 and the second via 210, thus it is not necessary to use etching process to remove the barrier layer 211 on the sidewall of the first via 209 and the second via 210, reducing the process flow and thus reducing the damage to the device.

[0075] An interface layer is formed on the top surface of the exposed source-drain plug layer and the gate structure. The step of forming the interface layer is described in detail in Figure 5 A reaction layer (not shown in the figure) is formed on the barrier layer 211, and the reaction layer reacts with the barrier layer 211 to form an interface layer 212 on the surface of the source-drain plug layer 207 and the gate structure 203.

[0076] In this embodiment, the reaction between the reaction layer and the barrier layer 211 causes the barrier layer 211 to be consumed, forming the interface layer 212.

[0077] The interface layer 212 has a resistance less than that of the barrier layer 211.

[0078] In this embodiment, the reaction layer reacts with the barrier layer 211 to replace the non-metallic substance in the barrier layer 211, or the reaction layer chemically reacts with the barrier layer 211, both of which result in the interface layer 212 having a resistance less than that of the barrier layer 211. This reduces the contact resistance Rc or the sheet resistance Rs of the bottom of the first via 209 and the second via 210 in the subsequent process of forming the interconnection layer, thereby enhancing the electrical performance of the semiconductor device.

[0079] In this embodiment, the reaction between the barrier layer 211 and the reaction layer forms the interface layer 212 on the top surface of the source-drain plug layer 207 and the gate structure 203, so that the source-drain plug layer 207 and the gate structure 203 have the interface layer 212 with the same properties. This ensures the uniform growth rate of the interconnection layer on the source-drain plug layer 207 and the gate structure 203 in the subsequent process of forming the interconnection layer in the first via 209 and the second via 210, thereby improving the quality of the formed interconnection layer. This is because when the growth rate of the interconnection layer in the first via 209 and the second via 210 is different, the interconnection layer growing faster in the via will diffuse into the interconnection layer growing slower in the via, which results in the formation of holes in the interconnection layer growing slower in the via, thereby degrading the quality of the formed interconnection layer. However, when the growth rate of the interconnection layer in the first via 209 and the second via 210 is the same, the formation of holes in the interconnection layer is avoided, thereby improving the quality of the formed interconnection layer and ensuring the performance of the final semiconductor device.

[0080] In this embodiment, the presence of the interface layer 212 on the source-drain plug layer 207 seals the top surface of the source-drain plug layer 207, which prevents the source-drain plug layer 207 from being damaged in the subsequent process, thereby improving the quality of the final source-drain plug layer 207 and enhancing the performance and yield of the final semiconductor device.

[0081] In this embodiment, the material of the reaction layer is tungsten.

[0082] In the embodiment, the process of forming the reaction layer is similar to the atomic layer deposition process, and the process parameters of forming the reaction layer include: using tungsten chloride gas and hydrogen, the gas flow of the tungsten chloride gas is 50-500sccm, the gas flow of the hydrogen is 300-3000sccm, the temperature is 300-600℃, and the pressure is 5-40torr.

[0083] In other embodiments, the material of the reaction layer can also be molybdenum.

[0084] In the embodiment, the reaction layer and the barrier layer 211 completely react to form the interface layer 212; in other embodiments, a part of the thickness of the barrier layer 211 can also remain, that is, the reaction layer does not consume the interface layer 212 formed after the complete reaction of the barrier layer 211, and a part of the thickness of the barrier layer 211 remains. Although a part of the thickness of the barrier layer 211 remains at this time, the resistance of the interface layer 212 formed is smaller than the resistance of the barrier layer 211, so that the contact resistance Rc or the sheet resistance Rs of the bottom of the first via hole 209 and the second via hole 210 is still reduced in the subsequent process of forming the interconnection layer, thereby enhancing the electrical performance of the semiconductor device formed.

[0085] In the embodiment, the thickness of the interface layer 212 is 15-20Å. When the thickness of the interface layer 212 is less than 15Å, the thickness of the interface layer 212 formed at this time is too thin, which leads to poor adhesion of the interconnection layer in the subsequent process of forming the interconnection layer, resulting in poor forming quality between the interconnection layer and the source-drain plug layer 207 and between the interconnection layer and the gate structure 203. At the same time, since the thickness of the interface layer 212 formed is too thin, it cannot play a role in sealing the top of the source-drain plug layer 207, thereby failing to play a role in protecting the source-drain plug layer 207. When the thickness of the interface layer 212 is greater than 20Å, the thickness of the interface layer 212 formed at this time is too thick, which leads to a corresponding decrease in the volume of the interconnection layer formed subsequently, so that the resistance of the semiconductor device formed finally increases, thereby reducing the electrical performance of the semiconductor device.

[0086] In the embodiment, the material of the interface layer 212 is titanium-tungsten alloy; in other embodiments, the material of the interface layer 212 can also be titanium-tungsten alloy, tantalum-tungsten alloy, or tantalum-molybdenum alloy.

[0087] Please refer to Figure 6 After the interface layer 212 is formed, the method further includes: forming an interconnection layer 213 on the interface layer 212, and the interconnection layer 213 fills the first via hole 209 and the second via hole 210 completely.

[0088] The material of the interconnection layer 213 is a metal material.

[0089] In the embodiment, the material of the interconnection layer 213 is tungsten; in other embodiments, the material of the interconnection layer 213 can also be a metal material such as copper, silver, Ru, cobalt (Co) or titanium (Ti).

[0090] In the embodiment, the forming process of the interconnection layer 213 is a selective growth process; in other embodiments, the forming process of the interconnection layer 213 can also be one or a combination of chemical vapor deposition process, atomic layer deposition process or physical vapor deposition.

[0091] In the embodiment, the reason for using the selective growth process to form the interconnection layer 213 is that the interconnection layer 213 formed by the selective growth process grows from the top surface of the interface layer 212 upwards, and the interconnection layer 213 formed has good compactness; on the other hand, the sidewalls of the first via 209 and the second via 210 are subjected to a precursor treatment, and the surface of the dielectric layer 201 has a large number of polar bonds or charges, and the surface of the interconnection layer 213 also has a large number of polar bonds or charges, so the interconnection layer 213 and the dielectric layer 201 can attract each other, so the interconnection layer 213 is easy to grow on the sidewalls of the first via 209 and the second via 210, thereby forming the interconnection layer 213 with good quality.

[0092] In the embodiment, the precursor treatment is a process of treating each surface before forming the interconnection layer 213.

[0093] In the embodiment, the top surface of the interconnection layer 213 is higher than the top surface of the dielectric layer 201.

[0094] Please refer to Figure 7 After forming the interconnection layer 213, an adhesion layer 214 is formed on the surface of the dielectric layer 201, and a metal layer 215 is formed on the adhesion layer 214 and the interconnection layer 213.

[0095] In the embodiment, the material of the adhesion layer 214 is TiN.

[0096] In the embodiment, the process of forming the adhesion layer 214 is an atomic layer deposition process.

[0097] In the embodiment, the material of the metal layer 215 is tungsten.

[0098] In the embodiment, the process of forming the metal layer 215 is a chemical vapor deposition process.

[0099] After the metal layer 215 is formed, the surface thereof is planarized so that the surface of the metal layer 215 is flat.

[0100] Correspondingly, the application also provides a semiconductor device, comprising: a substrate 200; a source-drain plug layer 207 in the substrate 200; a gate structure 203 in the substrate 200; a dielectric layer 201 on the substrate 200 and covering the gate structure 203 and the source-drain plug layer 207; a first via 209 in the dielectric layer 201 and exposing a top surface of the source-drain plug layer 207; a second via 210 in the dielectric layer 201 and exposing a top surface of the gate structure 203; and an interface layer 212 on the top surface of the source-drain plug layer 207 exposed by the first via 209 and on the top surface of the gate structure 203 exposed by the second via 210.

[0101] In this embodiment, since the interface layer 212 is on the top surface of the source-drain plug layer 207 exposed by the first via 209 and on the top surface of the gate structure 203 exposed by the second via 210, the top surfaces of the exposed source-drain plug layer 207 and the exposed gate structure 203 have the interface layer 212 with the same material properties, and in the subsequent process of forming an interconnection layer, the growth of the interconnection layer has the same environment, thereby ensuring that the interconnection layer has the same growth rate on the top of the source-drain plug layer 207 and the gate structure 203, avoiding the existence of holes in the interconnection layer due to the unbalanced growth rate, and improving the performance of the finally formed semiconductor device.

[0102] In this embodiment, since the source-drain plug layer 207 has the interface layer 212 thereon, the top surface of the source-drain plug layer 207 is sealed, which can avoid damage to the source-drain plug layer 207 in the subsequent process and improve the quality of the finally formed source-drain plug layer 207.

[0103] Further comprising: an interconnection layer 213 on the top surface of the interface layer 212 and filling the first via 209 and the second via 210.

[0104] In this embodiment, the material of the interconnection layer 213 is tungsten; in other embodiments, the material of the interconnection layer 213 can also be copper, silver, Ru, cobalt (Co), titanium (Ti), or other metal materials.

[0105] In the embodiment, the forming process of the interconnection layer 213 is a selective growth process; in other embodiments, the forming process of the interconnection layer 213 can also be one or a combination of chemical vapor deposition process, atomic layer deposition process or physical vapor deposition.

[0106] In the embodiment, the thickness of the interface layer 212 is 15-20 angstroms; when the thickness of the interface layer 212 is less than 15 angstroms, the thickness of the interface layer 212 formed is too thin, which results in poor adhesion of the interconnection layer in the subsequent process of forming the interconnection layer, and poor forming quality between the interconnection layer and the source-drain plug layer 207 and between the interconnection layer and the gate structure 203; at the same time, the interface layer 212 formed is too thin to seal the top of the source-drain plug layer 207, so as to protect the source-drain plug layer 207; when the thickness of the interface layer 212 is greater than 20 angstroms, the thickness of the interface layer 212 formed is too thick, which results in a corresponding decrease in the volume of the interconnection layer formed subsequently, so that the resistance of the semiconductor device formed finally is increased, and the electrical performance of the semiconductor device is reduced.

[0107] In the embodiment, the material of the interface layer 212 is titanium-tungsten alloy, titanium-molybdenum alloy, tantalum-tungsten alloy or tantalum-molybdenum alloy; the interface layer 212 reduces the resistance of the exposed top surface of the source-drain plug layer and the exposed top surface of the gate structure, so as to reduce the contact resistance (Rc) / sheet resistance (Rs) of the semiconductor device formed, and improve the electrical performance and use performance of the semiconductor device formed.

[0108] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized by, The method comprises: providing a substrate, the substrate having a dielectric layer thereon; etching the dielectric layer to form a first via and a second via, the first via having a bottom portion exposing a top surface of a source-drain plug layer within the substrate, the second via having a bottom portion exposing a top surface of a gate structure within the substrate; forming an interface layer on the exposed top surfaces of the source-drain plug layer and the gate structure; forming an interconnect layer on the interface layer, the interconnect layer filling the first via and the second via respectively; wherein the step of forming the interface layer comprises: forming a barrier layer on the exposed top surfaces of the source-drain plug layer and the gate structure; forming a reactive layer on the barrier layer, the reactive layer reacting with the barrier layer, the barrier layer being consumed to form the interface layer on the surfaces of the source-drain plug layer and the gate structure. The barrier layer is one or more of TiN, Ti, and TaN. The interface layer has a resistance less than that of the barrier layer. The barrier layer is formed by a selective growth process, an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. The reactive layer is tungsten or molybdenum.

2. The semiconductor device of claim 1, wherein, The interface layer has a thickness of 15 Å to 20 Å.

3. The semiconductor device of claim 1, wherein, The interface layer is a titanium-tungsten alloy, a titanium-molybdenum alloy, a tantalum-tungsten alloy, or a tantalum-molybdenum alloy.

4. A method of forming a semiconductor device, characterized by, ​ ​ ​ ​ ​ ​ ​ ​ 5. The formation method of claim 4, wherein, ​ 6. The formation method of claim 4, wherein, ​ 7. The formation method of claim 4, wherein, ​ 8. The formation process of claim 4 wherein, ​ 9. The formation method of claim 4, wherein, ​ 10. The formation method of claim 4, wherein, ​

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