Super junction device alignment mark protection method based on epitaxial backfill process

Abstract

The present application relates to a kind of super junction device alignment mark protection method based on epitaxial backfill process in the field of semiconductor technology, including forming the alignment mark defect layer of certain thickness in alignment mark region, removing alignment mark defect layer by chemical etching to form alignment mark after epitaxial backfill and polishing process, avoid the damage caused to alignment mark by epitaxial backfill and polishing process, solve the alignment problem of multilayer overlay of super junction device based on epitaxial backfill process.Compared with the alignment mark protection mode of introducing protective substance, this method has the advantages of not polluting epitaxial growth chamber, and the surface flatness after epitaxial backfill is not affected.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a method for alignment mark protection of superjunction devices based on epitaxial backfill technology. Background Technology

[0002] In recent years, the international community has placed increasing emphasis on energy conservation and emission reduction, which has placed higher demands on loss control and efficiency improvement of large power electronic equipment. As an important component of power electronic equipment, semiconductor power devices have received widespread attention from the industry. Superjunction devices can break through the one-dimensional theoretical performance limits of ordinary devices and have great performance advantages and application potential in medium and high voltage fields.

[0003] Currently, the mainstream manufacturing technologies for superjunction devices include multiple epitaxy and trench epitaxy with backfill. Superjunction devices based on the backfill process have the advantages of small cell size and low cost. However, after trench epitaxy with backfill and polishing, the alignment marks on the wafer surface are damaged, affecting the overlay accuracy of subsequent processes and posing challenges to the fabrication of superjunction devices. Introducing protective materials onto the alignment marks can easily contaminate the epitaxy equipment chamber and affect the wafer surface flatness after the backfill process, increasing the difficulty of the polishing process. Summary of the Invention

[0004] This invention addresses the problem of damaged alignment marks on the wafer surface of superjunction devices after epitaxial backfilling and polishing processes. It provides a method for protecting alignment marks, enabling clear alignment marks to be etched onto the wafer even after polishing.

[0005] To address the aforementioned technical problems, the present invention provides the following technical solution:

[0006] Before the epitaxial backfill process, an alignment mark defect layer of a certain thickness is first formed below the alignment mark area. After the epitaxial backfill and polishing processes, the alignment mark defect layer is removed by chemical etching to form the alignment mark.

[0007] Preferably, the alignment mark defect layer is formed by Ar ion implantation.

[0008] Preferably, the thickness of the alignment mark defect layer is the same as the required thickness of the alignment mark.

[0009] Preferably, the chemical etching to remove the defect layer in the alignment mark area uses KOH etchant.

[0010] Compared with the prior art, the technical solution provided by this invention has the following advantages:

[0011] This invention avoids damage to the alignment marks caused by the epitaxial backfilling and polishing processes by forming an alignment mark defect layer, followed by epitaxial backfilling and polishing, and then etching out the alignment marks. Since the epitaxial growth on the wafer surface is removed by polishing, there is no need to consider the impact of the alignment mark defect layer spreading during epitaxial growth. Compared to introducing other substances to protect the alignment marks, this method does not contaminate the epitaxial chamber, does not affect the flatness of the wafer after epitaxial backfilling, and facilitates subsequent polishing processes. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the embodiments are briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0013] Figure 1 A wafer structure diagram before the epitaxial backfill process in an alignment mark protection method proposed in this invention.

[0014] Figure 2 A diagram illustrating the alignment mark defect layer structure in an alignment mark protection method proposed in this invention.

[0015] Figure 3 This is a wafer structure diagram after the epitaxial backfill process in an alignment mark protection method proposed in this invention.

[0016] Figure 4 A wafer structure diagram after polishing in an alignment mark protection method proposed in this invention.

[0017] Figure 5 A wafer structure diagram after chemical etching in an alignment mark protection method proposed in this invention.

[0018] Figure reference numerals: 1. Alignment mark region; 2. Device region; 3. Superjunction trench; 4. Alignment mark defect layer; 5. Alignment mark defect layer implantation mask; 6. P-type doped region formed by epitaxial backfill; 7. Alignment mark trench Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments.

[0020] like Figure 1 As shown, the structure is simply divided into alignment mark area 1 and device area 2. Before the epitaxial backfill process, device area 2 has already formed a superjunction trench 3. Then, as... Figure 2The method shown is to form an alignment mark defect layer injection mask 5 on the wafer surface. Specifically, taking a SiO2 mask as an example, a SiO2 thin film is grown on the wafer surface, and a set or more alignment mark patterns are photolithographically etched in a suitable area on the wafer surface using a stepper lithography machine. Then, the SiO2 is etched to form the alignment mark defect layer injection mask 5.

[0021] After forming the implantation mask, an alignment mark defect layer 4 is formed below the alignment mark pattern area by Ar ion implantation. The thickness of the alignment mark defect layer 4 is determined by the thickness of the alignment mark trench that the lithography machine can recognize. After forming the alignment mark defect layer 4, the alignment mark defect layer implantation mask 5 is removed, and then a superjunction trench epitaxial backfill process is performed.

[0022] Since the alignment mark area has not undergone etching or the introduction of other material structures, after the epitaxial backfill process, such as Figure 3 As shown, the alignment mark surface remains flat. Since the p-type epitaxial layer 6 grown on the wafer surface is polished away and is not part of the device, there is no need to worry about defect propagation caused by the alignment mark defect layer during growth, and its impact on device performance is negligible.

[0023] After the epitaxial backfill process, the p-type epitaxial layer 6 on the wafer surface needs to be polished away. The polishing endpoint is the wafer surface position before epitaxy. Therefore, after the wafer surface polishing process, such as Figure 4 As shown, the aligned defect layer will be fully exposed. This polishing process requires precise time control. Depending on the superjunction device structure design and process parameters, the polishing endpoint position needs to be adjusted. If a certain thickness needs to be polished, then... Figure 2 The thickness of the center alignment mark defect layer 4 needs to be increased by the thickness of the over-polished layer.

[0024] Because the crystal structure of the alignment mark defect layer differs from other epitaxial regions, its surface region exhibits greater strain energy during chemical etching. Therefore, the defect region readily reacts with the etchant, resulting in a faster etching rate. KOH is used as the etchant to chemically etch the wafer surface for a specific time. The etching time depends on the etching rate of the alignment mark defect layer. After the alignment mark defect layer is completely removed by the etchant, such as... Figure 5 As shown, alignment mark trenches 7 with a certain depth are eventually formed on the wafer surface. The trench depth of the alignment mark pattern is mainly determined by the thickness of the alignment mark defect layer and is affected by the anisotropic etching rate of the etchant.

[0025] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A method for alignment mark protection of superjunction devices based on epitaxial backfill technology, characterized in that: After forming the superjunction trench, an alignment mark implantation mask is grown and formed on the wafer surface. An alignment mark defect layer is formed by Ar ion implantation. After epitaxial backfilling and polishing of the superjunction trench, the alignment mark defect layer is removed by chemical etching to form the alignment mark trench. The position of the alignment mark trench is determined by forming the alignment mark defect layer before the epitaxial backfilling process. No alignment mark trench or dielectric material exists during the epitaxial backfilling process. The alignment mark trench is formed by etching the alignment mark defect layer after the epitaxial backfilling process.

2. The method for protecting alignment marks of superjunction devices according to claim 1, characterized in that, The alignment mark defect layer is composed of one or more crystal defects.

3. The method for protecting alignment marks of superjunction devices according to claim 1, characterized in that, The thickness of the alignment mark defect layer is required to be the same as the depth of the alignment mark groove.

4. The method for protecting alignment marks of superjunction devices according to claim 1, characterized in that, The chemical corrosion is carried out using KOH as an etchant.

5. The method for protecting alignment marks of superjunction devices according to claim 1, characterized in that, The chemical etching time is the time required to reach the required depth of the alignment mark groove.

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