High power density ultra-heat dissipation chip symmetrical stacking packaging structure and packaging method thereof

Abstract

The present invention relates to a high-power density ultra-heat-dissipating chip symmetrical stacking packaging structure and a packaging method thereof, wherein the stacking packaging structure comprises an upper double-sided copper clad plate, a lower double-sided copper clad plate, a first chip, a second chip, a first copper clip, a second copper clip, pins and a plastic package, wherein the collector of the first chip is welded to the inner surface of the upper double-sided copper clad plate, the collector of the second chip is welded to the inner surface of the lower double-sided copper clad plate, one end of the first copper clip is welded to the inner surface of the lower double-sided copper clad plate, the emitter of the first chip is welded to the upper surface of the first copper clip, and the emitter of the second chip is welded to the lower surface of the first copper clip. This application is based on the innovative optimization of the existing product structure, and develops a new chip symmetrical structure to achieve vertical symmetry and rapid heat dissipation, with the advantages of more stable performance, greater power density, better heat dissipation, higher reliability, and lower power consumption, smaller product size, less material use, lower cost, and simpler and more efficient assembly process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-power density ultra-heat-dissipating chip symmetrical stacking packaging structure and a packaging method thereof. Background Art

[0002] Power modules are widely used in the fields of electricity, energy, etc., among which IGBT / MOSFET power modules occupy most of the market with their superior performance advantages, especially in the applications of new energy vehicles, rail transit, etc., IGBT / MOSFET power modules have become an indispensable part of the electronic control components. During the operation of IGBT / MOSFET power modules, the internal chips of the power modules will quickly generate heat due to the existence of resistance. If the heat cannot be dissipated in time, the rapid accumulation will cause the chip temperature to rise. As the chip temperature rises, the performance stability of the chip deteriorates, and even causes direct damage and failure of the chip. At present, the most effective improvement solution in the industry is to connect metal on both the top and bottom surfaces of the power module, directly exposing it to achieve fast and efficient heat dissipation, so as to slow down the temperature rise of the power module during operation and ensure stable and reliable operation of the power module.

[0003] Take IGBT power module as an example. Figures 1 to 3 As shown, it includes an upper double-sided copper clad board 1, a lower double-sided copper clad board 2, a plurality of chips 10, a metal pad A (91), a metal pad B (92), a pin 7 and a plastic package 8. The plurality of chips 10 are arranged flat, and the collector 101 of the chip 10 is welded on the inner surface of the lower double-sided copper clad board 2. The emitter 102 of the chip 10 is first welded to the metal pad A (91), and the metal pad A (91) is then welded to the inner surface of the upper double-sided copper clad board 1. The gate 103 of the chip 10 is electrically connected to the circuit on the lower double-sided copper clad board 2 through a metal welding wire 11 to form an effective functional circuit. The metal pad B (92) is provided The chip 10 is placed between the upper double-sided copper clad laminate 1 and the lower double-sided copper clad laminate 2 to support the upper double-sided copper clad laminate 1 and the lower double-sided copper clad laminate 2. The pins 7 are welded on the inner surface of the lower double-sided copper clad laminate 2 and are electrically connected to the collector 101, the emitter 102 and the gate 103 of the chip 10 through the circuit on the lower double-sided copper clad laminate 2. The plastic package 8 is used to wrap the chip 10, the metal pad A (91), the metal pad B (92), the inner part of the pins 7 and the inner surfaces and side surfaces of the upper double-sided copper clad laminate 1 and the lower double-sided copper clad laminate 2. The outer surfaces of the upper double-sided copper clad laminate 1 and the lower double-sided copper clad laminate 2 are exposed to quickly dissipate heat.

[0004] In this solution, the emitter 102 of the chip 10 is welded to the upper double-sided copper clad board 1 through the metal pad A (91), while the collector 101 is directly welded to the lower double-sided copper clad board 2, resulting in an asymmetric structure between the collector 101 and the emitter 102 of the chip 10. Asymmetric heat dissipation will cause different temperature rises on the upper and lower sides of the power module. Long-term temperature imbalance will affect the performance and service life of the product to a certain extent. The planar layout structure of using multiple chips in the power module at the same time results in a large product size, a large double-sided copper clad board area, a large amount of plastic packaging material, a large number of metal pads, and the heights of the metal pads are not completely the same. The assembly process is complicated and the cost is high. Because the metal pads are welded in an inclined manner and there are many welding voids, these will cause product performance to be reduced or fail, making it difficult to meet the high reliability and high stability requirements of lower-level products.

[0005] In this scheme, the packaging method of the power module is as follows: S1, the chip 10 and the metal pad B (92) need to be mounted on the lower double-sided copper-clad board 2, and then reflow soldering is performed to fix; S2, the gate of the chip 10 is then connected to the lower double-sided copper-clad board 2 through the metal welding wire 11; S3, the metal pad A (91) is then mounted on the chip 10, so that the metal pad A (91) is electrically connected to the emitter of the chip 10; S4, the upper double-sided copper-clad board 1 is then mounted on the metal pad A (91) and the metal pad B (92); S5, plastic sealing is performed. This packaging method is also relatively complex, the chip gate welding requires a metal wire welding process, the double-sided copper-clad board has many welding points, the copper layer circuit layout is complex, the probability of poor welding is high, the packaging process is complex, the chip circuit path in the module is long, and the circuit path power loss during operation is large. Summary of the invention

[0006] The object of the present invention is to provide a high-power density and ultra-heat-dissipating chip symmetrical stacking packaging structure and a packaging method thereof with greater power density, better heat dissipation and more stable performance.

[0007] The present invention is implemented as follows: a high-power density ultra-heat-dissipating chip symmetrical stacking packaging structure comprises an upper double-sided copper-clad laminate, a lower double-sided copper-clad laminate, a first chip, a second chip, a first copper clip, a second copper clip, a pin and a plastic package, wherein the collector of the first chip is welded on the inner surface of the upper double-sided copper-clad laminate, the collector of the second chip is welded on the inner surface of the lower double-sided copper-clad laminate, one end of the first copper clip is welded on the inner surface of the lower double-sided copper-clad laminate, the emitter of the first chip is welded on the upper surface of the first copper clip, and the emitter of the second chip is welded on the lower surface of the first copper clip; one end of the second copper clip is welded on the inner surface of the lower double-sided copper-clad laminate, the gate of the first chip is welded on the upper surface of the second copper clip, the gate of the second chip is welded on the lower surface of the second copper clip, the pin is welded on the inner surface of the lower double-sided copper-clad laminate, and is electrically connected to the collector, emitter and gate of the first chip and the second chip through the circuit on the lower double-sided copper-clad laminate, and the plastic package is used to wrap the inner part of the first chip, the second chip, the first copper clip, the second copper clip and the pin.

[0008] The first chip and the second chip are the same chip, and the first chip and the second chip are stacked and arranged completely symmetrically up and down.

[0009] The stacked packaging structure includes a plurality of groups of the first chip and the second chip, and the groups are arranged horizontally in parallel.

[0010] The plastic package is also used to wrap the inner surface and side surface of the upper double-sided copper clad laminate and the lower double-sided copper clad laminate, exposing the outer surface of the upper double-sided copper clad laminate and the lower double-sided copper clad laminate.

[0011] Among them, the stacked packaging structure also includes a metal pad, which is arranged between the upper double-sided copper clad laminate and the lower double-sided copper clad laminate, and is used to connect the upper double-sided copper clad laminate and the lower double-sided copper clad laminate to form a circuit loop, and is also used to support the upper double-sided copper clad laminate and the lower double-sided copper clad laminate.

[0012] There are two metal pads, which are distributed at two diagonal corners of the stacked package structure.

[0013] Wherein, the welding areas of the first copper clip and the second copper clip are provided with a welding material coating.

[0014] The present invention provides another technical solution: a packaging method for the above-mentioned high power density ultra-heat dissipation chip symmetrical stacking packaging structure, comprising the following steps:

[0015] S1: mounting the second chip on the lower double-sided copper-clad board, mounting the first copper clip and the second copper clip on the lower double-sided copper-clad board and the second chip, and then performing the first reflow soldering;

[0016] S2: Mounting the first chip on the first copper clip and the second copper clip, mounting the pins on the lower double-sided copper clad board, and then mounting the upper double-sided copper clad board on the first chip, and then performing a second reflow soldering;

[0017] S3: perform plastic sealing.

[0018] Wherein, in step S2, it also includes mounting the metal pad on the lower double-sided copper clad laminate, mounting the upper double-sided copper clad laminate on the metal pad and the first chip, and then performing a second reflow soldering.

[0019] The beneficial effects of the present invention are as follows: compared with the prior art, this application is based on the innovative optimization of the existing product structure, and develops a new chip symmetrical structure to achieve vertical symmetry and rapid heat dissipation, which has the advantages of more stable performance, greater power density, better heat dissipation, lower power consumption, higher reliability and longer service life. At the same time, the assembly process is also simpler and more efficient, the module size is smaller, less material is used, and the cost is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a cross-sectional view of the packaging structure of an IGBT module in the prior art;

[0021] Figure 2 It is a component layout diagram (top view) of the packaging structure of the IGBT module in the prior art;

[0022] Figure 3 It is a schematic diagram of the structure of an IGBT chip in the prior art;

[0023] Figure 4 is a cross-sectional view of the symmetrical stacked packaging structure of high power density and ultra-heat dissipating chips according to the present invention;

[0024] Figure 5 1. It is a component layout diagram (top view) of the high power density and ultra-heat dissipating chip symmetrical stacking packaging structure of the present invention.

[0025] 1. Upper double-sided copper clad laminate; 2. Lower double-sided copper clad laminate; 3. First chip; 4. Second chip; 5. First copper clip; 6. Second copper clip; 7. Pins; 8. Plastic package; 9. Metal pad; 91. Metal pad A; 92. Metal pad B; 10. Chip; 101. Collector; 102. Emitter; 103. Gate; 11. Metal welding wire. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] As an embodiment of the high power density ultra-heat dissipation chip symmetrical stacking packaging structure of the present invention, Figures 3 to 5 As shown, it includes an upper double-sided copper clad laminate 1, a lower double-sided copper clad laminate 2, a first chip 3, a second chip 4, a first copper clip 5, a second copper clip 6, a pin 7 and a plastic package 8, the collector of the first chip 3 is welded to the inner surface of the upper double-sided copper clad laminate 1, the collector of the second chip 4 is welded to the inner surface of the lower double-sided copper clad laminate 2, one end of the first copper clip 5 is welded to the inner surface of the lower double-sided copper clad laminate 2, the emitter of the first chip 3 is welded to the upper surface of the first copper clip 5, and the emitter of the second chip 4 is welded to the lower surface of the first copper clip 5 On; one end of the second copper clip 6 is welded on the inner surface of the lower double-sided copper clad laminate 2, the gate of the first chip 3 is welded on the upper surface of the second copper clip 6, and the gate of the second chip 4 is welded on the lower surface of the second copper clip 6. The pin 7 is welded on the inner surface of the lower double-sided copper clad laminate 2, and is electrically connected to the collector, emitter and gate of the first chip 3 and the second chip 4 through the circuit on the lower double-sided copper clad laminate 2. The plastic package 8 is used to wrap the first chip 3, the second chip 4, the first copper clip 5, the second copper clip 6 and the inner part of the pin 7.

[0028] The packaging method of the above-mentioned high power density ultra-heat dissipation chip symmetrical stacking structure comprises the following steps:

[0029] S1: Mount the second chip 4 on the lower double-sided copper clad board 1, then mount the first copper clip 5 and the second copper clip 6 on the lower double-sided copper clad board 2 and the second chip 4, and then perform the first reflow soldering;

[0030] S2: Mount the first chip 3 on the first copper clip 5 and the second copper clip 6, mount the pin 7 on the lower double-sided copper clad board 2, and then mount the upper double-sided copper clad board 1 on the first chip 3, and then perform a second reflow soldering;

[0031] S3: perform plastic sealing.

[0032] In this embodiment, the stacked package structure is preferably provided with a metal pad 9, which is arranged between the upper double-sided copper clad board 1 and the lower double-sided copper clad board 2, and is used to connect the upper double-sided copper clad board 1 and the lower double-sided copper clad board 2 to form a circuit loop, and is also used to support the upper double-sided copper clad board 1 and the lower double-sided copper clad board 2. The number of the metal pads 9 is two, distributed at two diagonal corners of the stacked package structure.

[0033] Due to the addition of the metal pad 9, the above packaging method in step S2 also includes mounting the metal pad 9 on the lower double-sided copper clad laminate 2, mounting the upper double-sided copper clad laminate 1 on the metal pad 9 and the first chip 3, and then performing a second reflow soldering.

[0034] In the present invention, the emitters of the first chip 3 and the second chip 4 are welded together with the first copper clip 5, the gates of the first chip 3 and the second chip 4 are welded together with the second copper clip 6, and the collectors of the first chip 3 and the second chip 4 are welded to the upper double-sided copper clad laminate 1 and the lower double-sided copper clad laminate 2 respectively, creatively realizing a special chip stacking structure, the first copper clip 5 can simultaneously extract the current of the two chips (the first chip and the second chip), the second copper clip 6 can simultaneously control the shutdown and conduction of the two chips, realize the synchronous switching operation of the dual chips, improve the power density of the module, withstand greater current, reduce the overall size of the module, and integrate more chips and components into the module, providing conditions for higher module integration without increasing or even reducing the size, thereby improving the module space utilization.

[0035] Since the first chip 3 and the second chip 4 are arranged up and down, they are a symmetrical structure. The symmetrical structure has balanced heat dissipation, and the upper and lower temperature rises of the stacked packaging structure are basically the same, which can improve the performance and service life of the product to a certain extent; the first copper clip 5 and the second copper clip 6 can also quickly transfer heat to the lower double-sided copper clad board 2, ensuring good heat dissipation performance; copper clip welding replaces the wire welding process, the packaging welding process is simple, the process is greatly simplified, and the module abnormality caused by poor chip packaging welding is reduced; the application can reduce the use of multiple materials and reduce material costs. The number of metal pads used is smaller and the size is consistent, which can simplify the assembly difficulty, improve the module yield, and use less plastic packaging material; the double-sided copper clad board solder joints are simplified and reduced, the copper layer line layout is simple, and the welding defect rate is reduced; the vertical circuit loop of the chip in the module is shortened, the circuit power loss during operation is reduced, the signal response is faster, and the parasitic inductance generated by high-frequency conversion is greatly reduced.

[0036] In this embodiment, the first chip 3 and the second chip 4 are the same chip, and the first chip 3 and the second chip 4 are stacked completely symmetrically up and down. The double-sided completely symmetrical heat dissipation structure has symmetrical heat dissipation of the chip, better heat dissipation, more stable chip operation performance, better reliability, and longer life, which can be improved by about 20%. This is the most preferred solution of this application. Of course, there is a slight deviation in the upper and lower positions of the first chip 3 and the second chip 4, and most of the beneficial effects of the above-mentioned stacking package can still be obtained.

[0037] In this embodiment, the stacked package structure includes multiple groups of the first chip 3 and the second chip 4, which are arranged horizontally in parallel. The specific number of groups in this embodiment is 2, and 4 identical chips are actually used, which greatly improves the power density.

[0038] In this embodiment, the plastic packaging body 8 is also used to wrap the inner surfaces and side surfaces of the upper double-sided copper clad laminate 1 and the lower double-sided copper clad laminate 2 , exposing the outer surfaces of the upper double-sided copper clad laminate 1 and the lower double-sided copper clad laminate 2 .

[0039] In this embodiment, the structure and size design of the first copper clip 5 and the second copper clip 6 need to match the structural polarity of the first chip and the second chip. The welding area of ​​the first copper clip 5 and the second copper clip 6 can be provided with a solder coating (such as a gold coating), which can be directly welded to the first chip 3 and the second chip 4 to improve the weldability.

[0040] Compared with the existing technology, this application innovates and optimizes the existing product structure to develop a new chip symmetrical structure to achieve vertical symmetry and rapid heat dissipation. It has the advantages of more stable performance, higher power density, better heat dissipation, lower power consumption, higher reliability and longer service life. At the same time, the assembly process is simpler and more efficient, the module size is smaller, the material usage is less, and the cost is lower.

[0041] According to the actual experimental data of the applicant, the innovative chip stacking structure is adopted, the module size is reduced by 50%, the module thickness is reduced by 40%, the use of plastic packaging materials is reduced by 60%, the size of the double-sided copper clad board is reduced by 50%, and the first copper clip and the second copper clip replace the original metal pad A for heat dissipation, and the heat dissipation effect is improved by more than 10%. The copper clip welding is simple and stable, with a low defect rate. The copper clip welding replaces the wire welding process, and the packaging process is simplified, which can reduce the module abnormality caused by poor chip packaging welding, reduce the packaging complexity, and reduce the product cost by 40%.

[0042] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high power density and ultra-heat dissipation chip symmetrical stacking packaging structure, It is characterized in that The invention comprises an upper double-sided copper clad laminate, a lower double-sided copper clad laminate, a first chip, a second chip, a first copper clip, a second copper clip, a pin and a plastic package. The collector of the first chip is welded on the inner surface of the upper double-sided copper clad laminate, the collector of the second chip is welded on the inner surface of the lower double-sided copper clad laminate, one end of the first copper clip is welded on the inner surface of the lower double-sided copper clad laminate, the emitter of the first chip is welded on the upper surface of the first copper clip, and the emitter of the second chip is welded on the lower surface of the first copper clip; one end of the second copper clip is welded on the inner surface of the lower double-sided copper clad laminate, the gate of the first chip is welded on the upper surface of the second copper clip, the gate of the second chip is welded on the lower surface of the second copper clip, the pin is welded on the inner surface of the lower double-sided copper clad laminate, and is electrically connected to the collector, emitter and gate of the first chip and the second chip through the circuit on the lower double-sided copper clad laminate; the plastic package is used to wrap the inner part of the first chip, the second chip, the first copper clip, the second copper clip and the pin; the first chip and the second chip are the same chip, and the first chip and the second chip are stacked completely symmetrically up and down.

2. The high power density ultra-heat dissipating chip symmetrical stacking packaging structure according to claim 1, It is characterized in that The stacked package structure includes a plurality of groups of the first chips and the second chips, and the groups are arranged horizontally and in parallel.

3. The high power density ultra-heat dissipating chip symmetrical stacking packaging structure according to claim 1, It is characterized in that The plastic package body is also used to wrap the inner surface and side surface of the upper double-sided copper clad laminate and the lower double-sided copper clad laminate, exposing the outer surface of the upper double-sided copper clad laminate and the lower double-sided copper clad laminate.

4. The high power density ultra-heat dissipating chip symmetrical stacking packaging structure according to claim 1, It is characterized in that The stacked packaging structure also includes a metal pad, which is arranged between the upper double-sided copper clad laminate and the lower double-sided copper clad laminate, and is used to connect the upper double-sided copper clad laminate and the lower double-sided copper clad laminate to form a circuit loop, and is also used to support the upper double-sided copper clad laminate and the lower double-sided copper clad laminate.

5. The high power density ultra-heat dissipating chip symmetrical stacking packaging structure according to claim 4, It is characterized in that The number of the metal pads is two and they are distributed at two diagonal corners of the stacked package structure.

6. The high power density ultra-heat dissipating chip symmetrical stacking packaging structure according to claim 1, It is characterized in that The welding areas of the first copper clip and the second copper clip are provided with a welding material coating.

7. A packaging method for the high power density ultra-heat dissipating chip symmetrical stacking packaging structure according to any one of claims 1 to 6, It is characterized in that The following steps are involved: S1: mounting the second chip on the lower double-sided copper-clad board, mounting the first copper clip and the second copper clip on the lower double-sided copper-clad board and the second chip, and then performing the first reflow soldering; S2: Mounting the first chip on the first copper clip and the second copper clip, mounting the pins on the lower double-sided copper clad board, and then mounting the upper double-sided copper clad board on the first chip, and then performing a second reflow soldering; S3: perform plastic sealing.

8. The packaging method of the high power density ultra-heat dissipating chip symmetrical stacking packaging structure according to claim 7, It is characterized in that In step S2, the process also includes mounting a metal pad on the lower double-sided copper clad laminate, mounting an upper double-sided copper clad laminate on the metal pad and the first chip, and then performing a second reflow soldering.

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