Synaptic device and method for manufacturing the same

Abstract

This application relates to the field of semiconductor structures, and particularly to a synaptic device and a manufacturing method thereof. The synaptic device includes: a substrate; a buffer layer formed on the substrate; a bottom electrode layer formed on the buffer layer; a ferroelectric layer formed on the bottom electrode layer; a semiconductor photosensitive layer formed on the ferroelectric layer; a source electrode and a drain electrode, wherein the source electrode and the drain electrode are spaced apart and disposed on the semiconductor photosensitive layer. This application can achieve short-term plasticity and long-term plasticity of the synaptic device, and the two plasticities can be switched, simulating the long-term potentiation and long-term depression effects of biological synapses, having basic neuromorphic learning and memory rules, capable of simulating human brain neurons and synapses, and being applicable to artificial neural network calculations.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and particularly to a synaptic device and a manufacturing method thereof. Background Art

[0002] With the rapid development of information technology, the amount and complexity of data that microelectronic devices need to process are both increasing rapidly, which poses higher requirements for data analysis, processing, and storage. In the past few decades, Moore's Law, which has supported the rapid development of microelectronic technology, is approaching its limit. It is almost impossible to further improve the performance of transistors by reducing their size. Moreover, the current von Neumann computing architecture with separate memory and computing units is also difficult to meet the needs of machine learning and artificial intelligence in the big data era and the future explosive growth of data processing requirements. A large amount of power is wasted in the repeated exchange process of data and information, resulting in an increasingly prominent heat dissipation problem.

[0003] To meet the future complex and diverse data processing requirements, inspired by the human brain, people have innovated at the microelectronic device level to manufacture synaptic devices that can directly simulate human brain neurons and synapses, and integrate them into a brain-like artificial neural network system to achieve some functions of an artificial brain. In view of this, there is a need to provide a synaptic device that can effectively simulate the plasticity behaviors of biological synapses, such as short-term plasticity, long-term plasticity, long-term potentiation, and long-term depression, and is suitable for artificial neural network computing. Summary of the Invention

[0004] One of the main objectives of this application is to provide a synaptic device that can effectively simulate the plasticity behaviors of biological synapses, such as short-term and long-term memory, frequency dependence, long-term potentiation, and long-term depression.

[0005] One of the main inventive objectives of the present invention is achieved through the following technical solutions:

[0006] A synaptic device, comprising:

[0007] A substrate;

[0008] A buffer layer formed on the substrate;

[0009] A bottom electrode layer formed on the buffer layer;

[0010] A ferroelectric layer formed on the bottom electrode layer;

[0011] A semiconductor photosensitive layer formed on the ferroelectric layer;

[0012] A source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart and disposed on the semiconductor photosensitive layer.

[0013] By adopting the above technical solution, a voltage is applied to the bottom electrode layer, and a potential difference is formed between the source electrode, the drain electrode and the bottom electrode layer to generate an electric field, so that the photogenerated carriers in the semiconductor photosensitive layer move in the direction of the electric field, so that a conductive channel is formed between the source electrode and the drain electrode. Under light of different energies or wavelengths, the concentration of photogenerated carriers will change, resulting in a change in the conductivity of the conductive channel, thereby simulating the response of biological synapses to light stimulation. At the same time, the electric field between the source electrode, the drain electrode and the bottom electrode layer will cause the ferroelectric layer to have a ferroelectric field effect (ferroelectric polarization effect), causing the polarization of the ferroelectric layer to flip, affecting the hole-electron distribution of the photosensitive semiconductor layer, thereby changing the conductivity of the semiconductor photosensitive layer, and achieving the function of regulating the conductivity of the conductive channel.

[0014] The degree of polarization reversal of the ferroelectric layer can be precisely controlled by the electric field, showing excellent conductivity control performance, while the photosensitive semiconductor layer has the characteristics of high-speed response of photogenerated carriers, high bandwidth and low crosstalk. The combination of the two can realize photoelectric coordinated control, which can realize short-term plasticity and long-term plasticity of synaptic devices, and the two types of plasticity can be switched to simulate the long-term enhancement and long-term inhibition of biological synapses. It has basic neuromorphic learning and memory laws, can simulate human brain neurons and synapses, and is suitable for artificial neural network calculations.

[0015] Optionally, the material of the ferroelectric layer includes Pb(Zr 0.2 Ti 0.8 ) 3 .

[0016] By adopting the above technical solution, the ferroelectric layer has the characteristics of excellent ferroelectric performance, excellent piezoelectric performance, excellent pyroelectric performance, high Curie temperature, easy doping and good stability.

[0017] Optionally, the thickness of the ferroelectric layer is 160nm-250nm.

[0018] By adopting the above technical solution and limiting the thickness range of the ferroelectric layer, the ferroelectric layer can maintain relatively stable ferroelectric properties, reduce the influence of the depolarization field, and achieve precise control of the conductivity of the semiconductor photosensitive layer by the ferroelectric layer.

[0019] Optionally, the material of the semiconductor photosensitive layer includes ZnO.

[0020] By adopting the above technical solution, the semiconductor photosensitive layer is made sensitive to ultraviolet light. Under ultraviolet light irradiation under different conditions, the semiconductor photosensitive layer will generate different numbers of photogenerated carriers, and the photogenerated carriers will move in a direction under the electric field, thereby changing the current passing through the source electrode or the drain electrode to simulate the basic performance of biological synapses under the stimulation of light signals.

[0021] Optionally, the thickness of the semiconductor photosensitive layer is 25 nm - 50 nm.

[0022] By adopting the above technical solution, by limiting the thickness range of the semiconductor photosensitive layer, the semiconductor photosensitive layer has a relatively good response to light stimulation, reduces the influence of the too large thickness of the semiconductor photosensitive layer on the resistance value and the synaptic device switching ratio, and is conducive to the polarization regulation of the ferroelectric layer.

[0023] Optionally, the material of the substrate includes mica material; the material of the buffer layer is CoFe 2 O 4 ; the material of the bottom electrode layer includes SrRuO 3 .

[0024] By adopting the above technical solution, by using mica material, the substrate is easy to obtain a smooth and flat surface after processing delamination and has good thermal stability. By using CoFe 2 O 4 material, the buffer layer has good chemical stability and thermal stability, and during the process of fabricating the synaptic device, the buffer layer can grow densely on the substrate, providing a basis for the high-quality growth of subsequent materials. By using SrRuO 3 material, the bottom electrode layer has good chemical stability and thermal stability, and the bottom electrode layer and the buffer layer have good lattice matching. During the process of fabricating the synaptic device, the bottom electrode layer is suitable for epitaxial growth on the buffer layer, providing a basis for the high-quality growth of subsequent materials.

[0025] Optionally, the thickness of the bottom electrode layer is 30 nm - 60 nm.

[0026] By adopting the above technical solution, by limiting the thickness range of the bottom electrode layer, the bottom electrode layer can achieve a relatively high conductivity and improve the performance of the synaptic device.

[0027] The second main object of the present application is to provide a method for fabricating a synaptic device, which can effectively simulate the plasticity behaviors such as short-term memory, long-term memory, frequency dependence, long-term potentiation, and long-term depression of biological synapses.

[0028] The second main inventive object of the present invention is achieved through the following technical solutions:

[0029] A method for fabricating a synaptic device as described in any one of the above, comprising the following steps:

[0030] S1. Provide a substrate;

[0031] S2. Deposit a buffer layer on the substrate by pulsed laser deposition technology;

[0032] S3. Deposit the bottom electrode layer on the buffer layer through the pulsed laser deposition process;

[0033] S4. Deposit the ferroelectric layer on the bottom electrode layer through the pulsed laser deposition process;

[0034] S5. Deposit the semiconductor photosensitive layer on the ferroelectric layer through the pulsed laser deposition process, and perform cooling after the deposition is completed;

[0035] S6. Through the electrode lithography process, after using photoresist to engrave the required electrode pattern on the semiconductor photosensitive layer, perform metal electrode evaporation to obtain the source electrode and the drain electrode.

[0036] By adopting the above technical solution, the synaptic device is prepared using the pulsed laser deposition process, so that the layers in the synaptic device grow epitaxially, making the combination between the layers tighter, the interface clearer, the thin film crystallization quality higher, and the defects fewer, and the preparation process has high replicability.

[0037] Optionally, in the specific method of step S6, it includes:

[0038] S61. Apply photoresist on the semiconductor photosensitive layer, spin-coat the photoresist, and bake the photoresist;

[0039] S62. Use electron beam exposure to expose the designed pattern on the photoresist. After development, the area that needs to be plated with electrodes is exposed, and metal is plated through metal evaporation;

[0040] S63. Strip off the excess photoresist and the excess metal layer to obtain the source electrode and the drain electrode.

[0041] By adopting the above technical solution, apply photoresist on the semiconductor photosensitive layer, spin-coat the photoresist, and bake the photoresist, then use electron beam exposure to expose the designed pattern on the photoresist. After development, the area that needs to be plated with electrodes is exposed, and finally metal is plated through metal evaporation. After stripping off the excess photoresist and the metal layer, mutually separated source electrode and drain electrode can be obtained.

[0042] Optionally, in step S2, the deposition atmosphere is 40 mTorr - 60 mTorr, and the substrate temperature is 580 °C - 620 °C;

[0043] In step S3, the deposition atmosphere is 60 mTorr - 100 mTorr, and the substrate temperature is 580 °C - 620 °C;

[0044] In step S4, the deposition atmosphere is 150 mTorr - 250 mTorr, and the substrate temperature is 580 °C - 620 °C;

[0045] In step S5, the deposition atmosphere is 3 mTorr - 10 mTorr, and the substrate temperature is 380°C - 420°C.

[0046] By adopting the above technical solution, in the pulsed laser deposition process, the deposition atmosphere and the substrate temperature are important factors affecting the growth of each layer in the synaptic device. By limiting the oxygen pressure of the deposition atmosphere and the substrate temperature, the crystallization quality of the synaptic device is improved.

[0047] In summary, the present application includes at least one of the following beneficial technical effects:

[0048] 1. The degree of polarization reversal of the ferroelectric layer can be precisely regulated by an electric field, showing excellent conductance regulation performance. The photosensitive semiconductor layer has the characteristics of high-speed response, high bandwidth, and low crosstalk of photo-generated carriers. The combination of the two realizes optoelectronic collaborative regulation, can achieve short-term plasticity and long-term plasticity of the synaptic device, and the two plasticities can be switched, simulating the long-term potentiation and long-term depression of biological synapses, following the basic neuromorphic learning and memory rules, can simulate human brain neurons and synapses, and is suitable for artificial neural network computing.

[0049] 2. After the ferroelectric layer undergoes polarization reversal, it can change the distribution of hole-electron pairs in the photosensitive semiconductor layer, thereby regulating the conductance of the photosensitive semiconductor layer, and this regulation can be non-volatile.

[0050] 3. Using the pulsed laser deposition process to fabricate the synaptic device enables epitaxial growth between the layers in the synaptic device, making the combination between the layers tighter, the interface clearer, the thin film crystallization quality higher, and the defects fewer, and the fabrication process has high reproducibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0052] The structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the limited conditions under which the present invention can be implemented. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention.

[0053] Figure 1It is a schematic structural diagram of the synaptic device according to the first embodiment of the present application.

[0054] Figure 2 It is a schematic flow chart of the manufacturing method of the synaptic device according to the first embodiment of the present application.

[0055] Figure 3 It is an XRD pattern of the synaptic device according to the first embodiment of the present application.

[0056] Figure 4 It is a cross-sectional TEM image of the synaptic device according to the first embodiment of the present application.

[0057] Figure 5 It is a schematic diagram of the transfer curve of the synaptic device according to the first embodiment of the present application.

[0058] Figure 6 It is a schematic diagram of the output curve of the synaptic device according to the first embodiment of the present application.

[0059] Figure 7 It is a test chart of the current change characteristics of the synaptic device according to the first embodiment of the present application under different light conditions, which is used to reflect the long-term plasticity and short-term plasticity of the synaptic device.

[0060] Figure 8 It is a test chart of the current change characteristics of the synaptic device according to the first embodiment of the present application at different light intervals, which is used to reflect the dependence of the long-term potentiation of the synaptic device on different light stimulation intervals.

[0061] Figure 9 It is a test chart of the current change characteristics of the synaptic device according to the first embodiment of the present application under the regulation of different gate pulse voltages, which is used to reflect the long-term potentiation of light stimulation and the long-term depression of gate electric control of the synaptic device.

[0062] Explanation of reference numerals: 1. Substrate; 2. Buffer layer; 3. Bottom electrode layer; 4. Ferroelectric layer; 5. Semiconductor photosensitive layer; 6. Source electrode; 7. Drain electrode. Detailed implementation manners

[0063] Currently, the synaptic electronic devices that are widely studied mainly include memristors with a two-port structure, phase change memories, magnetic memories, ion-gate transistors with a three-port structure, spin transistors, ferroelectric synaptic transistors, etc. It has been found that, compared with other types of synaptic electronic devices, the polarization reversal degree of the ferroelectric thin film in the ferroelectric synaptic transistor can be precisely regulated by an external electric field, and it can exhibit excellent conductance regulation characteristics. Moreover, the ferroelectric synaptic transistor can exhibit excellent properties such as multiple intermediate states, non-volatility, excellent durability, ultra-high linearity, and symmetry, and is very suitable for application in artificial synaptic function simulation and artificial neural network circuits. However, ordinary ferroelectric synaptic transistors rely on electrical pulse excitation and have drawbacks such as a relatively large change in synaptic weight in the first few electrical pulses, limited bandwidth, a large amount of write noise, significant resistance drift, and large interconnect energy loss, presenting technical difficulties.

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0065] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming the first feature "on" or "above" the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact.

[0066] The following will further describe the embodiments of the present invention in detail with reference to the Figures 1-9 accompanying drawings of the specification.

[0067] The embodiments of the present application disclose a synaptic device and a manufacturing method thereof.

[0068] Embodiment 1:

[0069] Refer to Figure 1, the synaptic device includes a substrate 1, a buffer layer 2 grown on the substrate 1, a bottom electrode layer 3 grown on the buffer layer 2, a ferroelectric layer 4 grown on the bottom electrode layer 3, a semiconductor photosensitive layer 5 grown on the ferroelectric layer 4, and a source electrode 6 and a drain electrode 7 grown on the semiconductor photosensitive layer 5 and separated from each other. Among them, the substrate 1 is a flexible substrate, and the buffer layer 2, the bottom electrode layer 3, the ferroelectric layer 4, and the semiconductor photosensitive layer 5 are all thin film structures, and the overall structure of the synaptic device forms a flexible epitaxial ferroelectric gate thin film transistor.

[0070] Specifically, the material of the substrate 1 is selected as mica. By using mica material, the substrate 1 can easily obtain a smooth and flat surface after processing delamination and has good thermal stability. On the other hand, mica material has a high cost performance and is suitable for large-scale production.

[0071] The material of the buffer layer 2 is selected as CoFe 2 O 4 , and the buffer layer 2 is a CoFe 2 O 4 thin film. The CoFe 2 O 4 thin film has good chemical stability and thermal stability, and during the process of fabricating the synaptic device, the CoFe 2 O 4 thin film can make the buffer layer 2 grow densely on the substrate 1, providing a basis for the high-quality growth of subsequent materials. The applicable thickness range of the buffer layer 2 is 5 nm - 10 nm, and in this embodiment, the thickness is preferably 10 nm.

[0072] The material of the bottom electrode layer 3 is selected as SrRuO 3 , and the bottom electrode layer 3 is a SrRuO 3 thin film with a thickness of 60 nm. The SrRuO 3 thin film has good chemical stability and thermal stability, and the SrRuO 3 thin film and the CoFe 2 O 4 thin film have good lattice matching. During the process of fabricating the synaptic device, the SrRuO 3 thin film can grow epitaxially better on the CoFe 2 O 4 thin film, providing a basis for the high-quality growth of subsequent materials. When the thickness of the SrRuO 3 thin film is 30 nm - 60 nm, it can achieve a relatively high conductivity. In this embodiment, the thickness is preferably 60 nm, and in other embodiments, the thickness can be adjusted according to actual parameter requirements.

[0073] The material of the ferroelectric layer 4 is selected as a ferroelectric material. In the structure of the synaptic device, on the one hand, the ferroelectric layer 4 serves as an insulating gate dielectric layer, which can reduce the leakage current; on the other hand, when a gate voltage is applied to the bottom electrode layer 3, a ferroelectric field effect (ferroelectric polarization effect) occurs in the ferroelectric layer 4, causing the polarization of the ferroelectric layer 4 to reverse. The polarization reversal of the ferroelectric layer 4 affects the distribution of hole-electron pairs in the photosensitive semiconductor layer, thereby regulating the conductance of the photosensitive semiconductor layer. Since the direction of the polarization of the ferroelectric layer 4 is regulated by the gate voltage, the purpose of regulating the conductance of the semiconductor photosensitive layer 5 by the gate voltage can be achieved.

[0074] The material of the ferroelectric layer 4 is selected as Pb(Zr 0.2 Ti 0.8 )O 3 , and the ferroelectric layer 4 is a Pb(Zr 0.2 Ti 0.8 )O 3 thin film with a thickness of 230 nm. The Pb(Zr 0.2 Ti 0.8 )O 3 thin film has excellent ferroelectric, piezoelectric and pyroelectric properties, a relatively high Curie temperature, is easy to dope and has good stability. In order to make the Pb(Zr 0.2 Ti 0.8 )O 3 thin film maintain relatively stable ferroelectric properties, reduce the influence of the depolarization field, and achieve precise regulation of the conductance of the semiconductor photosensitive layer 5, a Pb(Zr 0.2 Ti 0.8 )O 3 thin film with a suitable thickness should be selected. The specific thickness range is 160 nm - 250 nm. In this embodiment, the thickness is preferably 230 nm. In other embodiments, according to different ratios, the ferroelectric layer 4 can also be selected from Pb(Zr 0.1 Ti 0.9 )O 3 thin film, Pb(Zr 0.3 Ti 0.7 )O 3 thin film or Pb(Zr 0.5 2Ti 0.48 )O 3 thin film.

[0075] The semiconductor photosensitive layer 5 can respond to light stimuli. Under light illumination of different energies or different wavelengths, the concentration of photo-generated carriers in the semiconductor photosensitive layer 5 will change, thereby changing the conductive ability of the semiconductor photosensitive layer 5.

[0076] The material of the semiconductor photosensitive layer 5 is selected as ZnO, and the semiconductor photosensitive layer 5 is a ZnO thin film. The ZnO thin film is sensitive to ultraviolet light. Under the irradiation of ultraviolet light with different conditions (energy or wavelength), the ZnO thin film can generate different numbers of photo-generated carriers. When a gate voltage is applied to the bottom electrode layer 3 to generate an electric field, the photo-generated carriers move directionally under the electric field, thereby changing the current passing through the source electrode 6 or the drain electrode 7, so as to simulate the basic performance of a biological synapse under the stimulation of an optical signal. Different semiconductor photosensitive layers 5 have different responses to different optical stimuli. In other embodiments, indium gallium zinc oxide (IGZO) can also be selected as the material of the photosensitive semiconductor layer.

[0077] The thickness of the semiconductor photosensitive layer 5 affects its own performance. If the thickness is too small, it will affect its response to optical stimulation and cause the resistance of the semiconductor photosensitive layer 5 to be too large, affecting the performance of the synaptic device; if the thickness is too large, it will affect the on-off ratio of the synaptic device and is not conducive to the polarization regulation of the ferroelectric layer 4; therefore, a ZnO thin film with a suitable thickness needs to be selected, and the specific thickness range is 25 nm - 50 nm. In this embodiment, the thickness is preferably 40 nm.

[0078] The source electrode 6 and the drain electrode 7 are collectively referred to as the source-drain metal electrodes. The material of the source-drain metal electrodes can be Pt, can be Au, or can be Ag. In this embodiment, the material is preferably Au; the applicable thickness range of the source-drain metal electrodes is 60 nm - 120 nm. In this embodiment, the thickness is preferably 100 nm.

[0079] The implementation principle of the synaptic device disclosed in the first embodiment of this application is as follows: When a voltage is applied to the bottom electrode layer 3, a potential difference is formed between the source-drain metal electrodes and the bottom electrode layer 3 to generate an electric field, so that the photo-generated carriers in the semiconductor photosensitive layer 5 move in the direction of the electric field, so as to form a conductive channel between the source-drain metal electrodes. When the source-drain metal electrodes are connected to an external circuit, the source-drain metal electrodes output current.

[0080] Under illumination of different energies or different wavelengths, the concentration of photo-generated carriers changes, resulting in a change in the conductivity of the conductive channel, causing a change in the current value output by the source-drain metal electrodes, thereby simulating the response of a biological synapse to light stimulation. At the same time, the electric field between the source-drain metal electrodes and the bottom electrode layer 3 causes a ferroelectric field effect (ferroelectric polarization effect) in the ferroelectric layer 4, causing the polarization of the ferroelectric layer 4 to reverse, affecting the hole-electron distribution in the photosensitive semiconductor layer, thereby changing the conductivity of the semiconductor photosensitive layer 5, adjusting the conductivity of the conductive channel, and adjusting the current value output by the source-drain metal electrodes. Further, after applying a negative pulse voltage to the bottom electrode layer 3, a decrease in current can be caused, and it is stable during the pulse interval. This non-volatility is unique to the ferroelectric layer 4, and the polarization reversal of the ferroelectric layer 4 under the action of a negative pulse voltage will regulate the conductivity of the photosensitive semiconductor layer, and this regulation can also be non-volatile.

[0081] The degree of polarization reversal of the ferroelectric layer 4 can be precisely regulated by the electric field, showing excellent conductivity regulation performance. The photosensitive semiconductor layer has the characteristics of high-speed response of photo-generated carriers, high bandwidth, and low crosstalk. The combination of the two realizes optoelectronic collaborative regulation, can realize short-term plasticity and long-term plasticity of the synaptic device, and the two plasticities can be switched, simulating the long-term potentiation and long-term depression of biological synapses, having basic neuromorphic learning and memory laws, can simulate human brain neurons and synapses, is applicable to artificial neural network computing, and can perform image recognition through an artificial neural network.

[0082] The ferroelectric synaptic transistors in the related art rely on electrical pulse excitation, and have disadvantages such as a relatively large change in synaptic weight in the first few electrical pulses, limited bandwidth, a lot of write noise, large resistance drift, and large interconnection energy loss. The synaptic device in this application introduces a semiconductor photosensitive layer 5 on the basis of the ferroelectric layer 4, and utilizes the characteristics of high-speed response of photons, high bandwidth, and low crosstalk in the semiconductor photosensitive layer 5 to realize a multifunctional optoelectronic synaptic device based on optoelectronic collaborative regulation, effectively simulating plastic behaviors such as short-term plasticity, long-term plasticity, long-term potentiation, and long-term depression of biological synapses, which is of great significance for realizing artificial neural network computing.

[0083] This embodiment also discloses a manufacturing method of a synaptic device, including the following steps:

[0084] Referring to Figure 1 and Figure 2 , S1, provide the substrate 1.

[0085] S2, through a pulsed laser deposition process, deposit a buffer layer 2 on the substrate 1, that is, deposit CoFe 2 O 4A thin film. Among them, the laser energy is 300 mj, the deposition atmosphere is an oxygen pressure of 50 mTorr, and the substrate temperature is 600 °C.

[0086] S3. Deposit the bottom electrode layer 3 on the buffer layer 2 through a pulsed laser deposition process, that is, deposit SrRuO 2 O 4 thin film on the CoFe 3 thin film. Among them, the laser energy is 300 mj, the deposition atmosphere is an oxygen pressure of 80 mTorr, and the substrate temperature is 600 °C.

[0087] S4. Deposit the ferroelectric layer 4 on the bottom electrode layer 3 through a pulsed laser deposition process, that is, deposit Pb(Zr 3 Ti 0.2 Ti 0.8 )O 3 thin film on the SrRuO

[0088] thin film. Among them, the laser energy is 350 mj, the deposition atmosphere is an oxygen pressure of 200 mTorr, and the substrate temperature is 600 °C. 0.2 Ti 0.8 )O 3 Deposit the ZnO thin film on the Pb(Zr

[0089] thin film and cool it after the deposition is completed. Among them, the laser energy is 270 mj, the deposition atmosphere is an oxygen pressure of 6 mTorr, the substrate temperature is 400 °C, and the cooling method is to cool to room temperature at a rate of 5 °C / min.

[0090] Specifically, the laser energy is the energy density of the laser acting on the surface of the target material, which is a direct factor determining the quality of the thin film. Only when the energy density is high enough can the target material be successfully ablated. A Knudsen layer that ensures the consistency of the sample and the target material composition is formed. We can change the energy density by changing the energy output of the laser and the distance between the quartz lens and the target material.

[0091] The deposition atmosphere directly affects the movement rate and composition of the plasma. During the deposition process, the movement of the plasma sputtered from the surface of the target material will be hindered by the deposition atmosphere. In addition, the deposition atmosphere may react with the plasma, affecting the structural composition of the thin film.

[0092] The substrate temperature affects the diffusion rate of plasma particles after they reach the substrate 1. If the substrate temperature is relatively low, the plasma particles can only diffuse slowly on the surface of the substrate 1 after reaching the substrate 1, affecting the crystallization quality of the thin film; conversely, if the plasma particles move too fast after reaching the substrate 1, they are likely to form agglomerations or evaporate, which also increases the defects in the thin film.

[0093] S6. Through the electrode lithography process, after using photoresist to engrave the required electrode pattern on the semiconductor photosensitive layer 5, metal electrode evaporation is performed to obtain a series of source electrodes 6 and drain electrodes 7. The region between the source electrode 6 and the drain electrode 7 forms a channel, and the finally obtained channel length is about 20 μm, and the channel width is about 0.2 mm.

[0094] In the specific method of step S6, it includes:

[0095] S61. Apply photoresist on the semiconductor photosensitive layer 5, spin-coat the photoresist, and bake the photoresist.

[0096] S62. Use electron beam exposure to expose the designed pattern on the photoresist. After development, the area that needs to be plated with electrodes is exposed, and metal is plated through metal evaporation.

[0097] S63. Strip off the excess photoresist and the excess metal layer to obtain the source electrode 6 and the drain electrode 7. The obtained channel length is about 20 μm, and the channel width is about 0.2 mm.

[0098] The implementation principle of the manufacturing method of the synaptic device disclosed in the first embodiment of the present application is: using the pulsed laser deposition process to prepare the synaptic device, so that the epitaxial growth occurs between the various layers in the synaptic device, making the combination between the various layers closer, the interface clearer, the crystallization quality of the thin film higher, the defects fewer, and the manufacturing process has high replicability.

[0099] Embodiment Two:

[0100] The synaptic device includes a substrate, a buffer layer grown on the substrate, a bottom electrode layer grown on the buffer layer, a ferroelectric layer grown on the bottom electrode layer, a semiconductor photosensitive layer grown on the ferroelectric layer, and source electrodes and drain electrodes that are grown on the semiconductor photosensitive layer and are separated from each other.

[0101] Specifically, the material of the substrate is selected as mica.

[0102] The buffer layer is CoFe 2 O 4A thin film with a thickness of 8 nm.

[0103] The bottom electrode layer is SrRuO 3 thin film with a thickness of 40 nm.

[0104] The ferroelectric layer is Pb(Zr 0.2 Ti 0.8 )O 3 thin film with a thickness of 180 nm.

[0105] The semiconductor photosensitive layer is a ZnO thin film with a thickness of 50 nm.

[0106] The source electrode and the drain electrode are collectively referred to as the source-drain metal electrode. The material of the source-drain metal electrode is Pt, and the thickness is 80 nm.

[0107] The implementation principle of the synaptic device disclosed in the second embodiment of this application is the same as that of the synaptic device in the first embodiment above, and will not be elaborated here.

[0108] This embodiment also discloses a manufacturing method of a synaptic device, including the following steps:

[0109] S1. Provide a substrate.

[0110] S2. Deposit a buffer layer on the substrate through a pulsed laser deposition process, that is, deposit a CoFe 2 O 4 thin film. Among them, the laser energy is 300 mj, the deposition atmosphere is an oxygen pressure of 60 mTorr, and the substrate temperature is 580 °C.

[0111] S3. Deposit a bottom electrode layer on the buffer layer through a pulsed laser deposition process, that is, deposit a SrRuO 2 O 4 thin film on the CoFe 3 thin film. Among them, the laser energy is 300 mj, the deposition atmosphere is an oxygen pressure of 100 mTorr, and the substrate temperature is 580 °C.

[0112] S4. Deposit a ferroelectric layer on the bottom electrode layer through a pulsed laser deposition process, that is, deposit a Pb(Zr 3 Ti 0.2 Ti 0.8 )O 3 thin film. Among them, the laser energy is 350 mj, the deposition atmosphere is an oxygen pressure of 150 mTorr, and the substrate temperature is 580 °C.

[0113] S5. Deposit a semiconductor photosensitive layer on the ferroelectric layer through a pulsed laser deposition process, that is, deposit a Pb(Zr 0.2 Ti 0.8 )O 3Deposit a ZnO thin film on the thin film and cool it after the deposition is completed. Among them, the laser energy is 270 mj, the deposition atmosphere is an oxygen pressure of 4 mTorr, the substrate temperature is 420 °C, and the cooling method is to cool it to room temperature at a rate of 5 °C / min.

[0114] S6. Through the electrode lithography process, after using photoresist to engrave the required electrode pattern on the semiconductor photosensitive layer, evaporate the metal electrode to obtain the source electrode and the drain electrode. The obtained channel length is about 30 um, and the channel width is about 0.3 mm.

[0115] The implementation principle of the manufacturing method of the synaptic device disclosed in the second embodiment of this application is the same as that of the manufacturing method in the first embodiment above, and will not be elaborated here.

[0116] Embodiment 3:

[0117] The synaptic device includes a substrate, a buffer layer grown on the substrate, a bottom electrode layer grown on the buffer layer, a ferroelectric layer grown on the bottom electrode layer, a semiconductor photosensitive layer grown on the ferroelectric layer, and a source electrode and a drain electrode grown on the semiconductor photosensitive layer and separated from each other.

[0118] Specifically, the material of the substrate is selected as mica.

[0119] The buffer layer is a CoFe 2 O 4 thin film with a thickness of 5 nm.

[0120] The bottom electrode layer is a SrRuO 3 thin film with a thickness of 45 nm.

[0121] The ferroelectric layer is a Pb(Zr 0.2 Ti 0.8 )O 3 thin film with a thickness of 250 nm.

[0122] The semiconductor photosensitive layer is a ZnO thin film with a thickness of 25 nm.

[0123] The source electrode and the drain electrode are collectively referred to as the source-drain metal electrodes. The material of the source-drain metal electrodes is Ag, and the thickness is 120 nm.

[0124] The implementation principle of the synaptic device disclosed in the third embodiment of this application is the same as that of the synaptic device in the first embodiment above, and will not be elaborated here.

[0125] This embodiment also discloses a manufacturing method of a synaptic device, including the following steps:

[0126] S1. Provide a substrate.

[0127] S2. Deposit a buffer layer on the substrate through pulsed laser deposition, that is, deposit CoFe 2 O 4 thin film. Among them, the laser energy is 300 mj, the deposition atmosphere is an oxygen pressure of 60 mTorr, and the substrate temperature is 620 °C.

[0128] S3. Deposit a bottom electrode layer on the buffer layer through pulsed laser deposition, that is, deposit SrRuO 2 O 4 thin film on the CoFe 3 thin film. Among them, the laser energy is 300 mj, the deposition atmosphere is an oxygen pressure of 80 mTorr, and the substrate temperature is 620 °C.

[0129] S4. Deposit a ferroelectric layer on the bottom electrode layer through pulsed laser deposition, that is, deposit Pb(Zr 3 Ti 0.2 Ti 0.8 )O 3 thin film on the SrRuO

[0130] thin film. Among them, the laser energy is 350 mj, the deposition atmosphere is an oxygen pressure of 250 mTorr, and the substrate temperature is 620 °C. 0.2 Ti 0.8 )O 3 thin film. Among them, the laser energy is 270 mj, the deposition atmosphere is an oxygen pressure of 10 mTorr, the substrate temperature is 420 °C, and the cooling method is to cool to room temperature at a rate of 5 °C / min.

[0131] S6. Through electrode lithography process, after using photoresist to engrave the required electrode pattern on the semiconductor photosensitive layer, perform metal electrode evaporation to obtain the source electrode and the drain electrode. The obtained channel length is about 100 um, and the channel width is about 1 mm.

[0132] The implementation principle of the manufacturing method of the synaptic device disclosed in the third embodiment of this application is the same as that of the manufacturing method in the first embodiment above, and will not be elaborated here.

[0133] Embodiment 4:

[0134] The synaptic device includes a substrate, a buffer layer grown on the substrate, a bottom electrode layer grown on the buffer layer, a ferroelectric layer grown on the bottom electrode layer, a semiconductor photosensitive layer grown on the ferroelectric layer, and a source electrode and a drain electrode that are grown on the semiconductor photosensitive layer and are separated from each other.

[0135] Specifically, the material of the substrate is selected as mica.

[0136] The buffer layer is CoFe 2 O 4 thin film with a thickness of 6 nm.

[0137] The bottom electrode layer is SrRuO 3 thin film with a thickness of 30 nm.

[0138] The ferroelectric layer is Pb(Zr 0.2 Ti 0.8 )O 3 thin film with a thickness of 160 nm.

[0139] The semiconductor photosensitive layer is ZnO thin film with a thickness of 30 nm.

[0140] The source electrode and the drain electrode are collectively referred to as the source-drain metal electrode. The material of the source-drain metal electrode is Ag with a thickness of 60 nm.

[0141] The implementation principle of the synaptic device disclosed in the fourth embodiment of this application is the same as that of the synaptic device in the first embodiment above, and will not be elaborated here.

[0142] This embodiment also discloses a manufacturing method of a synaptic device, including the following steps:

[0143] S1. Provide a substrate.

[0144] S2. Deposit a buffer layer on the substrate by pulsed laser deposition process, that is, deposit CoFe 2 O 4 thin film. Among them, the laser energy is 300 mj, the deposition atmosphere is 40 mTorr oxygen pressure, and the substrate temperature is 600 °C.

[0145] S3. Deposit a bottom electrode layer on the buffer layer by pulsed laser deposition process, that is, deposit SrRuO 2 O 4 thin film on the CoFe 3 thin film. Among them, the laser energy is 300 mj, the deposition atmosphere is 60 mTorr oxygen pressure, and the substrate temperature is 600 °C.

[0146] S4. Deposit a ferroelectric layer on the bottom electrode layer by pulsed laser deposition process, that is, deposit Pb(Zr 3 thin film on the SrRuO 0.2 Ti 0.8 )O 3 thin film. Among them, the laser energy is 350 mj, the deposition atmosphere is 180 mTorr oxygen pressure, and the substrate temperature is 600 °C.

[0147] S5. Deposit a semiconductor photosensitive layer on the ferroelectric layer by pulsed laser deposition process, that is, deposit Pb(Zr 0.2Ti 0.8 )O 3 Deposit a ZnO thin film on the thin film and cool it after the deposition is completed. Among them, the laser energy is 270 mj, the deposition atmosphere is an oxygen pressure of 3 mTorr, the substrate temperature is 380 °C, and the cooling method is to cool to room temperature at a rate of 5 °C / min.

[0148] S6. Through the electrode lithography process, after using photoresist to engrave the required electrode pattern on the semiconductor photosensitive layer, metal electrode evaporation is performed to obtain the source electrode and the drain electrode. The obtained channel length is about 40 um, and the channel width is about 0.4 mm.

[0149] The implementation principle of the manufacturing method of the synaptic device disclosed in the fourth embodiment of this application is the same as that of the manufacturing method in the first embodiment above, and will not be elaborated here.

[0150] The test data of the synaptic device in the first embodiment are as Figure 2 shown in the figure. A series of test characterization means are performed on the synaptic device to prove the structure and various synaptic characteristics of the above synaptic device.

[0151] Refer to Figure 3 , which is the XRD pattern obtained after performing XRD test on the synaptic device. As can be seen from the figure, the SrRuO 3 thin film of the bottom electrode layer only has a (111) peak, the Pb(Zr 0.2 Ti 0.8 )O 3 thin film of the ferroelectric layer only has a (111) peak, the ZnO thin film of the semiconductor photosensitive layer only has a (002) peak, and no other impurity peaks appear. From this, it can be shown that the SrRuO 3 thin film, Pb(Zr 0.2 Ti 0.8 )O 3 thin film and the ZnO thin film are in an epitaxial growth relationship.

[0152] Refer to Figure 4 , which is the cross-sectional TEM (transmission electron microscope) image of the synaptic device. The figure shows the interface of Mica (substrate) / CFO (buffer layer, CoFe 2 O 4 thin film) / SRO (bottom electrode layer, SrRuO 3 thin film) / PZT (ferroelectric layer, Pb(Zr 0.2 Ti 0.8 )O 3 thin film) / ZnO (semiconductor photosensitive layer, ZnO thin film), further confirming the epitaxial relationship between the thin films of each layer in the synaptic device and showing good crystal quality.

[0153] Refer to Figure 5, is a test chart (one test cycle) of the transfer curve (transfer characteristic curve) of the synaptic device. As can be seen from the figure, the gate voltage VG gradually increases from -6V to 6V, the drain voltage VD = 4V, and the source-drain current IDS increases with the increase of the gate voltage VG and decreases with the decrease of the gate voltage VG in the linear region, indicating the good regulation of the gate voltage on the source-drain current IDS.

[0154] Refer to Figure 6 , is a test chart of the output curve of the synaptic device. As can be seen from the figure, the gate voltage VG gradually increases from 0V to 4V, and the source-drain current IDS linearly increases with the increase of the drain voltage VDS in the linear region. When the device operates in the saturation region, when VG = 4V and VDS = 6V, the maximum saturation current is IDS = 172.18uA, indicating that the synaptic device has good transistor characteristics.

[0155] Refer to Figure 7 , is a test chart of the current change characteristics of the synaptic device. Among them, the synaptic device is tested under ultraviolet light with different conditions and different irradiation times. Curve (a1) in the figure corresponds to the change characteristic curve of the source-drain current IDS after the synaptic device is irradiated with 0.48mW / cm 2 ultraviolet light for 5S; Curve (a2) corresponds to the change characteristic curve of the source-drain current IDS after the synaptic device is irradiated with 0.26mW / cm 2 ultraviolet light for 5S; Curve (a3) corresponds to the change characteristic curve of the source-drain current IDS after the synaptic device is irradiated with 0.18mW / cm 2 ultraviolet light for 2S.

[0156] By comparing Curve (a1), Curve (a2) and Curve (a3), it can be seen that under strong light intensity stimulation, that is, after being stimulated by strong and long-lasting light, the current of the synaptic device above the ground state can be maintained for a long time, corresponding to the long-term plasticity of biological synapses under strong light intensity stimulation; under weak light intensity stimulation, that is, after being stimulated by weak and short-lasting light, the current of the synaptic device above the ground state can be maintained for a short time, corresponding to the short-term plasticity of biological synapses under weak light intensity stimulation.

[0157] Refer to Figure 8 , is a test chart of the current change characteristics of the synaptic device. Among them, the synaptic device is tested under the intermittent irradiation of ultraviolet light with the same conditions. The ultraviolet light is 0.26mW / cm 2, the interval time between two adjacent irradiations is different. In the figure, curve (b1) corresponds to the synaptic device being irradiated with ultraviolet light for 2 s each time, and the interval time between every two irradiations is 3 s; curve (b2) in the figure corresponds to the synaptic device being irradiated with ultraviolet light for 2 s each time, and the interval time between every two irradiations is 10 s; curve (b3) in the figure corresponds to the synaptic device being irradiated with ultraviolet light for 2 s each time, and the interval time between every two irradiations is 20 s.

[0158] By comparing curve (b1), curve (b2) and curve (b3), it can be seen that the shorter the interval time of the ultraviolet light stimulation, that is, the higher the light stimulation frequency, the more photo-generated carriers are generated by the synaptic device, resulting in a larger source-drain current IDS, corresponding to the dependence of the biological synapse on the stimulation frequency.

[0159] Refer to Figure 9 , which is a test chart of the current change characteristics of the synaptic device. Among them, the synaptic device is first given 64 ultraviolet light pulses with an irradiation time of 2 s each time and an interval of 8 s between every two irradiations under ultraviolet light with a power of 0.26 mW / cm 2 , resulting in an increase in the source-drain current IDS, corresponding to the long-term potentiation of the biological synapse; then, the synaptic device is given 64 gate pulse voltages (negative gate pulse voltages) with a pulse peak of -0.5 V, a pulse width of 6 s, and a pulse interval of 4 s. The ferroelectric layer undergoes polarization reversal under the action of the negative gate pulse voltage, regulating the conductance of the photosensitive semiconductor layer, resulting in a decrease in the source-drain current IDS. When the pulse interval is stable, multiple negative gate pulse voltages form a long-term depression effect, making the source-drain current IDS return to the initial state, corresponding to the long-term depression of the biological synapse.

[0160] The above are all preferred embodiments of this application, and the protection scope of this application is not limited by this. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the essence and scope of the technical solutions of the present invention. Therefore, all equivalent changes made according to the structure, shape, and principle of this application should be covered by the protection scope of this application.

Claims

1. A synaptic device, characterized in that, comprising: a substrate (1), the material of the substrate (1) comprising mica material; Buffer layer (2), formed on the substrate (1), the material of the buffer layer (2) being CoFeO 3 , the thickness range of the buffer layer (2) being 5 nm - 10 nm; The bottom electrode layer (3) is formed on the buffer layer (2), and the material of the bottom electrode layer (3) includes SrRuO 3 , and the thickness of the bottom electrode layer (3) is 30 nm - 60 nm; the bottom electrode layer (3) epitaxially grows on the buffer layer (2); A ferroelectric layer (4) is formed on the bottom electrode layer (3), and the material of the ferroelectric layer (4) includes Pb(Zr 0.2 Ti 0.8 )O 3 , and the thickness of the ferroelectric layer (4) is 180 nm - 250 nm; a semiconductor photosensitive layer (5), formed on the ferroelectric layer (4), the material of the semiconductor photosensitive layer (5) comprising ZnO, and the thickness of the semiconductor photosensitive layer (5) being 25 nm - 50 nm; a source electrode (6) and a drain electrode (7), the source electrode (6) and the drain electrode (7) being separately disposed on the semiconductor photosensitive layer (5); the semiconductor photosensitive layer (5) is sensitive to ultraviolet light. Under the irradiation of ultraviolet light between the source electrode (6) and the drain electrode (7), different numbers of photo-generated carriers are generated in the semiconductor photosensitive layer (5), and the photo-generated carriers move directionally under an electric field, thereby changing the current passing through the source electrode (6) or the drain electrode (7) to simulate the response of a biological synapse under optical signal stimulation; A voltage is applied to the bottom electrode layer (3), and a potential difference is generated between the source-drain metal electrodes of the source electrode (6) and the drain electrode (7) and the bottom electrode layer (3) to generate an electric field, so that the photo-generated carriers in the semiconductor photosensitive layer (5) move in the direction of the electric field, so as to form a conductive channel between the source electrode (6) and the drain electrode (7). When the source-drain metal electrodes of the source electrode (6) and the drain electrode (7) are connected to an external circuit, the source-drain metal electrodes output a current I DS ; A negative pulse voltage is applied to the bottom electrode layer (3), resulting in a decrease in the current I DS , and it is stable during the pulse interval. The ferroelectric layer (4) undergoes polarization reversal under the action of the negative pulse voltage, which will regulate the conductance of the semiconductor photosensitive layer (5), and the regulation is non-volatile; Apply 0.26 mW / cm to the synaptic device 2 Under ultraviolet light, 64 ultraviolet light pulse stimulations with each irradiation lasting 2 s and an interval of 8 s between every two irradiations result in the enhancement of the source-drain current I DS , corresponding to the long-term potentiation of biological synapses; After that, a negative gate pulse voltage with 64 pulse peaks of -0.5V, a pulse width of 6S, and a pulse interval of 4S is applied to the synaptic device. The ferroelectric layer (4) undergoes polarization reversal under the action of the negative gate pulse voltage, regulating the conductance of the semiconductor photosensitive layer (5), resulting in the source-drain current I DS to weaken. During the stable pulse interval, multiple negative gate pulse voltages form a long-term inhibitory effect, causing the source-drain current I DS to return to the initial state, corresponding to the long-term inhibitory effect of biological synapses.

2. A manufacturing method of the synaptic device according to claim 1, characterized in that, comprising the following steps: S1. Provide a substrate (1); S2. Deposit a buffer layer (2) on the substrate (1) by pulsed laser deposition; S3. Deposit a bottom electrode layer (3) on the buffer layer (2) by pulsed laser deposition; S4. Deposit a ferroelectric layer (4) on the bottom electrode layer (3) by pulsed laser deposition; S5. Deposit a semiconductor photosensitive layer (5) on the ferroelectric layer (4) by pulsed laser deposition, and perform cooling after the deposition is completed; S6. Through electrode lithography, after using photoresist to engrave the required electrode pattern on the semiconductor photosensitive layer (5), perform metal electrode evaporation to obtain the source electrode (6) and the drain electrode (7).

3. According to the manufacturing method described in claim 2, characterized in that, in the specific method of step S6, it includes: S61. Apply, spin, and bake photoresist on the semiconductor photosensitive layer (5); S62. Use electron beam exposure to expose the designed pattern on the photoresist. After development, the area to be plated with electrodes is exposed, and metal is plated by metal evaporation; S63. Strip off the excess photoresist and the excess metal layer to obtain the source electrode (6) and the drain electrode (7).

4. According to the manufacturing method described in claim 2, characterized in that: in step S2, the deposition atmosphere is 40 mTorr - 60 mTorr, and the substrate temperature is 580 °C - 620 °C; in step S3, the deposition atmosphere is 60 mTorr - 100 mTorr, and the substrate temperature is 580 °C - 620 °C; in step S4, the deposition atmosphere is 150 mTorr - 250 mTorr, and the substrate temperature is 580 °C - 620 °C; in step S5, the deposition atmosphere is 3 mTorr - 10 mTorr, and the substrate temperature is 380 °C - 420 °C.

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