Probe devices, test equipment, and test methods for semiconductor devices

Abstract

A probe device includes: a first receiver configured to receive a multilevel signal having M levels, where M is a natural number greater than 2; a second receiver configured to receive a reference signal; a receive buffer including: a first input connected to the first receiver, a second input connected to the second receiver, and an output configured to output a multilevel signal based on signals received from the first and second inputs; and a resistor circuit including a plurality of resistors connected to the first and second receivers, and determining the magnitude of the termination resistance of the first and second receivers.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0122196, filed on September 22, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to probe devices, test equipment, and test methods for semiconductor devices. Background Technology

[0004] Semiconductor devices can exchange signals with other semiconductor devices in various ways, and the transmitting semiconductor device can encode data into a signal and send it to the receiving semiconductor device. To improve the communication speed between semiconductor devices, various methods have recently been proposed using multi-level signals that differ from non-return-to-zero (NRZ) signals. Summary of the Invention

[0005] The present invention discloses a probe device and a test device, as well as a test method for semiconductor devices using the same. The probe device and the test device can accurately detect and test multi-level signals output by semiconductor devices by connecting a resistor circuit with a control terminal resistor to a receiving terminal.

[0006] According to an example embodiment, a probe device includes: a first receiver configured to receive a multilevel signal having M levels, where M is a natural number greater than 2; a second receiver configured to receive a reference signal; a receive buffer including: a first input connected to the first receiver, a second input connected to the second receiver, and an output configured to output a multilevel signal based on signals received from the first and second inputs; and a resistor circuit including a plurality of resistors connected to the first and second receivers, and determining the magnitude of the termination resistance of the first and second receivers.

[0007] According to an example embodiment, a test apparatus includes: a probe device configured to contact the output pads of a semiconductor device, the semiconductor device being configured to output a multilevel signal having M levels, where M is a natural number greater than 2; and a control device configured to receive the multilevel signal from the probe device and test the semiconductor device using the multilevel signal, wherein the probe device includes: a resistor circuit having: a first receiving end configured to receive the multilevel signal, a second receiving end configured to receive a reference signal, and a plurality of resistors connected to the first receiving end and the second receiving end; and the control device configured to determine the resistance value of the resistor circuit as a termination resistance value for testing the multilevel signal.

[0008] According to an example embodiment, a testing method for a semiconductor device includes: contacting a first pin and a second pin of a probe device with a signal pad and a ground pad of the semiconductor device; setting the resistance value of each of a plurality of variable resistors connected to the first pin and the second pin in the probe device according to the termination method of the semiconductor device; providing a power supply voltage to the semiconductor device; and verifying a multi-level signal output from the signal pad by the semiconductor device, wherein the multi-level signal is a pulse amplitude modulation signal having M levels, where M is a natural number greater than 2. Attached Figure Description

[0009] The above and other aspects, features, and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a simple illustration of a system including semiconductor devices according to an example embodiment;

[0011] Figure 2 and Figure 3 This is a diagram illustrating a multi-level signal output by a semiconductor device according to an example embodiment;

[0012] Figure 4 and Figure 5 This is a simple diagram illustrating a driver that generates multi-level signals in a semiconductor device according to an example embodiment;

[0013] Figure 6 It is a diagram used to illustrate the process of manufacturing a semiconductor device according to an example embodiment;

[0014] Figure 7A , Figure 7B and Figure 8 This is a diagram illustrating a test method for a semiconductor device according to an example embodiment;

[0015] Figure 9A , Figure 9B and Figure 10 This is a diagram illustrating a comparative example of a test method for a semiconductor device according to an example embodiment;

[0016] Figure 11 This is a flowchart illustrating a test method for a semiconductor device according to an example embodiment;

[0017] Figure 12 and Figure 13 This is a simple diagram illustrating a test apparatus according to an example embodiment;

[0018] Figure 14 and Figure 15This is a simple diagram illustrating a probe device according to an example embodiment;

[0019] Figures 16 to 18 This is a diagram illustrating the operation of a probe device according to an example embodiment; and

[0020] Figure 19 This is a simple illustration of a mobile system including semiconductor devices according to an example embodiment. Detailed Implementation

[0021] Preferred exemplary embodiments will be described below with reference to the accompanying drawings.

[0022] Figure 1 This is a simple diagram illustrating a system including semiconductor devices according to an example embodiment.

[0023] refer to Figure 1 The system 10, including the semiconductor device according to the example embodiment, includes a memory controller 20 and a memory device 30, and the memory controller 20 and the memory device 30 can exchange multilevel signals having M levels through at least one of a plurality of channels (DQ, CLK, CA, and DQS), where M is a natural number greater than 2. However, the semiconductor device according to the example embodiment is not limited to the memory controller 20 or the memory device 30, and should be understood to include all semiconductor devices capable of outputting multilevel signals to other semiconductor devices.

[0024] The semiconductor device according to the example embodiment may be a memory controller 20 and / or a memory device 30, and may transmit and / or receive multilevel signals, for example, via a data channel DQ. However, according to the example embodiment, multilevel signals may be transmitted via at least one of a clock channel CLK, a data strobe channel DQS, and a command / address channel CA.

[0025] The memory controller 20 may include a DQS output circuit 21, a data input / output circuit 22, a clock generation circuit 23 (e.g., a clock generator), a command / address signal generator 24, a processor 25, etc. The processor 25 may include at least one core. Components 21 to 25 included in the controller 20 can exchange data with each other via bus 26. The memory device 30 may include a DQS receiving circuit 31, a data input / output circuit 32, a clock receiver 33, a command / address signal receiver 34, and a memory region 35. Components 31 to 35 included in the memory device 30 can exchange data with each other via bus 36. The memory region 35 may include a memory bank having multiple memory cells.

[0026] For example, memory device 30 can receive multilevel signals from memory controller 20 via data channel DQ. As previously mentioned, the multilevel signal can have M levels, and M can be defined as a power of 2. For instance, when M is 2N, N bits of data can be sent from memory controller 20 to memory device 30 during one cycle of the multilevel signal.

[0027] In order for the memory controller 20 and the memory device 30 to accurately exchange multilevel signals, it is necessary to accurately measure, during manufacturing, the mismatches, etc., between the M levels of the multilevel signals output from the memory controller 20 and / or the memory device 30. However, the absolute value of each of the M levels included in the multilevel signal can vary depending on the termination resistance of the driver connected to the output multilevel signal. Therefore, by detecting the multilevel signal while connecting an appropriate termination resistance to the driver, the characteristics of the multilevel signal can be accurately tested.

[0028] After the semiconductor device is packaged, it is mounted on a test board. With the semiconductor device actually connected to another semiconductor device, the characteristics of multi-level signals can be tested. Therefore, by connecting a termination resistor to the driver, the driver can output a multi-level signal, and the characteristics of the multi-level signal can be accurately detected. Conversely, performing accurate testing by connecting a termination resistor to the driver of, for example, a wafer-level semiconductor device before packaging is complete can be difficult.

[0029] In an example embodiment, a probe device capable of measuring multi-level signals by contacting pads or the like of a wafer-level semiconductor device may include a resistor circuit capable of setting a termination resistance level optimized for the driver. The resistor circuit includes multiple resistors connected to pins of the probe device that contact the pads of the semiconductor device, and the termination resistance level can be set according to various termination modes and desired resistance values. Therefore, even before packaging the semiconductor device, the characteristics of the multi-level signals output from the semiconductor device can be accurately measured, and ZQ calibration can be performed precisely.

[0030] Figure 2 and Figure 3 This is a diagram illustrating a multi-level signal output by a semiconductor device according to an example embodiment.

[0031] refer to Figure 2 In the example embodiment, the multi-level signal output by the semiconductor device can have four levels, LV1 to LV4. Figure 2In the example embodiment shown, the semiconductor device can generate a multilevel signal based on a 4-level pulse amplitude modulation (PAM-4) method. When data is transmitted as a multilevel signal generated based on the PAM-4 method, two data bits can be transmitted during one data transmission cycle (PR).

[0032] For example, the four levels LV1 to LV4 can correspond to data

[00] ,

[01] ,

[10] , and

[11] , respectively. Therefore, the semiconductor device can transmit two bits, such as one of

[00] ,

[10] ,

[01] , and

[11] , during a data transmission cycle PR. The semiconductor device receiving the multilevel signal can include a multilevel receiver that recovers data from the multilevel signal. The multilevel receiver can include multiple sense amplifiers, and the multiple sense amplifiers can compare the multilevel signal with multiple reference signals VREF1 to VREF3.

[0033] refer to Figure 3 In the example embodiment, the multi-level signal output from the semiconductor device can have eight levels, LV1 to LV8. Figure 3 In the example embodiment shown, the semiconductor device can generate a multi-level signal based on an 8-level pulse amplitude modulation (PAM-8) method. When data is transmitted as a multi-level signal generated based on the PAM-8 method, three data bits can be transmitted during one data transmission cycle (PR).

[0034] For example, the eight levels LV1 to LV8 can correspond to data

[000] ,

[001] ,

[010] ,

[011] ,

[100] ,

[101] ,

[110] , and

[111] , respectively. Therefore, the semiconductor device can transmit 3 bits during one data transmission cycle PR. In this case, the multilevel receiver can compare the multilevel signal with multiple reference signals VREF1 to VREF7.

[0035] Figure 4 and Figure 5 This is a simple diagram illustrating a driver that generates multi-level signals in a semiconductor device according to an example embodiment.

[0036] according to Figure 4 The driver 40 in the example embodiment shown can output a multi-level signal with four levels. Figure 4In the illustrated example embodiment, driver 40 may include a first driver 41 and a second driver 42. Each of the first driver 41 and the second driver 42 may include a PMOS transistor with a first power supply voltage VDD input and an NMOS transistor with a second power supply voltage VSS input. The second power supply voltage VSS may be ground. The output terminal OUT of driver 40 may be a node connected between the PMOS transistor and the NMOS transistor.

[0037] In an example embodiment, the first driver 41 may be controlled by the low bit D0 of the data determining the multilevel signal, while the second driver 42 may be controlled by the high bit D1 of the data determining the multilevel signal. For example, the complementary value of the low bit D0 is input to the gate of the transistor included in the first driver 41, and the complementary value of the high bit D1 is input to the gate of the transistor included in the second driver 42. As described above, a multilevel signal with four levels can transmit 2 bits of data in one data transmission cycle. As an example, the levels of the multilevel signal, depending on the data and the operation of the first driver 41 and the second driver 42, can be as follows: Figure 2 As shown in Table 1 below.

[0038] [Table 1]

[0039]

[0040] At the same time, according to Figure 5 The driver 50 of the example embodiment shown can output a multi-level signal with eight levels. Figure 5 In the example embodiment shown, driver 50 may include first driver 51 to third driver 53. Each of the first driver 51 to third driver 53 may include a PMOS transistor that receives a first power supply voltage VDD and an NMOS transistor that receives a second power supply voltage VSS.

[0041] The transistor of the first driver 51 is controlled by the complementary value of the low bit D0 of the data determining the multi-level signal, the transistor of the second driver 52 is controlled by the complementary value of the middle bit D1 of the data determining the multi-level signal, and the transistor of the third driver 53 can be controlled by the complementary value of the high bit D2 of the data determining the multi-level signal. As an example, the levels of the multi-level signals according to the data and the operation of the first driver 51 to the third driver 53 can be as follows: Figure 3 And as shown in Table 2 below.

[0042] [Table 2]

[0043]

[0044] Reference Figure 4 and Figure 5In the example embodiment described, the absolute value of each of the levels LV1 to LV4 and LV1 to LV8 can vary depending on the size of the termination resistor connected to the output terminal OUT of each of the drivers 40 and 50. Therefore, in order to accurately test the mismatch of the levels LV1 to LV4 and LV1 to LV8 output from the drivers 40 and 50, termination resistors are connected to the output terminal OUT of the drivers 40 and 50.

[0045] In an example embodiment, the probe device (e.g., a probe card) may include a resistor circuit capable of setting termination resistors, and the probe device contacts a pad connected to an output terminal OUT of a semiconductor device (e.g., in wafer state) including at least one of drivers 40 and 50. The resistor circuit includes multiple resistors, and at least one of the multiple resistors may be a variable resistor. Therefore, wafer-level testing can be performed while the termination resistor is connected to the drivers 40 and 50 included in the semiconductor device, and the accuracy of the testing can be improved. As an example, since multi-level signals can be detected while the termination resistor is connected, level mismatch ratio (RLM), etc., can be accurately tested. In addition, ZQ calibration testing can be performed while changing the resistance value of the termination resistor without the need for an external reference resistor.

[0046] Figure 6 This is a diagram illustrating the process of manufacturing a semiconductor device according to an example embodiment.

[0047] refer to Figure 6 Multiple semiconductor devices can be manufactured by applying semiconductor processes to wafer W, and wafer W can be fabricated. Semiconductor devices can be mounted on wafer W in the form of semiconductor dies. When wafer W is manufactured, a first fusing 61 involving writing data to a first fuse element can be performed. The data written to the first fuse element via the first fusing can include custom data, repair data, and data related to the production / manufacturing history of the semiconductor device.

[0048] Once the first fuse 61 is completed, EDS test 62 can be performed. According to an example embodiment, EDS test 62 may include multiple tests performed sequentially in different environments. For example, EDS test 62 may include a first EDS test and a second EDS test, wherein the first EDS test is performed in a relatively high-temperature environment, while the second EDS test is performed in a relatively low-temperature environment. When EDS test 62 is completed, a second fuse 63 involving rewriting data in the fuse element can be performed. The second fuse 63 may be a process performed taking into account the possibility of data deformation in the fuse element during EDS testing. When the second fuse 63 is completed, a scribing process 64 involving separating the semiconductor die and a packaging assembly process 65 can be performed.

[0049] After the packaging assembly process 65, packaging test 66 can be performed. As an example, packaging test 66 can be performed with the packaged semiconductor device mounted on a test board, etc. The semiconductor device can exchange signals with other semiconductor devices through the test board. Therefore, during packaging test 66, the actual operation of the semiconductor device can be tested through the test board.

[0050] In cases where a semiconductor device includes a driver that generates and outputs multi-level signals, a procedure for testing the multi-level signals can typically be executed during package testing 66. The absolute value of the level of each of the multi-level signals can vary depending on the termination resistor connected to the driver that outputs the multi-level signals. Therefore, to accurately measure the multi-level signals, a termination resistor needs to be connected to the output of the driver. In package testing 66, the semiconductor device is connected to another semiconductor device via a test board; therefore, with the termination resistor connected to the output of the driver, level mismatches and other defects in the multi-level signals can be accurately measured.

[0051] In an example embodiment, even prior to package assembly process 65, a method for accurately testing multilevel signals is proposed. A probe device included in the test apparatus and in contact with an output terminal for outputting the multilevel signal may include a resistor circuit. The resistor circuit may be connected to the pin in contact with the output terminal to provide the termination resistance required for testing the multilevel signal. Therefore, each level of the multilevel signal can be accurately measured prior to package assembly process 65.

[0052] Figure 7A , Figure 7B and Figure 8 This is a diagram illustrating a test method for a semiconductor device according to an example embodiment.

[0053] First, refer to Figure 7A Channel CH and terminating resistor 103 can be connected to the output terminal OUT of driver 100, which outputs a multi-level signal with four levels. Driver 100 includes a first driver 101 and a second driver 102, and the operation of driver 100 can be as described above. Figure 4 As described. For example, the first control signal CTR1 of the first driver 101 may be the complementary value of the low bits of the data that determines the level of the multi-level signal, and the second control signal CTR2 of the second driver 102 may be the complementary value of the high bits of the data that determines the level of the multi-level signal.

[0054] Figure 7B It can be shown Figure 7AThe equivalent circuit 110 of the driver 100 shown is illustrated. Referring to the equivalent circuit 110, a pull-up resistor 111 is connected between the output terminal OUT of the multi-level signal and the first power supply voltage (or first power node) VDD, and a pull-down resistor 112 can be connected between the output terminal OUT and the second power supply voltage (or second power node) VSS. The output terminal OUT can be connected to the terminating resistor 113 via channel CH.

[0055] The value of each of the pull-up resistor 111 and pull-down resistor 112 can be determined based on whether the transistors included in the first driver 101 and the second driver 102 are turned on / off. Hereinafter, the case where the resistance values ​​of the channel CH and the terminating resistor 113 are both R, and the on-resistance of each transistor included in driver 100 is 6R, will be described. The off-resistance of each transistor can be assumed to be infinite.

[0056] For example, when the data transmitted as a multi-level signal is

[00] , the NMOS transistors in the first driver 101 and the second driver 102 can be turned on and the PMOS transistors can be turned off through the first control signal CTR1 and the second control signal CTR2. Therefore, the pull-up resistor 111 is electrically disconnected from the output terminal OUT, and the resistance value of the pull-down resistor 112 is R. Since the first power node and the output terminal OUT are electrically disconnected, the level of the multi-level signal can be the second power supply voltage VSS, such as... Figure 8 As shown.

[0057] Simultaneously, when the data is

[01] , the PMOS transistor in the first driver 101 is turned on, and the NMOS transistor in the second driver 102 is turned on. In this regard, the pull-up resistor 111 has a resistance of 3R, while the pull-down resistor 112 has a resistance of 1.5R. For example... Figure 8 As shown, the level of the multi-level signal can be determined as 2VDD / 9. When the data is

[10] , the NMOS transistor in the first driver 101 is turned on, and the PMOS transistor in the second driver 102 is turned on. The level of the multi-level signal can be determined as 4VDD / 9. When the data is

[11] , the PMOS transistors in the first driver 101 and the second driver 102 are turned on, so that the level of the multi-level signal can be 6VDD / 9.

[0058] When the resistance of channel CH is 0 and the resistance of terminating resistor 113 is R, when the data sent as a multi-level signal is

[00] , the level of the multi-level signal can be determined as the second power supply voltage VSS; when the data sent as a multi-level signal is

[01] , the level of the multi-level signal can be determined as VDD / 6; when the data sent as a multi-level signal is

[10] , the level of the multi-level signal can be determined as 2VDD / 6; when the data sent as a multi-level signal is

[11] , the level of the multi-level signal can be determined as 3VDD / 6.

[0059] For reference Figure 7A , Figure 7B and Figure 8 As shown in the example embodiment, the magnitude of each level in the multi-level signal can vary depending on the resistance value of the terminating resistor. For example, the magnitude of each level in the multi-level signal can change when the terminating resistor is not connected or when the resistance value of the terminating resistor changes. Therefore, in order to accurately test the characteristics of the multi-level signal (e.g., level mismatch ratio (RLM)), the test needs to be performed with the terminating resistor (e.g., in the actual operating environment of the semiconductor device) connected to the output terminal OUT of the driver 100.

[0060] In an example embodiment, the accuracy of the testing process can be improved by including a resistor circuit capable of setting the resistance level at the line terminals in the probe device. For example, when detecting multilevel signals using a conventional probe device that does not include a resistor circuit, multilevel signals with different levels can be detected compared to multilevel signals in the actual operating environment of the semiconductor device. This will be referred to... Figure 9A , Figure 9B and Figure 10 Describe it.

[0061] Figure 9A , Figure 9B and Figure 10 This is a diagram illustrating a comparative example of a test method for a semiconductor device according to an example embodiment.

[0062] Figure 9A This shows the circuit diagram of driver 200. Its structure and operation can be compared with the reference. Figure 7A Those described are similar. Figure 9B The equivalent circuit 210 of the driver 200 is shown. The value of the pull-up resistor 211 can be determined by the on / off state of the PMOS transistor included in the driver 200, while the value of the pull-down resistor 212 can be determined by the on / off state of the NMOS transistor included in the driver 200.

[0063] Similar to a reference Figure 7A , Figure 7Band Figure 8 In the example embodiment described above, assuming the resistance of each transistor is 6R, when the data is

[00] , the level of the multi-level signal can be the second power supply voltage VSS, such as... Figure 10 As shown. Conversely, when the data is

[01] and

[10] , the levels of the multilevel signal are VDD / 3 and 2VDD / 3, respectively. When the data is

[11] , the level of the multilevel signal can be detected as VDD.

[0064] For example, the level of a multilevel signal may differ from the level when the terminating resistor is not connected to the output terminal OUT compared to when the terminating resistor is connected to the output terminal OUT. Therefore, conventional probe equipment that may not be connected to the terminating resistor may not be able to accurately test how the driver 200 outputs a multilevel signal in a real-world operating environment. Conversely, the probe equipment according to the example embodiment includes a resistor circuit capable of setting the value of the terminating resistor, thus allowing for accurate testing of the driver 200's operation using a terminating resistor with a resistance value equal to that of the actual operating environment.

[0065] Figure 11 This is a flowchart illustrating a test method for a semiconductor device according to an example embodiment.

[0066] refer to Figure 11 The testing method for semiconductor devices according to the example embodiment can be started by manufacturing a semiconductor device and producing a wafer (in S10) by performing a semiconductor process on a wafer. The manufactured wafer may be in a state where no scribing process or the like has been applied. In S11, the manufactured wafer can be moved to a testing device.

[0067] A test apparatus is a device used to perform tests on semiconductor devices formed on a wafer, and can be, for example, a probe station. In an example embodiment, the test apparatus may include: a probe device having a plurality of probe pins mounted thereon, and a control device for testing the semiconductor devices using signals measured by the probe device. According to an example embodiment, the test apparatus can contact two or more semiconductor devices with the probe device and perform tests on two or more semiconductor devices simultaneously.

[0068] When the wafer is moved to the test equipment, the probe device can contact the wafer (in S12). The probe device includes multiple exposed pins, and these pins can contact pads formed on each of the semiconductor devices on the wafer. When detecting and testing the characteristics of a multi-level signal using the probe device, the first and second pins included in the probe device can be connected to an output pad that outputs the multi-level signal and a reference pad near the output pad, respectively. The reference pad can be a pad connected to a predetermined reference voltage.

[0069] When the probe device contacts the wafer, the internal resistance of the probe device can be set according to the termination mode (in S13). The probe device includes a resistor circuit connected to a first pin and a second pin. As an example, the resistor circuit may include multiple variable resistors connected to the first pin and the second pin. In S13, the control device of the test equipment can set the resistance value and termination mode of each of the variable resistors according to the actual operating environment of the semiconductor device connected to the probe device.

[0070] When the value of the termination resistor is set by the resistor circuit included in the probe device, power is supplied to the semiconductor device on the wafer, and the probe device can detect multi-level signals (in S14). In S15, the control device can test the multi-level signals detected by the probe device. As previously described, the probe device provides a termination resistor with a resistance level equal to or close to the resistance value in the actual operating environment of the semiconductor device, thus enabling accurate detection of level mismatches in the multi-level signals and precise ZQ calibration of the driver outputting the multi-level signals.

[0071] Figure 12 and Figure 13 This is a simple diagram illustrating a test device according to an example embodiment.

[0072] refer to Figure 12 The test apparatus 300 according to the example embodiment may include a probe station 310 and a control device 320. The probe station 310 may include: a first stage 311 and a second stage 312 on which a wafer W is mounted; a probe holder 313 on which a probe device 314 is mounted; and a probe head 315 for receiving signals from the probe device 314. The probe head 315 may be connected to enable communication with the control device 320.

[0073] When the wafer W is placed on the first stage 311 and the second stage 312 by a wafer transfer device or the like, the position of the wafer W is adjusted by the first stage 311 and the second stage 312 to align with the probe device 314. For example, the first stage 311 can adjust the position of the wafer W in the horizontal direction, while the second stage 312 can adjust the position of the wafer W in the vertical direction.

[0074] Each of the probe devices 314 may include a pin that contacts a pad formed on the semiconductor device of the wafer W. When each of the semiconductor devices of the wafer W includes a driver for outputting a multi-level signal, each of the probe devices 314 may include a first pin PIN1 that contacts an output pad PAD1 that outputs the multi-level signal and a second pin PIN2 that contacts a reference pad PAD2 disposed near the output pad PAD1, such as... Figure 13As shown. According to an example embodiment, in the first direction, the second width W2 of the second pin PIN2 can be greater than the first width W1 of the first pin PIN1. For example, when the semiconductor device is a memory device, the output pad PAD1 that outputs a multi-level signal can be a data output pad that outputs a data signal.

[0075] Before starting the testing and detection of multilevel signals, the resistance value of the resistor circuit connected between the first pin PIN1 and the second pin PIN2 in each probe device 314 can be adjusted. In this case, the resistance value of the resistor circuit can be determined based on the actual operating environment of the semiconductor device, taking into account the termination mode and the size of the termination resistor. When the test begins, the multilevel signal detected by each probe device 314 can be sent to the control device 320. In an example embodiment, the control device 320 may include a device capable of detecting the levels of the multilevel signals, such as an oscilloscope.

[0076] Figure 14 and Figure 15 This is a simple diagram illustrating a probe device according to an example embodiment.

[0077] refer to Figure 14 The testing equipment may include a probe device 400 and a control device 500 connected to the probe device 400. According to an example embodiment, the probe device 400 may include a first receiver 401, a second receiver 402, a receive buffer (BUF) 410, a resistor circuit 420, etc. The first receiver 401 is connected to a first pin of the probe device (e.g., ...). Figure 13 The second receiver 402 is connected to the second pin of the probe device (e.g., PIN1), and can contact the pads of the semiconductor device used for outputting multi-level signals during test operations. Figure 13 The reference signal can be PIN2 in the first receiver 401 and can contact the pads of the semiconductor device for outputting a reference signal during test operations. For example, the reference signal may correspond to a multi-level signal output on the first receiver 401. In some example embodiments, the reference signal may be a ground voltage, a differential signal of a multi-level signal, or... Figure 2 and Figure 3 One of the multiple reference signals in the signal.

[0078] The receive buffer 410 may have a first input terminal connected to the first receive terminal 401, a second input terminal connected to the second receive terminal 402, and an output terminal for outputting a multi-level signal. For example, the receive buffer 410 may be a comparator. The resistor circuit 420 may include a plurality of resistors R1 to R4 connected to the first receive terminal 401 and the second receive terminal 402.

[0079] In an example embodiment, resistor circuit 420 may include a first resistor R1 connected between a first receiving terminal 401 and a first power node 403, a second resistor R2 connected between a second receiving terminal 402 and the first power node 403, a third resistor R3 connected between the first receiving terminal 401 and the second power node 404, and a fourth resistor R4 connected between the second receiving terminal 402 and the second power node 404. Figure 14 In the example embodiment shown, each of the first resistor R1 to the fourth resistor R4 is shown as a variable resistor; however, at least one of the first resistor R1 to the fourth resistor R4 may have a fixed resistance value. A first termination voltage VT may be applied to the first power node 403, and a reference signal may be applied to the second power node 404, for example, a ground voltage less than the first termination voltage VT.

[0080] The control device 500 may include an oscilloscope configured to examine a multi-level signal output from the receive buffer 410.

[0081] The resistance value of each of the first resistors R1 to the fourth resistor R4 and the level of the first termination voltage VT can be determined according to the termination mode. (See below for further details.) Figures 16 to 18 Describe the operation of resistor circuit 420 according to the termination mode.

[0082] Figure 15 This is a diagram illustrating an example embodiment of resistor circuit 420. (Refer to...) Figure 15 The first resistor R1 may include two or more unit circuits, wherein a first switching element TR1 and a first unit resistor element UR1 are connected in series with each other. Each unit circuit may include a switching element and a resistor connected in series with each other. The unit circuits in the first resistor R1 may be connected in parallel with each other. Each of the second resistors R2 to the fourth resistor R4 may have a structure similar to that of the first resistor R1. According to an example embodiment, at least some of the first switching elements TR1 to the fourth switching elements TR4 may have different characteristics, or at least some of the first unit resistor elements UR1 to the fourth unit resistor elements UR4 may have different resistance values. For example, at least some of the first switching elements TR1 to the fourth switching elements TR4 may have different on-resistances. As an example, one or more unit circuits of each of the first resistors R1 to the fourth resistor R4 may have on-resistances different from those of the remaining unit circuits of each of the first resistors R1 to the fourth resistor R4.

[0083] In some embodiments, each of the first switching element TR1 to the fourth switching element TR4 may include multiple transistors. In some example embodiments, each of the first switching element TR1 to the fourth switching element TR4 may include an NMOS transistor. In some example embodiments, each of the first switching element TR1 and the second switching element TR2 may include a PMOS transistor, and each of the third switching element TR3 and the fourth switching element TR4 may include an NMOS transistor.

[0084] A control device 500 connected to the probe device 400 can provide gate signals G0 to G11 to each of the first resistors R1 to the fourth resistors R4 to determine the resistance value of the first resistors R1 to the fourth resistors R4. In this case, the control device 500 may include a code generator configured to generate the gate signals G0 to G11. According to an example embodiment, at least one of the first resistors R1 to the fourth resistors R4 may include only the first switching elements TR1 to the fourth switching elements TR4 without the first unit resistor elements UR1 to the fourth unit resistor elements UR4. In this case, the resistance value of the first resistors R1 to the fourth resistors R4 can be determined by the on-resistance of the first switching elements TR1 to the fourth switching elements TR4.

[0085] Figures 16 to 18 This is a diagram used to illustrate the operation of a probe device according to an example embodiment.

[0086] exist Figure 16 In the example embodiment shown, the termination mode can be a pseudo-open-drain (POD) termination mode. (See reference...) Figure 16 In POD termination mode, each of the second resistors R2 to the fourth resistor R4 can be electrically decoupled from the first receiver 401 and the second receiver 402. As an example, in reference... Figure 15 In the described example embodiment, the second resistors R2 to R4 are turned off by gate signals G3 to G11 input to the second switching element TR2 to the fourth switching element TR4, and the probe device 400 can support POD termination mode. For example, the resistance values ​​of the second resistors R2 to R4 are set to infinity, and the resistance value of the first resistor R1 can be determined as the combined resistance of the first unit resistor element UR1. Therefore, the first resistor R1 can be defined as having a resistance value smaller than that of the second resistors R2 to R4.

[0087] Simultaneously, in POD termination mode, the level of the first termination voltage VT can be set to be greater than the ground level. In an example embodiment, the level of the first termination voltage VT can be equal to the maximum level of the power supply voltage input to the driver of the output multi-level signal. For example, the level of the first termination voltage VT can be the first power supply voltage VDD.

[0088] exist Figure 17 In the example embodiment shown, the termination mode can be center tap termination (CTT). See reference. Figure 17 In center-tap termination mode, the second resistor R2 and the fourth resistor R4 are electrically disconnected from the second receiver 402, and the first resistor R1 and the third resistor R3 can be connected to the first receiver 401. The level of the first termination voltage VT can be equal to the maximum level of the power supply voltage input to the driver of the output multi-level signal, similar to the pseudo-open-drain termination mode. For example, the level of the first termination voltage VT can be the first power supply voltage VDD.

[0089] exist Figure 17 In the example embodiment shown, the first resistor R1 and the third resistor R3 can have the same resistance value. Furthermore, since the second switching element TR2 and the fourth switching element TR4 in the second resistor R2 and the fourth resistor R4 are off, each of the second resistor R2 and the fourth resistor R4 can be defined as having an infinite resistance value. Therefore, the resistance values ​​of the first resistor R1 and the third resistor R3 can be less than the resistance values ​​of the second resistor R2 and the fourth resistor R4.

[0090] exist Figure 18 In the example embodiment shown, the termination mode can be a low-tap termination (LTT) mode. (See reference...) Figure 18 In LTT mode, the second resistor R2 to the fourth resistor R4 are electrically isolated from the first receiver 401 and the second receiver 402, and the first resistor R1 can be connected to the first receiver 401. The first termination voltage VT of the first power node 403 can be set to ground. Similar to POD termination mode, in LTT mode, the resistance value of the first resistor R1 can be defined as less than the resistance values ​​of the second resistor R2 to the fourth resistor R4. In the example embodiment, Figure 18 The resistance value of each of the first resistor R1 to the fourth resistor R4 in the circuit can be equal to... Figure 16 The resistance value of each of the first resistor R1 to the fourth resistor R4 in the circuit.

[0091] Figure 19 This is a simple illustration of a mobile system including semiconductor devices according to an example embodiment.

[0092] refer to Figure 19 The mobile system 1000 may include a camera 1100, a display 1200, an audio processing unit 1300, a modem 1400, dynamic random access memory (DRAM) 1500a and 1500b, flash memory devices 1600a and 1600b, input / output devices 1700a and 1700b, and an application processor (hereinafter referred to as "AP") 1800.

[0093] The mobile system 1000 can be implemented as a laptop computer, portable terminal, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, the mobile system 1000 can be implemented as a server or personal computer.

[0094] Camera 1100 can capture still images or videos under user control. Mobile system 1000 can use the still images / videos captured by camera 1100 to obtain specific information, or it can convert the still images / videos into another type of data, such as text, and store that data. Alternatively, mobile system 1000 can recognize strings included in the still images / videos captured by camera 1100 and provide a corresponding text or audio translation. Therefore, the applications of camera 1100 in mobile system 1000 are becoming increasingly diverse. In an example embodiment, camera 1100 can send data such as still images / videos to AP 1800 via a MIPI-based D-Phy or C-Phy interface.

[0095] Display 1200 can be implemented in various forms, such as liquid crystal display (LCD), organic light-emitting diode (OLED) display, active-matrix organic light-emitting diode (AM-OLED), plasma display panel (PDP), field emission display (FED), or electronic paper. In an example embodiment, display 1200 can also be used as an input device for mobile system 1000 by providing touchscreen functionality. Furthermore, display 1200 can be integrated with a fingerprint sensor or similar device to provide security features for mobile system 1000. In an example embodiment, AP1800 can send image data to be displayed on display 1200 via a MIPI-based D-Phy or C-Phy interface.

[0096] The audio processing unit 1300 can process audio data stored in flash memory devices 1600a and 1600b or audio data included in content received from external sources via modem 1400 or input / output devices 1700a and 1700b. For example, the audio processing unit 1300 can perform various processes on the audio data, such as encoding / decoding, amplification, noise filtering, etc.

[0097] The modem 1400 modulates and transmits signals to send / receive wired / wireless data and demodulates signals received from external sources to recover the original signal. Input / output devices 1700a and 1700b are devices that provide digital input / output and may include ports that can be connected to external recording media, input devices such as touchscreens and mechanical buttons, output devices that output vibrations in a haptic or other manner, etc. In some examples, input / output devices 1700a and 1700b can be connected to external recording media via ports such as USB, Lightning cable, SD card, micro SD card, DVD, and network adapter.

[0098] AP 1800 can control the overall operation of mobile system 1000. Specifically, AP 1800 can control display 1200 so that a portion of the content stored in flash memory devices 1600a and 1600b is displayed on the screen. Furthermore, when user input is received via input / output devices 1700a and 1700b, AP 1800 can perform control operations corresponding to the user input.

[0099] The AP 1800 can be provided as a System-on-Chip (SoC) driving applications, operating systems (OS), etc. Furthermore, the AP 1800 can be included in a single semiconductor package and other devices included in the mobile system 1000, such as DRAM 1500a, flash memory 1620, and / or memory controller 1610. For example, the AP 1800 and at least one or more devices can be provided in packages such as PoP, Ball Grid Array (BGA), Chip Scale Package (CSP), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer Scale Fabrication Package (WFP), Wafer Scale Fabrication Stacked Package (WSP), etc. The kernel of the operating system running on the AP 1800 can include device drivers and I / O schedulers for controlling flash memory devices 1600a and 1600b. The device drivers can control the access performance of flash memory devices 1600a and 1600b by referencing the number of synchronization queues managed by the I / O scheduler, or they can control CPU modes, Dynamic Voltage and Frequency Scaling (DVFS) levels, etc., within the SoC.

[0100] In an example embodiment, the AP 1800 may include a processor block that performs operations or drives applications and / or an operating system, as well as various other peripheral components connected to the processor block via a system bus. Peripheral components may include a memory controller, internal memory, a power management block, an error detection block, a monitoring block, etc. The processor block may include one or more cores; where the processor block includes multiple cores, each core includes a cache memory, and a common cache memory shared by the cores may be included in the processor block.

[0101] In the example embodiment, AP 1800 may also include accelerator block 1820, which is dedicated circuitry for AI data computation. Alternatively, according to the example embodiment, a separate accelerator chip may be provided separately from AP 1800, and DRAM 1500b may be additionally connected to accelerator block 1820 or the accelerator chip. Accelerator block 1820 is a functional block dedicated to performing specific functions of AP 1800, and may include a graphics processing unit (GPU), functional blocks dedicated to processing graphics data, a neural processing unit (NPU), blocks dedicated to performing AI computation and inference, a data processing unit (DPU), blocks dedicated to data transmission, etc.

[0102] According to an example embodiment, the mobile system 1000 may include a plurality of DRAMs 1500a and 1500b. In an example embodiment, the AP 1800 may include a controller 1810 for controlling the DRAMs 1500a and 1500b, and the DRAM 1500a may be directly connected to the AP 1800.

[0103] The AP 1800 controls the DRAM by setting command and mode register settings (MRS) compliant with JEDEC standards, or it can perform communication by setting the specifications and functions required by the mobile system 1000 (e.g., low voltage / high speed / reliability) and the DRAM interface protocol for CRC / ECC. For example, the AP 1800 can communicate with the DRAM 1500a through an interface compliant with JEDEC standards such as LPDDR4 and LPDDR5.

[0104] Alternatively, the AP 1800 can be configured with a new DRAM interface protocol to control the DRAM 1500b used for the accelerator, wherein the accelerator block 1820 or the accelerator chip configured separately from the AP 1800 has a higher bandwidth than the DRAM 1500a, thereby enabling communication.

[0105] Despite Figure 19Only DRAMs 1500a and 1500b are shown, but the configuration of the mobile system 1000 is not necessarily limited to these. Depending on the bandwidth, response speed, and voltage conditions of the AP 1800 or accelerator block 1820, other memories besides DRAMs 1500a and 1500b may also be included in the mobile system 1000. For example, the controller 1810 and / or the accelerator block 1820 can control various memories, such as phase-change RAM (PRAM), static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), hybrid RAM, etc. DRAMs 1500a and 1500b have relatively lower latency and higher bandwidth compared to input / output devices 1700a and 1700b or flash memory devices 1600a and 1600b. DRAM 1500a and 1500b can be initialized at the power-on time of the mobile system 1000, and can be used as a temporary storage location for the operating system and application data or as an execution space for various software codes when the operating system and application data are loaded.

[0106] In DRAMs 1500a and 1500b, arithmetic operations, such as addition / subtraction / multiplication / division, vector operations, address operations, or FFT operation data, can be stored. In another example embodiment, DRAMs 1500a and 1500b can be provided as processing-in-memory (PIM) equipped with computational capabilities. As an example, functions for performing inference within DRAMs 1500a and 1500b can be executed. In this case, inference can be performed using a deep learning algorithm employing an artificial neural network. The deep learning algorithm can include training operations that train a model using various data and inference operations that use the trained model to identify data. For example, the functions used for inference can include the hyperbolic tangent function, the sigmoid function, the rectified linear unit (ReLU) function, etc.

[0107] As an example embodiment, an image captured by a user through camera 1100 can be signal processed and stored in DRAM 1500b, and accelerator block 1820 or accelerator chip can use the data stored in DRAM 1500b and functions for inference to perform AI data operations on the recognition data.

[0108] According to an example embodiment, the mobile system 1000 may include multiple memory devices or multiple flash memory devices 1600a and 1600b with capacities greater than DRAM 1500a and 1500b. Flash memory devices 1600a and 1600b may include a memory controller 1610 and flash memory 1620. The memory controller 1610 receives control commands and data from the AP 1800, and in response to the control commands, writes data to or reads data stored in the flash memory 1620, and may also send the data to the AP 1800.

[0109] According to an example embodiment, the accelerator block 1820 or accelerator chip can use flash memory devices 1600a and 1600b to perform training operations and AI data computation. In the example embodiment, the operational logic capable of performing predetermined operations within the flash memory devices 1600a and 1600b can be implemented in the controller 1610, and the operational logic can use data stored in flash memory 1620 locally to perform at least a portion of the training operations and inference AI data operations performed by AP 1800 and / or accelerator block 1820.

[0110] In the example embodiment, AP 1800 may include interface 1830, so flash memory devices 1600a and 1600b can be directly connected to AP 1800. For example, AP 1800 can be implemented as a SoC, while flash memory device 1600a can be implemented as a separate chip different from AP 1800. AP 1800 and flash memory device 1600a can be mounted in the same package. However, the example embodiment is not limited to this, and multiple flash memory devices 1600a and 1600b can be electrically connected to mobile system 1000 via interconnection.

[0111] Flash memory devices 1600a and 1600b can store data (e.g., still images / videos captured by camera 1100), or data received via a communication network and / or ports included in input / output devices 1700a and 1700b, and can store, for example, augmented reality / virtual reality, high-definition (HD) or ultra-high-definition (UHD) content.

[0112] exist Figure 19 In the illustrated example embodiment, at least a portion of the configuration elements included in the mobile system 1000 can exchange data using multi-level signals. For example, DRAMs 1500a and 1500b and / or flash memory devices 1600a and 1600b can exchange data with AP 1800 using multi-level signals. The probe device according to the illustrated embodiment can be used in devices including drivers that output multi-level signals, such as DRAMs 1500a and 1500b, flash memory devices 1600a and 1600b, AP 1800, etc.

[0113] As described above, according to the example embodiment, before packaging the semiconductor device, a multi-level signal can be detected by allowing the pins of the probe device to contact the pads of the semiconductor device that output a multi-level signal, and by setting the size of the termination resistor in the resistor circuit inside the probe device to be suitable for the multi-level signal. Therefore, the level mismatch ratio (RLM) of the multi-level signal can be accurately measured, and the semiconductor device productivity can be improved by testing the semiconductor device according to various termination resistor conditions.

[0114] The various advantages and beneficial effects of the present invention are not limited to the above description, and will be readily understood in the description of specific embodiments of the present invention.

[0115] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A probe device, comprising: The first receiving end is configured to receive a multi-level signal with M levels, where M is a natural number greater than 2; The second receiver is configured to receive a reference signal; A receive buffer includes: a first input terminal connected to the first receive terminal, a second input terminal connected to the second receive terminal, and an output terminal configured to output the multi-level signal based on signals received from the first input terminal and the second input terminal; and A resistor circuit includes multiple resistors connected to the first receiving terminal and the second receiving terminal, and determines the magnitude of the termination resistance of the first receiving terminal and the second receiving terminal. The resistance value of each of the plurality of resistors is determined according to the termination mode of the semiconductor device.

2. The probe device according to claim 1, wherein, The plurality of resistors in the resistor circuit includes a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein: The first resistor is connected between the first receiving terminal and the first power supply node. The second resistor is connected between the second receiving terminal and the first power node. The third resistor is connected between the first receiving terminal and the second power node, and The fourth resistor is connected between the second receiving terminal and the second power node.

3. The probe device according to claim 2, wherein, At least one of the first resistor, the second resistor, the third resistor, and the fourth resistor is a variable resistor.

4. The probe device according to claim 2, wherein, A first terminal voltage is applied to the first power node, and a second terminal voltage is applied to the second power node. The first termination voltage has a level determined according to the termination mode of the semiconductor device, and the second termination voltage has a fixed level.

5. The probe device according to claim 4, wherein, The level of the first termination voltage is determined according to the termination mode.

6. The probe device according to claim 5, wherein, When the termination mode is a pseudo-open-drain (POD) termination mode, the level of the first termination voltage is set to a first level greater than the ground level, and the resistance value of the first resistor is set to be less than the resistance value of each of the second resistor, the third resistor, and the fourth resistor.

7. The probe device according to claim 5, wherein, When the termination mode is center tap termination (CTT mode), the level of the first termination voltage is set to a first level greater than the ground level, and the resistance value of each of the first resistor and the third resistor is set to be less than the resistance value of each of the second resistor and the fourth resistor.

8. The probe device according to claim 5, wherein, When the termination mode is low tap termination (LTT) mode, the level of the first termination voltage is set to be equal to the level of the second termination voltage, and the resistance value of the first resistor is set to be less than the resistance value of each of the second resistor, the third resistor, and the fourth resistor.

9. The probe device according to claim 2, wherein, Each of the first resistor, the second resistor, the third resistor, and the fourth resistor includes a plurality of unit circuits, each of the plurality of unit circuits having a switching element and a unit resistor connected in series with each other.

10. The probe device according to claim 1, further comprising: The first pin is connected to the first receiving end; as well as The second pin is connected to the second receiving end. Wherein, the first receiving end is configured to receive the multi-level signal through the first pin, and The second receiving end is configured to receive the reference signal through the second pin.

11. The probe device according to claim 1, wherein, The resistor circuit is configured to provide a variable external resistor for performing ZQ calibration of a semiconductor device configured to output the multi-level signal.

12. A testing device, comprising: A probe device is configured to contact the output pads of a semiconductor device, the semiconductor device being configured to output a multilevel signal with M levels, where M is a natural number greater than 2; as well as A control device is configured to receive the multilevel signal from the probe device and use the multilevel signal to test the semiconductor device. The probe device includes a resistor circuit, which has the following characteristics: The first receiving end is configured to receive the multi-level signal. The second receiver is configured to receive a reference signal, and Multiple resistors are connected to the first receiver and the second receiver, and The control device is configured as follows: The resistance value of the resistor circuit is determined as the termination resistance value used to test the multi-level signal, and The resistance value of each of the plurality of resistors is changed according to the termination mode of the semiconductor device.

13. The testing equipment according to claim 12, wherein, The test equipment is configured to test the level mismatch ratio (RLM) of the multilevel signal at the wafer level of the semiconductor device.

14. The testing equipment according to claim 12, wherein, The semiconductor device includes a memory device, and The probe device is configured to contact the data output pads of the memory device.

15. The testing equipment according to claim 12, wherein, The control device is also configured to change the level of the termination voltage applied to the plurality of resistors according to the termination mode of the semiconductor device.

16. The testing apparatus according to claim 15, wherein, When the termination mode is a low-tap termination mode, the resistance value of each of the plurality of resistors is equal to the resistance value of each of the plurality of resistors when the termination mode is a pseudo-open-drain termination mode.

17. The testing apparatus according to claim 15, wherein, The level of the termination voltage when the termination mode is a pseudo-open-drain termination mode is equal to the level of the termination voltage when the termination mode is a center-tap termination mode.

18. The testing apparatus according to claim 12, wherein, The probe device includes a first pin and a second pin that protrude outwards and are adjacent to each other. During the testing of the semiconductor device, the first pin contacts the signal pad of the semiconductor device that outputs the multi-level signal, and the second pin contacts the reference pad of the semiconductor device that outputs the reference signal.

19. A testing method for a semiconductor device, the testing method comprising: The first and second pins of the probe device are made in contact with the signal pads and ground pads of the semiconductor device. According to the termination method of the semiconductor device, the resistance value of each of the plurality of variable resistors in the probe device connected to the first pin and the second pin is set; Provide power supply voltage to the semiconductor device; as well as Verify the multi-level signal output from the signal pad by the semiconductor device. The multi-level signal is a pulse amplitude modulation signal with M levels, where M is a natural number greater than 2.

20. The test method according to claim 19, wherein, Each of the plurality of variable resistors includes at least one unit circuit, the unit circuit having a switching element and a unit resistor connected in series with each other, and When the semiconductor device outputs the multi-level signal, the switching element included in at least one of the plurality of variable resistors is turned off.

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