Differential bus control system, device address allocation method, device and equipment

Abstract

The present application provides a differential bus control system, a device address allocation method, an apparatus and a device, which belong to the field of differential circuit technology. The system includes: a main control device, a plurality of node sub-devices, the main control device is respectively connected to each node sub-device through a differential bus; each node sub-device includes: a device body, a differential drive circuit, a fault detection circuit and a relay circuit; the device body is electrically connected to the differential bus through a differential drive circuit, and the differential drive circuit is used to change the communication transceiver state of the device body; the fault detection circuit is electrically connected to the device body; the relay circuit is electrically connected to the fault detection circuit. The present application can more accurately determine the specific location of the node where the fault occurs, and can avoid the communication disconnection of the differential bus.

Description

Technical Field

[0001] The present application relates to the field of differential circuit technology, and in particular to a differential bus control system, a device address allocation method, a device and a device. Background Art

[0002] A differential bus network usually includes a master control device and multiple sub-nodes, each of which is equipped with a controlled device. In this differential bus network, circuit damage is usually caused by various factors. In order to understand the circuit status in time, it is necessary to obtain the location of the electrical damage in time.

[0003] In the prior art, it is only possible to determine that a circuit failure occurs when the bus circuit is locked; and in the prior art, each sub-node device needs to be manually coded in sequence to repair the corresponding device failure.

[0004] However, the bus circuit may be locked because the driving circuit of one of the sub-devices is damaged, or the bus itself is damaged. It is impossible to determine specifically where the fault occurs in the circuit, and the controlled devices of each sub-node in the network will not perform self-fault diagnosis or set corresponding addresses. This results in the main control device being unable to determine the specific fault address, and accordingly unable to determine the location of the faulty node. In addition, damage to the controlled device of a sub-node will also cause the communication of the entire differential bus to be disconnected. In addition, the efficiency of labeling sub-node devices using artificial sequential coding is relatively low. Summary of the invention

[0005] The purpose of the present application is to provide a differential bus control system, a device address allocation method, an apparatus and a device, which can more accurately determine the specific location of the node where the fault occurs and avoid the communication disconnection of the differential bus.

[0006] The embodiment of the present application is implemented as follows:

[0007] In one aspect of an embodiment of the present application, a differential bus control system is provided, the system comprising: a main control device and a plurality of node sub-devices, the main control device being communicatively connected with each node sub-device via a differential bus;

[0008] Each node sub-device includes: a device body, a differential drive circuit, a fault detection circuit and a relay circuit;

[0009] The device body is electrically connected to the differential bus via a differential drive circuit, and the differential drive circuit is used to change the communication transceiver state of the device body;

[0010] The fault detection circuit is electrically connected to the device body and is used to determine whether the node sub-device has a fault according to the communication transceiver state and the overcurrent state of the device body;

[0011] The relay circuit is electrically connected to the fault detection circuit to control the on / off connection between the differential drive circuit and the differential bus according to the output result of the fault detection circuit. The main control device determines whether there is a fault in the node sub-device based on the on / off connection between the differential drive circuit and the differential bus.

[0012] Optionally, the differential driving circuit is electrically connected to the differential bus via a differential sub-wire, and the fault detection circuit includes: a current detection unit, a judgment unit;

[0013] The current detection unit is used to detect whether there is current in the differential sub-wire to determine the overcurrent state of the device body;

[0014] The judgment unit is electrically connected to the current detection unit and the device body respectively, and is used to judge whether the node sub-device has a fault according to the communication transceiver state and the overcurrent state of the device body.

[0015] Optionally, the current detection unit includes: a Hall current detector and an amplifier, the Hall current detector is electrically connected to the amplifier, and the Hall current detector is used to obtain the overcurrent state of the device body and send it to the judgment unit after amplification by the amplifier.

[0016] Optionally, the relay circuit includes: a first relay driving unit, a first relay;

[0017] The first relay driving unit is electrically connected to the first relay and the fault detection circuit respectively, and is used to control the first relay arranged on the differential sub-line to be connected or disconnected according to the output result of the fault detection circuit.

[0018] Optionally, the node sub-device further includes: a second relay driving unit and a second relay;

[0019] The second relay driving unit is electrically connected to the device body and the second relay respectively. When the node sub-device is powered on for the first time, the device body controls the second relay to be connected through the second relay driving unit.

[0020] Another aspect of an embodiment of the present application provides a method for allocating device addresses, the method being applied to a master control device, the method comprising:

[0021] Send an address query command to the target node sub-device, and receive the query result returned by the target node sub-device;

[0022] If the query result does not include address information, an address is assigned to the target node sub-device.

[0023] Optionally, assigning an address to a target node sub-device includes:

[0024] Determine the address information of the target node sub-device based on the currently allocated address;

[0025] The address information of the target node sub-device is sent to the target node sub-device.

[0026] Optionally, if the query result includes address information, an address query instruction is sent to a subsequent node sub-device of the target node sub-device.

[0027] A device address allocation method is provided, the method is applied to a node sub-device, and the method comprises:

[0028] Receive the address query instruction sent by the master device and determine whether the node sub-device has address information;

[0029] If not, disconnect the node sub-device from the subsequent node sub-device and return the query result to the main control device;

[0030] Receive and store the address information of the node sub-device sent by the master control device;

[0031] Restore the connection between the node sub-device and the subsequent node sub-device.

[0032] Another aspect of the embodiment of the present application provides a fault detection method, which is applied to the above-mentioned main control device, and the method includes:

[0033] Receive the heartbeat packets sent by each node sub-device;

[0034] If the heartbeat packet sent by the target node sub-device is not received within the preset time, it is determined that the target node sub-device has a fault;

[0035] Determine the address information of the target node sub-device.

[0036] Another aspect of the embodiment of the present application provides a device address allocation apparatus, which is applied to a master control device, and includes: a master control sending module, a master control receiving module;

[0037] The main control sending module is used to send an address query instruction to the target node sub-device, and the main control receiving module is used to receive the query result returned by the target node sub-device;

[0038] The main control sending module is also used to allocate an address to the target node sub-device if the query result does not include address information.

[0039] Optionally, the main control sending module is further used to determine the address information of the target node sub-device based on the currently allocated address; and send the address information of the target node sub-device to the target node sub-device.

[0040] Optionally, the main control sending module is further configured to send an address query instruction to a subsequent node sub-device of the target node sub-device if the query result includes address information.

[0041] Another aspect of the embodiment of the present application provides a device address allocation apparatus, which is applied to a node sub-device, and includes: a node receiving module, a node sending module;

[0042] The node receiving module is used to receive the address query instruction sent by the main control device and determine whether the node sub-device has the address information; if not, disconnect the node sub-device from the subsequent node sub-device. The node sending module is used to return the query result to the main control device;

[0043] The node receiving module is also used to receive and store the address information of the node sub-device sent by the main control device; and restore the connection between the node sub-device and the subsequent node sub-device.

[0044] In another aspect of the embodiment of the present application, a fault detection device is provided, which is applied to the above-mentioned main control device, and the device includes: a detection receiving module, a detection judging module and a detection determining module;

[0045] A detection receiving module is used to receive the heartbeat packets sent by each node sub-device;

[0046] A detection and judgment module is used to determine that a target node sub-device fails if a heartbeat packet sent by the target node sub-device is not received within a preset time;

[0047] The detection and determination module is used to determine the address information of the target node sub-device.

[0048] On the other hand, an embodiment of the present application provides a master control device, including: a first memory and a first processor, wherein the first memory stores a computer program that can be run on the first processor, and when the first processor executes the computer program, the steps of the device address allocation method and the fault detection method applied to the master control device are implemented.

[0049] In another aspect of an embodiment of the present application, there is provided an Internet of Things device, including: a second memory and a second processor, wherein the second memory stores a computer program that can be run on the second processor, and when the second processor executes the computer program, the steps of the device address allocation method applied to the node sub-device are implemented.

[0050] In another aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned device address allocation method and fault detection method are implemented.

[0051] The beneficial effects of the embodiments of the present application include:

[0052] In a differential bus control system provided by an embodiment of the present application, a master control device is respectively connected to each node sub-device through a differential bus; each node sub-device includes: a device body, a differential drive circuit, a fault detection circuit and a relay circuit; the device body is electrically connected to the differential bus through a differential drive circuit, and the differential drive circuit is used to change the communication transceiver state of the device body; the fault detection circuit is electrically connected to the device body, and is used to determine whether the node sub-device has a fault according to the communication transceiver state and the overcurrent state of the device body; the relay circuit is electrically connected to the fault detection circuit, and is used to control the on-off connection between the differential drive circuit and the differential bus according to the output result of the fault detection circuit, and the master control device determines whether the node sub-device has a fault based on the on-off connection between the differential drive circuit and the differential bus. Among them, the fault detection of the node sub-device can be realized through the fault detection circuit and the relay circuit, and when there is a fault, the connection between the differential bus and the device is disconnected in time, so as to obtain the fault location more accurately; and by controlling the disconnection from the differential bus, the differential bus can also be prevented from being locked, and the differential bus can be prevented from stopping working, thereby improving the safety and practicality of the differential bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 1 ;

[0055] Figure 2 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 2 ;

[0056] Figure 3 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 3 ;

[0057] Figure 4 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 4 ;

[0058] Figure 5 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 5 ;

[0059] Figure 6 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 6 ;

[0060] Figure 7 Schematic diagram of the process of device address allocation method provided in the embodiment of the present application Figure 1 ;

[0061] Figure 8 Schematic diagram of the process of device address allocation method provided in the embodiment of the present application Figure 2 ;

[0062] Fig. 9 Schematic diagram of the process of device address allocation method provided in the embodiment of the present application Figure 3 ;

[0063] Fig.10 A flowchart of a fault detection method provided in an embodiment of the present application;

[0064] Fig.11 A schematic diagram of the structure of the device address allocation device provided in the embodiment of the present application Figure 1 ;

[0065] Fig.12 A schematic diagram of the structure of the device address allocation device provided in the embodiment of the present application Figure 2 ;

[0066] Fig.13 A schematic diagram of the structure of a fault detection device provided in an embodiment of the present application;

[0067] Fig.14 A schematic diagram of the structure of the main control device provided in the embodiment of the present application;

[0068] Fig.15 A schematic diagram of the structure of the Internet of Things device provided in an embodiment of the present application.

[0069] Icons: 100-main control device; 200-node sub-device; 210-device body; 220-differential drive circuit; 230-fault detection circuit; 231-current detection unit; 2311-Hall current detector; 2312-amplifier; 232-judgment unit; 240-relay circuit; 241-first relay drive unit; 242-first relay; 251-second relay drive unit; 252-second relay; 310-main control sending module; 320-main control receiving module; 330-detection receiving module; 340-detection judgment module; 350-detection determination module; 410-node receiving module; 420-node sending module; 510-first memory; 520-first processor; 610-second memory; 620-second processor. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0071] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0072] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0073] In the description of the present application, it should be noted that the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0074] The specific structure and connection relationship of the differential bus control system provided in the embodiment of the present application are explained in detail below.

[0075] Figure 1 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 1 , please refer to Figure 1 The system includes: a main control device 100, a plurality of node sub-devices 200, the main control device 100 is respectively connected to each node sub-device 200 through a differential bus; each node sub-device 200 includes: a device body 210, a differential drive circuit 220, a fault detection circuit 230 and a relay circuit 240; the device body 210 is electrically connected to the differential bus through the differential drive circuit 220, and the differential drive circuit 220 is used to change the communication transceiver state of the device body; the fault detection circuit 230 is electrically connected to the device body 210, and is used to determine whether the node sub-device 200 has a fault according to the communication transceiver state and the overcurrent state of the device body 210; the relay circuit 240 is electrically connected to the fault detection circuit 230, and is used to control the on-off connection between the differential drive circuit 220 and the differential bus according to the output result of the fault detection circuit 230, and the main control device 100 determines whether the node sub-device 200 has a fault based on the on-off connection between the differential drive circuit 220 and the differential bus.

[0076] Optionally, the master control device 100 may be any computer device, such as a computer, a mobile phone, a tablet computer, a dedicated electronic device, etc., which is not specifically limited here; the node sub-device may be a controlled device, such as a single-chip microcomputer, or other types of controlled devices, which may also be a computer device, which is not specifically limited here. The master control device may determine whether a node sub-device has a fault based on whether each node sub-device has a timed reply heartbeat frame.

[0077] Optionally, the device body 210 may be a single chip microcomputer, a simple logic combination circuit, a control chip with logic processing function, etc., which is not specifically limited here.

[0078] Optionally, the differential driving circuit 220 may be a differential driver, which may implement communication reception by weak pull-up or floating, or communication transmission by pull-down, that is, the communication transceiver state of the entire node sub-device 200 may be changed.

[0079] Optionally, the fault detection circuit 230 may be a logic judgment circuit for performing logic judgment according to an input digital signal to determine whether a node sub-device has a fault.

[0080] Optionally, the relay circuit 240 can control the on and off of the connection between the differential drive circuit and the differential bus based on the judgment result of the fault detection circuit 230. For example: when the judgment result of the fault detection circuit 230 is that there is a fault, the differential drive circuit is controlled to be disconnected from the differential bus; when the judgment result of the fault detection circuit 230 is that there is no fault, the differential drive circuit and the differential bus are controlled to remain closed.

[0081] The following is a detailed explanation of the process of fault detection based on the structure of the above node sub-devices:

[0082] The fault detection circuit 230 obtains two digital signals, namely the communication receiving and transmitting status and the overcurrent status of the device body 210, and determines whether a fault exists based on the two digital signals. When a fault exists, the control relay circuit 240 works to disconnect the connection between the differential drive circuit and the differential bus; when no fault exists, the connection between the differential drive circuit and the differential bus is maintained.

[0083] In a differential bus control system provided by an embodiment of the present application, a master control device is respectively connected to each node sub-device through a differential bus; each node sub-device includes: a device body, a differential drive circuit, a fault detection circuit and a relay circuit; the device body is electrically connected to the differential bus through a differential drive circuit, and the differential drive circuit is used to change the communication transceiver state of the device body; the fault detection circuit is electrically connected to the device body, and is used to determine whether the node sub-device has a fault according to the communication transceiver state and the overcurrent state of the device body; the relay circuit is electrically connected to the fault detection circuit, and is used to control the on-off connection between the differential drive circuit and the differential bus according to the output result of the fault detection circuit, and the master control device determines whether the node sub-device has a fault based on the on-off connection between the differential drive circuit and the differential bus. Among them, the fault detection of the node sub-device can be realized through the fault detection circuit and the relay circuit, and when there is a fault, the connection between the differential bus and the device is disconnected in time, so as to obtain the fault location more accurately; and by controlling the disconnection from the differential bus, the differential bus can also be prevented from being locked, and the differential bus can be prevented from stopping working, thereby improving the safety and practicality of the differential bus.

[0084] The specific structural relationship of the fault detection circuit in the differential bus control system provided in the embodiment of the present application is explained in detail below.

[0085] Figure 2 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 2 , please refer to Figure 2 The differential driving circuit 220 is electrically connected to the differential bus through the differential sub-line, and the fault detection circuit 230 includes: a current detection unit 231 and a judgment unit 232; the current detection unit 231 is used to detect whether there is current in the differential sub-line to determine the overcurrent state of the device body 210; the judgment unit 232 is electrically connected to the current detection unit 231 and the device body 210 respectively, and is used to judge whether the node sub-device 200 has a fault according to the communication transceiver status and the overcurrent state of the device body 210.

[0086] Optionally, the current detection unit 231 may specifically obtain whether there is current in the differential subwire; the judgment unit 232 may specifically be an AND gate logic judger, and the specific judgment basis is as follows:

[0087] When the differential drive circuit 220 works normally, there will be a current signal only when it is in the sending state. For the current signal of the differential sub-line: 1 indicates current, and 0 indicates no current; for the communication transceiver state: 1 indicates the receiving state, and 0 indicates the sending state.

[0088] The truth table is as follows:

[0089] Table 1

[0090] result Current signal Send and receive status damage 1 1 normal 1 0 normal 0 1 Damaged but not locked 0 0

[0091] According to Table 1, it can be known that in both cases, when there is a current signal and the communication is in a receiving state, and when there is no current signal and the communication is in a sending state, it can be considered that the node sub-device has a fault; among them, when there is a current signal and the communication is in a receiving state, it can be characterized as a short circuit fault in the node sub-device, and the relay circuit 240 needs to be disconnected at this time; when there is no current signal and the communication is in a sending state, it can be characterized as an open circuit fault in the node sub-device, and the relay circuit 240 does not need to be disconnected at this time. Therefore, the judgment unit 232 can determine whether the node sub-device has a fault through the logic of the above truth table. Based on this, the fault condition of the node sub-device can also be output when a fault occurs.

[0092] That is, when the inputs of the judgment unit 232 are all 1 or 0, there is a fault. In other cases, it can be considered that the node sub-device has no fault. It should be noted that if there is a fault in the node sub-device, it can be specifically that there is a fault in the differential drive circuit 220. For example, when the inputs of the judgment unit 232 are all 1, it can be considered that there is a short circuit fault in the differential drive circuit 220; when the inputs of the judgment unit 232 are all 0, it can be considered that there is an open circuit fault in the differential drive circuit 220.

[0093] The specific structural relationship of the current detection unit in the differential bus control system provided in the embodiment of the present application is explained in detail below.

[0094] Figure 3 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 3 , please refer to Figure 3 The current detection unit 231 includes: a Hall current detector 2311 and an amplifier 2312. The Hall current detector 2311 is electrically connected to the amplifier 2312. The Hall current detector 2311 is used to obtain the overcurrent state of the device body 210 and send it to the judgment unit 232 after amplification by the amplifier 2312.

[0095] Optionally, the Hall current detector 2311 can be a current sensor that can determine whether there is current in the differential sub-wire by electromagnetic induction. If there is no current in the differential sub-wire, the Hall current detector 2311 does not generate an induced voltage; if there is current in the differential sub-wire, the Hall current detector 2311 generates an induced voltage by electromagnetic induction. Since the induced voltage is small, the current signal can be amplified by the amplifier 2312 to obtain an amplified current. When there is an amplified current, the aforementioned current information is in a state of 1; correspondingly, when there is no amplified induced voltage, the aforementioned current information is in a state of 0. The presence or absence of this current information can reflect the overcurrent state of the node sub-device.

[0096] Optionally, if the differential drive circuit is damaged, the following states may occur: 1. The differential bus level is locked in the idle state; 2. The differential bus is locked in the occupied state. If a device on the bus initiates communication when it is locked in the idle state, an excessive current will be generated when it is connected to the bus, and the Hall current sensor will output a current signal; if it is locked in the occupied state, since the source end of the node sub-device uses a 120-ohm pull-up resistor, a current signal will be output at the damaged node.

[0097] The structural connection relationship and working principle of the relay circuit provided in the embodiment of the present application are explained in detail below.

[0098] Figure 4 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 4 , please refer to Figure 4 The relay circuit 240 includes: a first relay driving unit 241 and a first relay 242; the first relay driving unit 241 is electrically connected to the first relay 242 and the fault detection circuit 230 respectively, and the first relay driving unit 241 is used to control the first relay 242 set on the differential sub-line to be connected or disconnected according to the output result of the fault detection circuit 230.

[0099] Optionally, the first relay driving unit 241 can be a transistor, which can be turned on or off based on the result after the fault detection circuit 230 outputs a result. For example, if the result output by the fault detection circuit 230 is 1, that is, a high-level signal indicating that a fault exists, the first relay driving unit 241 can be turned on based on the signal, thereby controlling the first relay 242 connected thereto to work so that the switch remains disconnected, that is, disconnecting the connection between the differential driving circuit 220 and the differential bus; if the result output by the fault detection circuit 230 is 0, that is, a low-level signal indicating that there is no fault, the first relay driving unit 241 is not turned on based on the signal, thereby causing the first relay 242 to not work, so that the switch remains in a closed state, that is, maintaining the connection between the differential driving circuit 220 and the differential bus.

[0100] Optionally, the fault detection circuit 230 and the differential bus are electromagnetically isolated and the current detection unit 231 has a very strong overload capacity. If an abnormality of the differential bus is detected, the first relay can actively disconnect from the differential bus.

[0101] Optionally, the first relay may be a normally open relay. In the case where the node is completely burned due to severe overload, the first relay may be disconnected from the bus due to mechanical force due to lack of power supply, thereby preventing accidents.

[0102] Another specific structural relationship of the differential bus control system provided in the embodiment of the present application is explained in detail below.

[0103] Figure 5 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 5 , please refer to Figure 5 The node sub-device 200 also includes: a second relay driving unit 251 and a second relay 252; the second relay driving unit 251 is electrically connected to the device body 210 and the second relay 252 respectively. When the node sub-device 200 is powered on for the first time, the device body 210 controls the second relay 252 to be connected through the second relay driving unit 251.

[0104] Optionally, the second relay driving unit 251 may also be a triode, and the second relay 252 may be a normally closed relay. After the entire node sub-device is damaged and powered off due to excessive voltage and current pulses, it is still possible to ensure smooth communication of the subsequent circuit when disconnecting itself.

[0105] Figure 6 A schematic diagram of the structure of the differential bus control system provided in the embodiment of the present application Figure 6 , please refer to Figure 6When the second relay 252 is in a closed state, the node sub-device at the subsequent stage can communicate with the differential bus; when the second relay 252 is in an open state, the node sub-device at the subsequent stage cannot communicate with the differential bus.

[0106] Optionally, each node sub-device 200 can be connected to the bus through the first relay 242 and the second relay 252 respectively. The specific connection relationship can be referred to Figure 6 .

[0107] In the differential control system provided in the embodiment of the present application, the second relay driving unit is electrically connected to the device body and the second relay respectively. When the node sub-device is powered on for the first time, the device body controls the second relay to be connected through the second relay driving unit. The connection relationship between the subsequent node sub-device of the node sub-device and the differential bus can be changed through the second relay. Since the second relay is a normally closed relay, the overall differential bus can be prevented from being unable to work due to damage to a node sub-device on the differential bus, thereby improving the stability and practicality of the system.

[0108] The specific implementation process of the device address allocation method provided in the embodiment of the present application is explained in detail below.

[0109] Figure 7 Schematic diagram of the process of device address allocation method provided in the embodiment of the present application Figure 1 , please refer to Figure 7 , the method is applied to a master control device, the method comprising:

[0110] S610: Send an address query instruction to a target node sub-device, and receive a query result returned by the target node sub-device.

[0111] Optionally, the master control device may send an address query instruction to each node sub-device in sequence, and may receive the query result returned by the node sub-device. The address query instruction and the returned query result may be transmitted via the differential bus.

[0112] If the query result does not include address information, S620: assign an address to the target node sub-device.

[0113] Optionally, the allocated address may be sent to the target node sub-device that does not include address information, and information transmission may be performed specifically through the above-mentioned differential bus.

[0114] Optionally, after sending an address query instruction to the target node sub-device and receiving a query result returned by the target node sub-device, the method further includes:

[0115] If the query result includes address information, S630: sending an address query instruction to a subsequent node sub-device of the target node sub-device.

[0116] Optionally, when the target node sub-device has an address, the above process may be repeated for the node sub-device at the next level of the node sub-device to continue determining the address allocation, thereby obtaining the address status of each node sub-device under the differential bus.

[0117] Another specific implementation process of the device address allocation method provided in the embodiment of the present application is explained in detail below.

[0118] Figure 8 Schematic diagram of the process of device address allocation method provided in the embodiment of the present application Figure 2 , please refer to Figure 8 , assign addresses to the target node sub-devices, including:

[0119] S710: Determine address information of a target node sub-device based on the currently allocated address.

[0120] Optionally, the master control device may allocate addresses based on currently allocated addresses, for example, if the allocated address is 11, the address information of the target node sub-device is 12, or other address information allocation methods may be used, which are not specifically limited here and are only an example.

[0121] S720: Send the address information of the target node sub-device to the target node sub-device.

[0122] Optionally, after the address information of the target node sub-device is determined, the information is sent to the corresponding target node sub-device via a differential bus.

[0123] It should be noted that the above method is mainly aimed at the address allocation method of node sub-devices under the same differential bus. In actual application, each master control device can be connected to multiple differential buses. When the master control device performs address allocation, it can allocate addresses to the node sub-devices in each differential bus in turn, which is specifically the above-mentioned S610-S630 process.

[0124] Optionally, before address allocation, the address of each node sub-device may be cleared by broadcasting an address reset instruction.

[0125] Optionally, each differential bus may be detected in turn whether there is a node sub-device with an unassigned address. If a node sub-device with an unassigned address is detected in the first detection, addresses may be assigned to the node sub-devices in the differential bus, and a second detection may be performed; if there is no node sub-device with an unassigned address in the first detection, the above detection may be performed on other differential buses; if there is a node sub-device with an unassigned address in the second detection, address assignment to the differential bus may be stopped, and the node sub-device may be determined to be a faulty node sub-device; if there is no node sub-device with an unassigned address in the second detection, the above detection may be performed on other differential buses.

[0126] It should be noted that when the master device queries whether there is any node sub-device with unassigned address, if there is, the node sub-device will reply with a result, and the master device can use whether the reply is received as a basis for determining whether there is any node sub-device without address.

[0127] In the device address allocation method provided in the embodiment of the present application, an address query instruction can be sent to the target node sub-device, and the query result returned by the target node sub-device can be received; if the query result does not include address information, an address is allocated to the target node sub-device. Among them, by allocating addresses in the above manner, it is possible to add new nodes and allocate addresses to new nodes without power failure, which can improve the stability and practicality of the circuit; and, by the above manner, the sequential coding can be realized automatically, thereby determining the address of the faulty node more quickly, and thereby repairing the faulty point more conveniently.

[0128] Another specific implementation process of the device address allocation method provided in the embodiment of the present application is explained in detail below.

[0129] Fig. 9 Schematic diagram of the process of device address allocation method provided in the embodiment of the present application Figure 3 , please refer to Fig. 9 , the method is applied to a node sub-device, the method comprising:

[0130] S810: Receive an address query instruction sent by the master device, and determine whether the node sub-device has address information.

[0131] S820: If not, disconnect the node sub-device from the subsequent node sub-device, and return the query result to the main control device.

[0132] S830: Receive and store the address information of the node sub-device sent by the master control device.

[0133] S840: Restore the connection between the node sub-device and the subsequent node sub-device.

[0134] Optionally, when a node sub-device does not have address information, the connection with the subsequent node sub-device can be disconnected, that is, the second relay is controlled to be disconnected through the second relay driving circuit, thereby disconnecting the communication between the main control device and other node sub-devices, and the address is directed to the node sub-device; accordingly, after the address is determined, the connection between the node sub-device and the subsequent node sub-device can be restored, that is, the second relay is controlled to remain normally closed through the second relay driving circuit, thereby allowing the main control device to allocate the address of the subsequent node sub-device.

[0135] Fig.10 For a flow chart of the fault detection method provided in the embodiment of the present application, please refer to Fig.10 , the method comprising:

[0136] S910: Receive the heartbeat packet sent by each node sub-device.

[0137] Optionally, the execution subject of the method may be the aforementioned master device, each node sub-device may send a heartbeat packet to the master device every certain period of time, and the master device may receive the heartbeat packet based on the bus. If received, it may The node sub-device and the main control device are in a state where they can communicate.

[0138] S920: If the heartbeat packet sent by the target node sub-device is not received within a preset time, it is determined that the target node sub-device fails.

[0139] Among them, the heartbeat packet cannot be transmitted when it is determined that the driving circuit of the sub-device of the target node fails.

[0140] Optionally, the preset time can be the transmission time of two heartbeat packets or the time set according to actual needs. No specific limitation is made here. When the heartbeat packet sent by the target node sub-device is not received within the preset time, it can be determined that the target sub-device is disconnected from the main control device, that is, the driving circuit of the target sub-device fails, causing the target sub-device to be disconnected from the bus, thereby making it impossible for the target sub-device to communicate with the main control device, that is, the heartbeat packet sent cannot be received by the main control device.

[0141] The target sub-device may be any one of the multiple sub-devices.

[0142] S930: Determine the address information of the target node sub-device.

[0143] Optionally, after determining that a target sub-device has a fault based on the above-mentioned manner of detecting the heartbeat packet, the address of the target sub-device may be confirmed. Specifically, the address information of the target sub-device may be determined based on the above-mentioned allocation result.

[0144] In a fault detection method provided in an embodiment of the present application, a heartbeat packet sent by each node sub-device can be received. If a heartbeat packet sent by a target node sub-device is not received within a preset time, it is determined that a fault has occurred in the target node sub-device, and the address information of the target node sub-device is determined. Among them, the heartbeat packet method can enable the main control device to promptly determine the target sub-device that has failed, and can determine the corresponding fault address information based on the result of address allocation, thereby improving the stability of the entire system and the fault detection capability, and improving processing efficiency.

[0145] The following describes the apparatus, device, storage medium, etc. corresponding to the device address allocation method provided in the present application for executing. The specific implementation process and technical effects are described above and will not be repeated below.

[0146] Fig.11 A schematic diagram of the structure of the device address allocation device provided in the embodiment of the present application Figure 1 , please refer to Fig.11 , the device is applied to a master control device, and the device comprises: a master control sending module 310, a master control receiving module 320;

[0147] The main control sending module 310 is used to send an address query instruction to the target node sub-device, and the main control receiving module 320 is used to receive the query result returned by the target node sub-device;

[0148] The master control sending module 310 is further used to allocate an address to the target node sub-device if the query result does not include address information.

[0149] Optionally, the master control sending module 310 is further configured to determine the address information of the target node sub-device based on the currently allocated address; and send the address information of the target node sub-device to the target node sub-device.

[0150] Optionally, the master control sending module 310 is further configured to send an address query instruction to a subsequent node sub-device of the target node sub-device if the query result includes address information.

[0151] Fig.12 A schematic diagram of the structure of the device address allocation device provided in the embodiment of the present application Figure 2 , please refer to Fig.12 , the device is applied to a node sub-device, and the device includes: a node receiving module 410, a node sending module 420;

[0152] The node receiving module 410 is used to receive the address query instruction sent by the master device and determine whether the node sub-device has the address information; if not, disconnect the node sub-device from the subsequent node sub-device. The node sending module 420 is used to return the query result to the master device;

[0153] The node receiving module 410 is further used to receive and store the address information of the node sub-device sent by the master control device; and restore the connection between the node sub-device and the subsequent node sub-device.

[0154] Fig.13 For a schematic diagram of the structure of the fault detection device provided in the embodiment of the present application, please refer to Fig.13 , a fault detection device, the device is applied to the above-mentioned main control device, the device includes: a detection receiving module 330, a detection judgment module 340 and a detection determination module 350;

[0155] The detection receiving module 330 is used to receive the heartbeat packet sent by each node sub-device;

[0156] A detection and judgment module 340 is used to determine that the target node sub-device has a fault if no heartbeat packet sent by the target node sub-device is received within a preset time, and the heartbeat packet cannot be transmitted when it is determined that the driving circuit of the target node sub-device has a fault;

[0157] The detection and determination module 350 is used to determine the address information of the target node sub-device.

[0158] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0159] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more microprocessors, or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0160] Fig.14 For a schematic diagram of the structure of the master control device provided in the embodiment of the present application, please refer to Fig.14 The master control device includes: a first memory 510 and a first processor 520. The first memory 510 stores a computer program that can be run on the first processor 520. When the first processor 520 executes the computer program, the steps of the device address allocation method applied to the master control device are implemented, and / or the steps of the fault detection method are implemented.

[0161] Fig.15 For a schematic diagram of the structure of the IoT device provided in the embodiment of the present application, please refer to Fig.15 The IoT device includes: a second memory 610 and a second processor 620. The second memory 610 stores a computer program that can be run on the second processor 620. When the second processor 620 executes the computer program, the steps of the device address allocation method applied to the node sub-device are implemented.

[0162] Optionally, the IoT device may specifically be any one of the aforementioned multiple node sub-devices.

[0163] In another aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned device address allocation method and / or the steps of the above-mentioned fault detection method are implemented.

[0164] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0165] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0166] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0167] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English: Read-Only Memory, abbreviated: ROM), random access memory (English: Random Access Memory, abbreviated: RAM), disk or optical disk and other media that can store program codes.

[0168] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0169] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A differential bus control system, characterized in that: The system comprises: a main control device and a plurality of node sub-devices, wherein the main control device is respectively connected to each of the node sub-devices for communication via a differential bus; Each of the node sub-devices comprises: a device body, a differential drive circuit, a fault detection circuit and a relay circuit; The device body is electrically connected to the differential bus via the differential drive circuit, and the differential drive circuit is used to change the communication transceiver state of the device body; The fault detection circuit is electrically connected to the device body, and is used to determine whether the node sub-device has a fault according to the communication transceiver state and the overcurrent state of the device body; The relay circuit is electrically connected to the fault detection circuit, and is used to control the on-off connection between the differential drive circuit and the differential bus according to the output result of the fault detection circuit, and the main control device determines whether the node sub-device has a fault based on the on-off connection between the differential drive circuit and the differential bus; Wherein, the differential driving circuit is electrically connected to the differential bus through a differential sub-wire, and the fault detection circuit includes: a current detection unit and a judgment unit; The current detection unit is used to detect whether there is current in the differential sub-wire to determine the overcurrent state of the device body; The judgment unit is electrically connected to the current detection unit and the device body respectively, and is used to judge whether the node sub-device has a fault according to the communication transceiver state of the device body and the overcurrent state; Among them, the judgment unit is an AND gate logic judger, and the judgment unit is specifically used to determine whether the node sub-device has a fault based on a pre-established fault logic truth table, the current signal of the differential sub-line and the communication transceiver status of the device body. The fault logic truth table is generated based on the current signal of the differential sub-line and the communication transceiver status of the device body.

2. The system according to claim 1, characterized in that The current detection unit includes: a Hall current detector and an amplifier, wherein the Hall current detector is electrically connected to the amplifier, and the Hall current detector is used to obtain the overcurrent state of the device body and send it to the judgment unit after amplification by the amplifier.

3. The system according to claim 1, characterized in that The relay circuit comprises: a first relay driving unit and a first relay; The first relay driving unit is electrically connected to the first relay and the fault detection circuit respectively, and is used to control the first relay disposed on the differential sub-line to be connected or disconnected according to an output result of the fault detection circuit.

4. The system according to any one of claims 1 to 3, characterized in that: The node sub-device further includes: a second relay driving unit and a second relay; The second relay driving unit is electrically connected to the device body and the second relay respectively. When the node sub-device is powered on for the first time, the device body controls the second relay to be connected through the second relay driving unit.

5. A method for allocating device addresses, characterized in that: The method is applied to the main control device according to any one of claims 1 to 4, and the method includes: Sending an address query instruction to a target node sub-device, and receiving a query result returned by the target node sub-device; If the query result does not include address information, an address is allocated to the target node sub-device.

6. The method according to claim 5, characterized in that The allocating an address to the target node sub-device includes: Determine the address information of the target node sub-device based on the currently allocated address; The address information of the target node sub-device is sent to the target node sub-device.

7. The method according to claim 5, characterized in that After sending the address query instruction to the target node sub-device and receiving the query result returned by the target node sub-device, the method further includes: If the query result includes address information, the address query instruction is sent to the subsequent node sub-device of the target node sub-device.

8. A fault detection method, characterized in that: The method is applied to the main control device according to any one of claims 1 to 4, and the method includes: Receive the heartbeat packets sent by each node sub-device; If the heartbeat packet sent by the target node sub-device is not received within the preset time, it is determined that the target node sub-device has a fault; Determine the address information of the target node sub-device.

9. A method for allocating device addresses, characterized in that: The method is applied to the node sub-device according to any one of claims 1 to 4, and the method comprises: Receive the address query instruction sent by the main control device, and determine whether the node sub-device has address information; If not, disconnect the node sub-device from the subsequent node sub-device and return the query result to the main control device; Receive and store the address information of the node sub-device sent by the master control device; The connection between the node sub-device and the subsequent node sub-device is restored.

10. A device address allocation apparatus, characterized in that: The device is applied to the main control device according to any one of claims 1 to 4, and the device comprises: a main control sending module and a main control receiving module; The master control sending module is used to send an address query instruction to the target node sub-device, and the master control receiving module is used to receive the query result returned by the target node sub-device; The master control sending module is further used to allocate an address to the target node sub-device if the query result does not include address information.

11. A device address allocation apparatus, characterized in that: The device is applied to the node sub-device according to any one of claims 1 to 4, and the device comprises: a node receiving module and a node sending module; The node receiving module is used to receive the address query instruction sent by the main control device, and determine whether the node sub-device has address information; if not, disconnect the node sub-device from the subsequent node sub-device, and the node sending module is used to return the query result to the main control device; The node receiving module is further used to receive and store the address information of the node sub-device sent by the main control device; and restore the connection between the node sub-device and the subsequent node sub-device.

12. A fault detection device, characterized in that: The device is applied to the main control device according to any one of claims 1 to 4, and the device comprises: a detection receiving module, a detection judging module and a detection determining module; The detection receiving module is used to receive the heartbeat packet sent by each node sub-device; The detection and judgment module is used to determine that the target node sub-device has a fault if no heartbeat packet sent by the target node sub-device is received within a preset time; The detection and determination module is used to determine the address information of the target node sub-device.

13. A main control device, characterized in that: include: A first memory and a first processor. The first memory stores a computer program that can be run on the first processor. When the first processor executes the computer program, the steps of the method described in any one of claims 5 to 8 are implemented.

14. An Internet of Things device, characterized in that: include: A second memory and a second processor. The second memory stores a computer program that can be run on the second processor. When the second processor executes the computer program, the steps of the method described in claim 9 are implemented.

15. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the steps of the method described in any one of claims 5 to 9.

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