A timing management method for the disordered state of pins during the power-on process of a microprocessor

Abstract

The present invention discloses a timing management method for the disordered state of pins during the power-on process of a microprocessor. The timing management method for the disordered state of pins during the power-on process of a microprocessor can effectively determine the disordered state of pins during the power-on process of the microprocessor as a low level, that is, a logic "0" output; the circuit includes a microcontroller, an inverter module circuit, and a jumper. The circuit structure of the present invention is simple, and the high and low level timing of the output pins during the power-on process of the microprocessor can be effectively determined, thereby increasing the reliability of the microprocessor circuit system, having universality, and meeting the application needs of all microprocessors.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a timing management method for disordered pin states during the power-on process of a microprocessor. Background Art

[0002] Microprocessors are widely used in intelligent management and process control of electronic equipment such as communication equipment, instruments and meters, medical equipment, and household appliances.

[0003] In various application fields, the microprocessor, as the main control chip, controls the operation of various peripheral circuits through the logic high and low level output of the pins. During the power-on startup process of the microprocessor, the logic high and low level states of its pins are disordered. That is, the output state of the microprocessor pins can be high or low, and this disordered state cannot be confirmed by engineers in the early stage of circuit design. On the other hand, since the microprocessor itself is in the power-on startup process, it cannot control and manage its own pin state.

[0004] Various electronic devices and electronic switches are all high-level effective or high-level enabled. If the microprocessor IO pins that control these electronic devices are at a high level during the startup process, the peripheral circuits controlled by them will also be triggered.

[0005] In many fields controlled by microprocessors, due to power consumption, functionality and other reasons, it is not desirable for the controlled peripheral devices to continue to work during the power-on process of the microprocessor or after the entire system is powered on.

[0006] Therefore, it is necessary to provide a timing management method for the disordered state of pins during the power-on process of the microprocessor, and determine the timing of the pins during the power-on process of the microprocessor as a logic "0" output. Summary of the invention

[0007] The object of the present invention is to provide a timing management method for the disordered state of pins during the power-on process of a microprocessor, which can effectively determine the disordered state of pins during the power-on process of the microprocessor as a low-level logic "0" output.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] A timing management method for the disordered state of pins during the power-on process of a microprocessor is provided, wherein the timing of the pins during the power-on process of the microprocessor is determined as a logic "0" output;

[0010] The circuit includes a microprocessor MCU, an inverter module circuit, and a jumper J1;

[0011] Wherein, the inverter module circuit is composed of a transistor Q1, a pull-up resistor R1, a current limiting resistor R2, and a base-to-ground resistor R3; one end of the pull-up resistor R1 is connected to one end of the power supply VCC, and the other end is respectively connected to the transistor Q1 and one end of the base-to-ground resistor R3, and the other end of the base-to-ground resistor R3 is grounded; one end of the transistor Q1 is connected to one end of the pull-up resistor R1, and the other end of the pull-up resistor R1 is connected to the power supply VCC, and the transistor Q1 serves as the output end of the inverter module circuit;

[0012] The jumper J1 includes a jumper pin 1, a jumper pin 2 and a jumper pin 3, wherein the jumper pin 1 is connected to the inverter module circuit output terminal B, the jumper pin 3 is connected to the microprocessor I / O pin terminal A, and the jumper pin 2 is the pin timing logic "0" output terminal Y after setting;

[0013] When the circuit board is powered on for the first time, the jumper cap is not inserted; during the power-on process, the level of pin 3 of jumper J3, that is, the output level of the microprocessor IO port, is tested. If it is a low level, the jumper cap connects pin 2 and pin 3 of J3; the low level is output to the back-end controlled circuit; if it is a high level, the jumper cap connects pin 1 and pin 2 of J3, that is, the level of the microprocessor IO port is inverted to a low level by the inverter and output to the back-end controlled circuit.

[0014] Furthermore, the selection of jumper pins is achieved by jumper caps;

[0015] During the power-on process of the microprocessor, the high and low level states of the timing logic output by its pins are uncertain; it may be the timing logic "low" or the timing logic "high"; when its timing logic is "low", the control timing logic level directly provided to the controlled unit is "low"; when its timing logic is "high", the inverter module provided by the present invention reverses it, and after its timing state jumps to "low", it is provided to the back-end controlled unit;

[0016] The low level is a logic "0", which means that the output voltage range of the microprocessor IO pin is 0VDC to 0.7VDC, and the high level is a logic "1", which means that the output voltage range of the microprocessor IO pin is 1.7VDC to 3.3V.

[0017] Compared with the prior art, the beneficial effects of the present invention are: the circuit structure of the present invention is simple, universal, and can meet the application requirements of all microprocessors. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a circuit structure principle diagram of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] See also Figure 1 As shown, the present invention provides a technical solution: a timing management method for the disordered state of pins during the power-on process of a microprocessor, which determines the timing of the pins during the power-on process of the microprocessor as a logic "0" output;

[0021] The circuit includes a microprocessor MCU, an inverter module circuit, and a jumper J1;

[0022] Wherein, the inverter module circuit is composed of a transistor Q1, a pull-up resistor R1, a current limiting resistor R2, and a base-to-ground resistor R3; one end of the pull-up resistor R1 is connected to one end of the power supply VCC, and the other end is respectively connected to the transistor Q1 and one end of the base-to-ground resistor R3, and the other end of the base-to-ground resistor R3 is grounded; one end of the transistor Q1 is connected to one end of the pull-up resistor R1, and the other end of the pull-up resistor R1 is connected to the power supply VCC, and the transistor Q1 serves as the output end of the inverter module circuit;

[0023] The jumper J1 includes a jumper pin 1, a jumper pin 2 and a jumper pin 3, wherein the jumper pin 1 is connected to the inverter module circuit output terminal B, the jumper pin 3 is connected to the microprocessor I / O pin terminal A, and the jumper pin 2 is the pin timing logic "0" output terminal Y after setting;

[0024] When the circuit board is powered on for the first time, the jumper cap is not inserted; during the power-on process, the level of pin 3 of jumper J3, that is, the output level of the microprocessor IO port, is tested. If it is a low level, the jumper cap connects pin 2 and pin 3 of J3; the low level is output to the back-end controlled circuit; if it is a high level, the jumper cap connects pin 1 and pin 2 of J3, that is, the level of the microprocessor IO port is inverted to a low level by the inverter and output to the back-end controlled circuit.

[0025] The selection of jumper pins is achieved by jumper caps;

[0026] During the power-on process of the microprocessor, the high and low level states of the timing logic output by its pins are uncertain; it may be the timing logic "low" or the timing logic "high"; when its timing logic is "low", the control timing logic level directly provided to the controlled unit is "low"; when its timing logic is "high", the inverter module provided by the present invention reverses it, and after its timing state jumps to "low", it is provided to the back-end controlled unit;

[0027] The low level is a logic "0", which means that the output voltage range of the microprocessor IO pin is 0VDC to 0.7VDC, and the high level is a logic "1", which means that the output voltage range of the microprocessor IO pin is 1.7VDC to 3.3V.

[0028] Among them, in the inverter module circuit, the pull-up resistor R1 is connected to the power supply VCC; R2 is a current limiting resistor to prevent excessive current flowing through the base from damaging the transistor; the ground resistor R3 plays an important role. First, the ground resistor R3 is equivalent to the pull-down resistor of the base. If the A terminal is suspended, the transistor can be kept in a reliable off state due to the existence of the ground resistor R3; second, the ground resistor R3 can increase the high-level threshold voltage of the transistor to ensure that the transistor is not mis-turned on.

[0029] Specifically, when the microprocessor IO output is low level, there is no current in the transistor base, the transistor is not turned on, and the output terminal B of the inverter has a potential of VCC; when the microprocessor IO output is high level, the transistor is turned on, and the output terminal B of the inverter has a potential of zero.

[0030] The model of the transistor Q1 is MMBT3904LT.

[0031] The power supply +VCC is a DC level of 3.3V.

[0032] In conclusion, the present invention can effectively determine the disordered state of the pins during the power-on process of the microprocessor as a low level, that is, a logic "0" output. The circuit structure of the present invention is simple, and it can effectively determine the high and low level timing of the output pins during the power-on process of the microprocessor, increase the reliability of the microprocessor circuit system, have universality, and can meet the application needs of all microprocessors.

[0033] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A timing management method for the disordered state of pins during the power-on process of a microprocessor, characterized in that: Determine the timing of the pins during the microprocessor power-up process to output a logic "0"; The circuit includes a microprocessor MCU, an inverter module circuit, and a jumper J1; Wherein, the inverter module circuit is composed of a transistor Q1, a pull-up resistor R1, a current limiting resistor R2, and a base-to-ground resistor R3; one end of the pull-up resistor R1 is connected to one end of the power supply VCC, and the other end is respectively connected to the transistor Q1 and one end of the base-to-ground resistor R3, and the other end of the base-to-ground resistor R3 is grounded; one end of the transistor Q1 is connected to one end of the pull-up resistor R1, and the other end of the pull-up resistor R1 is connected to the power supply VCC, and the transistor Q1 serves as the output end of the inverter module circuit; The jumper J1 includes a jumper pin 1, a jumper pin 2 and a jumper pin 3, wherein the jumper pin 1 is connected to the inverter module circuit output terminal B, the jumper pin 3 is connected to the microprocessor I / O pin terminal A, and the jumper pin 2 is the pin timing logic "0" output terminal Y after setting; When the circuit board is powered on for the first time, the jumper cap is not inserted; during the power-on process, the level of pin 3 of jumper J3, that is, the output level of the microprocessor IO port, is tested. If it is a low level, the jumper cap connects pin 2 and pin 3 of J3; the low level is output to the back-end controlled circuit; if it is a high level, the jumper cap connects pin 1 and pin 2 of J3, that is, the level of the microprocessor IO port is inverted to a low level by the inverter and output to the back-end controlled circuit.

2. The timing management method for the disordered pin state during the power-on process of a microprocessor according to claim 1, characterized in that: The selection of jumper pins is achieved by jumper caps; During the power-on process of the microprocessor, the high and low level states of the timing logic output of its pins are uncertain; it may be the timing logic "low" or the timing logic "high"; when its timing logic is "low", the control timing logic level directly provided to the controlled unit is "low"; When its timing logic is "high", the inverter module reverses it, making its timing state jump to "low" and then provides it to the back-end controlled unit; The low level is logic "0", which means that the output voltage range of the microprocessor IO pin is 0VDC~0.7VDC, and the high level is logic "1", which means that the output voltage range of the microprocessor IO pin is 1.7VDC~3.3V.

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