Hybrid Channel Storage Device

Abstract

A hybrid-channel storage device is provided. The provided hybrid-channel storage device includes a control component and NVM chips. The control component includes a media interface controller for coupling a plurality of NVM chips; the media interface controller couples the plurality of NVM chips through a plurality of channels; a first channel among the plurality of channels couples the plurality of NVM chips; a first NVM chip among the plurality of NVM chips has a first type, and a second NVM chip among the plurality of NVM chips has a second type; wherein, the first type is different from the second type; the media interface controller includes a micro-instruction storage unit, a micro-instruction execution unit, and a signal driver; the micro-instruction execution unit executes a micro-instruction sequence to operate the signal driver to provide signals to the plurality of channels.

Description

Technical Field

[0001] This application relates to storage device technology, and particularly to a storage device with a hybrid channel, its controller, and a method for providing a hybrid channel. Background Art

[0002] Figure 1 A block diagram of a storage device is shown. The storage device 102 is coupled to a host and is used to provide storage capabilities for the host. The host and the storage device 102 can be coupled in various ways, including but not limited to coupling the host to the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, a wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device in the above ways. For example, a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105, and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, and software is executed in the processor or controller to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. The FTL table and / or the data of the cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash interface controller (or also known as a media interface controller, a flash channel controller). The flash interface controller is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105 and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc. Examples of media interface controllers are provided in the Chinese patent with the application number 201510253428.1 and the patent name "Micro-instruction Sequence Execution Method and Its Device", where storage medium access commands are applied to the NVM chip by executing micro-instructions. Examples of media interface controllers are also provided in the Chinese patent application with the application number 2020106080147 and the patent name "Adaptive NVM Reading Method and Its Device", the Chinese patent application with the application number "202010615178.2" and the patent name "Intelligent Read Redo Method and Its Media Interface Controller", the Chinese patent application with the application number "202010207004.2" and the patent name "Media Interface Controller and Storage Controller for Read Command Fusion", the Chinese patent with the application number 201810380329.3 and the patent name "Method and Device for Out-of-Order Execution of NVM Commands", and the Chinese patent application with the application number 201610836531.3 and the patent name "Method and Device for Generating NVM Chip Interface Commands".

[0007] The NVM chip includes one or more Logic Units (LUNs). One or more dies may be included within the NVM chip package. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within the NVM chip can execute commands and report status independently of each other. The meanings of target, logic unit, and plane are provided in the "Open NAND Flash Interface Specification (Revision 3.0)" available at http: / / www.micron.com / ~ / media / Documents / Products / Other%20Documents / ONFI3_0Gold.ashx, which is part of the prior art. In this application, unless otherwise indicated, the terms Target and Logic Unit (LUN) can be used interchangeably.

[0008] NVM chips typically store and read data by page, and erase data by block. A block (also referred to as a physical block) contains multiple pages (also referred to as physical pages). A physical page has a fixed size, such as 17,664 bytes. A physical page can also have other sizes.

[0009] In a storage device, the Flash Translation Layer (FTL) is used to maintain the mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of the storage device as perceived by upper-layer software such as the operating system. Physical addresses are the addresses used to access the physical storage units of the storage device. In the related art, address mapping can also be implemented using an intermediate address form. For example, a logical address is mapped to an intermediate address, and then the intermediate address is further mapped to a physical address.

[0010] The table structure that stores the mapping information from logical addresses to physical addresses is called the FTL table. The FTL table is important metadata in the storage device. Typically, the data items in the FTL table record the address mapping relationship in the storage device in units of data pages.

[0011] The FTL of some storage devices is provided by the host coupled to the storage device. The FTL table is stored in the host's memory, and the host's processor executes software to provide the FTL. There are also some storage management devices provided between the host and the storage device that provide the FTL.

[0012] Figure 2 A detailed block diagram of the control component of the storage device is shown.

[0013] The host accesses the storage device with an IO command that follows the storage protocol. The control component generates one or more storage commands according to the IO command from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that follow the interface protocol of the NVM chip according to the storage commands. The control component also tracks that all storage commands generated from one IO command have been executed and completed, and indicates the processing result of the IO command to the host.

[0014] See Figure 2 , the control component includes, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface obtains the IO command provided by the host and generates a storage command to provide to the storage command processing unit. The storage commands access the same size of storage space, for example, 4KB. The data unit corresponding to the data accessed by one storage command recorded in the NVM chip is called a data frame. A physical page records one or more data frames. For example, if the size of a physical page is 17664 bytes and the size of a data frame is 4KB, then one physical page can store 4 data frames.

[0015] The storage media management unit maintains the conversion from logical address to physical address for each storage command. For example, the storage media management unit includes an FTL table. For a read command, the storage media management unit outputs the physical address corresponding to the logical address accessed by the storage command. For a write command, the storage media management unit allocates an available physical address for it and records the mapping relationship between the accessed logical address and the allocated physical address. The storage media management unit also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0016] The storage command processing unit operates the media interface controller to issue a storage media access command to the NVM chip according to the physical address provided by the storage media management unit. For the purpose of clarity, the command sent by the storage command processing unit to the media interface controller is called a media interface command, and the command sent by the media interface controller to the NVM chip is called a storage media access command. The storage media access command follows the interface protocol of the NVM chip.

[0017] Figure 3 Shows the media interface controller.

[0018] The media interface controller includes a microinstruction memory, a microinstruction execution unit, and a signal driver. The media interface controller is also coupled to the NVM chip. The media interface controller provides a storage media access command to the NVM chip and obtains the processing result of the storage media access command. The microinstruction memory stores a sequence of microinstructions.

[0019] The media interface controller receives the media interface command provided by the storage command processingFigure 3 shown as CMD). The micro-instruction sequence corresponds to the media interface command. The media interface controller obtains the corresponding micro-instruction sequence according to the received media interface command and provides it to the micro-instruction execution unit. The micro-instruction execution unit executes the micro-instruction sequence, drives the signal driver according to the signals indicated by the micro-instruction sequence, and generates specified signals on the leads where the media interface is coupled to the NVM chip. And by executing the micro-instruction sequence, a signal sequence that conforms to the NVM chip interface protocol is generated. The signal driver also collects signals from the leads, for example, collects the data read from the NVM chip from the DQ lead.

[0020] There are various types of NVM chips. Various types of NVM chips, for example, come from different suppliers, follow different NVM chip interface protocols (such as, "Toggle", "ONFI", etc.), and provide different features for different application scenarios (such as, low latency, large capacity, high durability, etc.).

[0021] The media interface controller couples the NVM chip through a channel. To increase the storage density and balance the number of pins of the controller chip, usually 2 or more NVM chips (or coupled to the channel in units of LUN or Target) are coupled to a single channel. Multiple Targets coupled to the same channel share the bus (including the control bus and the data bus) to reduce the number of pins used to couple the NVM chip to the media interface controller. The channel provides its dedicated chip enable (CE) signal for each Target coupled to the channel to avoid transmitting signals to more than one Target at any time.

[0022] Each NVM chip coupled to the same channel usually has the same type, so that the media interface controller can operate all NVM chips in the same way. Summary of the Invention

[0023] Some application systems need to utilize different types of NVM chips to meet diverse performance requirements. For example, CDN (Content Delivery Network) requires better read performance, while enterprise-level applications require higher data reliability. Inside a storage device, there is also a growing demand for diverse NVM chip types. For example, for the critical metadata of a storage device, it needs to be accessed (read and / or written) with low latency; for a storage device capable of distinguishing between cold / hot data, it is desired that the storage medium for cold data has better retention while the storage medium for hot data has better endurance and / or access latency. Thus, there is a need to couple different types of NVM chips on the same control component within a storage device. Further, it is desired to couple different types of NVM chips on the same channel. However, NVM chips on the same channel share a bus, and when the types of these NVM chips are different, the way to drive one type of NVM chip is likely to be ineffective in driving another type of NVM chip, which poses a challenge to the media interface controller.

[0024] Coupling different types of NVM chips on the same control component also poses challenges to the management of the storage medium. It is necessary to distinguish the storage spaces provided by different NVM chips, and it is also desired to maintain a low technical complexity for the introduction of new functions.

[0025] According to a first aspect of the present application, there is provided a first control component according to the first aspect of the present application, including a media interface controller for coupling a plurality of NVM chips; the media interface controller couples the plurality of NVM chips through a plurality of channels; a first channel among the plurality of channels couples a plurality of NVM chips; a first NVM chip among the plurality of NVM chips has a first type, and a second NVM chip among the plurality of NVM chips has a second type; wherein, the first type is different from the second type.

[0026] According to the first control component of the first aspect of the present application, there is provided a second control component according to the first aspect of the present application, wherein the first type is the SLC type and the second type is the TLC type.

[0027] According to the first or second control component of the first aspect of the present application, there is provided a third control component according to the first aspect of the present application, wherein a second channel among the plurality of channels couples a second plurality of NVM chips; a third NVM chip among the second plurality of NVM chips has a third type, and a fourth NVM chip among the second plurality of NVM chips has a fourth type; wherein, the third type is different from the fourth type.

[0028] According to the first control component of the first aspect of the present application, a fourth control component according to the first aspect of the present application is provided, wherein the media interface controller includes a signal driver, and signals are provided to the plurality of channels through the signal driver.

[0029] According to one of the first to fourth control components of the first aspect of the present application, a fifth control component according to the first aspect of the present application is provided, wherein the media interface controller further includes a plurality of NVM configuration register groups, and each NVM configuration register group includes a plurality of registers storing the characteristics of the NVM chip.

[0030] According to the fifth control component of the first aspect of the present application, a sixth control component according to the first aspect of the present application is provided, wherein the NVM configuration register group includes a time constraint configuration register, an address format configuration register, a data length configuration register, and / or a command format configuration register.

[0031] According to the fifth or sixth control component of the first aspect of the present application, a seventh control component according to the first aspect of the present application is provided, wherein according to the type of the NVM chip to be accessed, the characteristics of the type of the NVM chip to be accessed are obtained from the corresponding NVM configuration register group; the signal driver provides signals to the NVM chip to be accessed through the channel according to the obtained characteristics.

[0032] According to the seventh control component of the first aspect of the present application, an eighth control component according to the first aspect of the present application is provided, wherein the media interface controller further includes a plurality of cache units; the data read from the first NVM chip is stored in the first cache unit among the plurality of cache units; the data to be written to the second NVM chip is also stored in the first cache unit.

[0033] According to the eighth control component of the first aspect of the present application, a ninth control component according to the first aspect of the present application is provided, wherein the first NVM chip serves as a cache for the second NVM chip.

[0034] According to one of the first to ninth control components of the first aspect of the present application, a tenth control component according to the first aspect of the present application is provided, wherein the media interface controller includes a micro-instruction storage unit, a micro-instruction execution unit, and a signal driver; the micro-instruction execution unit executes a micro-instruction sequence to operate the signal driver to provide signals to the plurality of channels.

[0035] According to the tenth control component of the first aspect of the present application, an eleventh control component according to the first aspect of the present application is provided, wherein the microinstruction memory stores a plurality of microinstruction sequences; the plurality of microinstruction sequences include a microinstruction sequence for processing a media interface command and a plurality of microinstruction sequences for providing a storage media access command to the NVM chip; the microinstruction sequence for processing the media interface command is executed, and the microinstruction sequence for providing the storage media access command corresponding to the media interface command is called.

[0036] According to the eleventh control component of the first aspect of the present application, a twelfth control component according to the first aspect of the present application is provided, wherein the plurality of microinstruction sequences for providing a storage media access command to the NVM chip include a microinstruction sequence for providing a programming command to the first type of NVM chip and a microinstruction sequence for providing a programming command to the second type of NVM chip.

[0037] According to the eleventh or twelfth control component of the first aspect of the present application, a thirteenth control component according to the first aspect of the present application is provided, wherein the microinstruction execution unit further includes a plurality of NVM configuration register groups, and each NVM configuration register group includes a plurality of registers storing the characteristics of the NVM chip; the type flag is also set when the microinstruction sequence for processing the media interface command is executed; the microinstruction execution unit accesses one of the plurality of NVM configuration register groups according to the type flag, and operates the signal driver to provide signals to the plurality of channels using the characteristics of the NVM chip obtained by accessing one of the plurality of NVM configuration register groups.

[0038] According to the thirteenth control component of the first aspect of the present application, a fourteenth control component according to the first aspect of the present application is provided, wherein the microinstruction execution unit further includes a microinstruction decoder and a plurality of signal generation units; the microinstruction decoder provides the microinstruction to one of the plurality of signal generation units according to the meaning of the microinstruction; the microinstruction decoder also selects one or more of the plurality of registers of one of the plurality of NVM configuration register groups according to the type flag and provides them to one or more of the plurality of signal generation units; the signal generation unit operates the signal driver to provide signals to one of the plurality of channels according to the microinstruction provided by the microinstruction decoder and the characteristics obtained from one of the plurality of NVM configuration register groups.

[0039] According to the fourteenth control component of the first aspect of the present application, a fifteenth control component according to the first aspect of the present application is provided, wherein the plurality of signal generation units include a command signal generation unit, an address signal generation unit, and / or a data transfer signal generation unit; the command signal generation unit generates a command header of a storage media access command according to the microinstruction, and also obtains time constraint information from the time constraint configuration register of the NVM configuration register group to generate an ALE signal and / or a CLE signal on the channel.

[0040] According to the fourteenth or fifteenth control component of the first aspect of the present application, a sixteenth control component according to the first aspect of the present application is provided, wherein the address signal generation unit generates an address part of a storage medium access command according to a micro-instruction, and also obtains an address format from an address format configuration register of the NVM configuration register group to generate a DQ signal for multiple cycles on the channel.

[0041] According to one of the fourteenth to sixteenth control components of the first aspect of the present application, a seventeenth control component according to the first aspect of the present application is provided, wherein the data transfer signal generation unit generates a data part of a storage medium access command according to a micro-instruction, and also obtains a data length from a data length configuration register of the NVM configuration register group to generate a DQ signal for a specified number of cycles on the channel.

[0042] According to one of the tenth to seventeenth control components of the first aspect of the present application, an eighteenth control component according to the first aspect of the present application is provided, wherein the media interface controller includes one or more cache units for caching data read from one of the multiple NVM chips or data to be written to one of the multiple NVM chips; the micro-instruction execution unit executes a micro-instruction sequence for a copy operation to provide a read command to the first NVM chip, record the read data in the first cache unit, and provide a programming command to the second NVM chip to write the data in the first cache unit to the second NVM chip.

[0043] According to the eighteenth control component of the first aspect of the present application, a nineteenth control component according to the first aspect of the present application is provided, wherein the media interface controller calls a micro-instruction sequence for a copy operation in response to identifying a media interface command indicating a transfer operation.

[0044] According to the eighteenth or nineteenth control component of the first aspect of the present application, a twentieth control component according to the first aspect of the present application is provided, wherein the first NVM chip serves as a cache for the second NVM chip; the media interface controller further includes a block mapping table, and entries of the block mapping table are associated with recording blocks of the second NVM chip and one or more blocks of the first NVM chip.

[0045] According to the twentieth control component of the first aspect of the present application, a twenty-first control component according to the first aspect of the present application is provided, wherein in response to receiving a first media interface command indicating writing data to a first block of the second NVM chip, the block mapping table is accessed to obtain a second block of the first NVM chip associated with the first block; the writing data indicated by the first media interface command is written to the second block through a micro-instruction sequence for providing a programming command to the first type of NVM chip.

[0046] According to the twenty - first control component of the first aspect of the present application, the twenty - second control component of the first aspect of the present application is provided, wherein in response to receiving a first media interface command indicating writing data to a first block of the second NVM chip, the association between the first block and a second block of the first NVM chip is recorded in the block mapping table.

[0047] According to the twenty - first or twenty - second control component of the first aspect of the present application, the twenty - third control component of the first aspect of the present application is provided, wherein the data writing size indicated by the first media interface command is the physical page size of the first block; when executing a micro - instruction sequence for providing a programming command to the first type of NVM chip, the conversion method between the physical page address of the second NVM chip and the physical page address of the first NVM chip is obtained through an address format configuration register of the NVM configuration register group corresponding to the same - type tag, and the physical page address of the second block is generated.

[0048] According to one of the twenty - first to twenty - third control components of the first aspect of the present application, the twenty - fourth control component of the first aspect of the present application is provided, wherein according to the association relationship between the first block and the second block recorded in the block mapping table, the data of the second block is copied to the first block by executing a micro - instruction sequence for the copy operation; and the association relationship between the first block and the second block is cleared in the block mapping table.

[0049] According to one of the twenty - first to twenty - fourth control components of the first aspect of the present application, the twenty - fifth control component of the first aspect of the present application is provided, wherein in response to receiving a second media interface command indicating writing data to a third block of the second NVM chip, accessing the block mapping table shows that the third block is not recorded in the block mapping table; the writing data indicated by the second media interface command is written to the third block through a micro - instruction sequence for providing a programming command to the second type of NVM chip.

[0050] According to one of the tenth to twenty - fifth control components of the first aspect of the present application, the twenty - sixth control component of the first aspect of the present application is provided, wherein the media interface controller includes a scheduler for scheduling a plurality of threads to be executed by the micro - instruction execution unit, wherein the executed micro - instruction sequence together with its state is called a thread; the first plurality of threads among the plurality of threads correspond one - to - one with the LUNs of the plurality of NVM chips, and each of the first plurality of threads corresponds to a micro - instruction sequence for providing a storage media access command to the NVM chip.

[0051] According to the twenty-sixth control component of the first aspect of the present application, the twenty-seventh control component of the first aspect of the present application is provided, wherein the second thread of the plurality of threads corresponds to the LUN of the first NVM chip and the LUN of the second NVM chip for which data is to be copied, and the second thread corresponds to the micro-instruction sequence applied to the copy operation.

[0052] According to the twenty-sixth control component of the first aspect of the present application, the twenty-eighth control component of the first aspect of the present application is provided, wherein the media interface controller schedules the first thread and the second thread in response to identifying a media interface command indicating a transfer operation, and both the first thread and the second thread are allocated a first cache unit; the first thread reads data from the first NVM chip according to the micro-instruction sequence for providing a read command to the NVM chip and records it in the first cache unit; the second thread writes the data in the first cache unit to the second NVM chip according to the micro-instruction sequence for providing a programming command to the NVM chip.

[0053] According to the twenty-eighth control component of the first aspect of the present application, the twenty-ninth control component of the first aspect of the present application is provided, wherein the second thread yields in response to the data to be written to the second NVM chip not being recorded in the first cache unit; and / or schedules the second thread in response to the data to be written to the second NVM chip being recorded in the first cache unit.

[0054] According to the second aspect of the present application, a storage device according to the second aspect of the present application is provided, including a control component and a plurality of NVM chips; wherein the control component is one of the first to twenty-ninth control components of the first aspect of the present application.

[0055] According to the third aspect of the present application, a first media interface command processing method according to the third aspect of the present application is provided, including: obtaining a media interface command, and identifying the type of the NVM chip to be accessed by the media interface; according to the identified type, obtaining the characteristics of the NVM chip to be accessed; generating a storage media access command for accessing the NVM chip according to the obtained characteristics.

[0056] According to the first media interface command processing method of the third aspect of the present application, a second media interface command processing method according to the third aspect of the present application is provided, wherein in response to the type being the first type, a first micro-instruction sequence corresponding to the first type is executed; the first micro-instruction sequence obtains the characteristics during execution and generates a storage media access command for accessing the NVM chip according to the obtained characteristics.

[0057] According to the first medium interface command processing method of the third aspect of the present application, there is provided a third medium interface command processing method according to the third aspect of the present application, wherein in response to the medium interface command indicating a first operation, a first micro-instruction sequence corresponding to the first operation is executed; the first micro-instruction sequence obtains the feature during execution and generates a storage medium access command for accessing the NVM chip according to the obtained feature.

[0058] According to the second or third medium interface command processing method of the third aspect of the present application, there is provided a fourth medium interface command processing method according to the third aspect of the present application, wherein according to the identified type, a feature of the type of the NVM chip to be accessed is obtained from the NVM configuration register group corresponding to the type; the NVM configuration register group includes a time constraint configuration register, an address format configuration register, a data length configuration register, and / or a command format configuration register for storing the features of the NVM chip.

[0059] According to one of the second to fourth medium interface command processing methods of the third aspect of the present application, there is provided a fifth medium interface command processing method according to the third aspect of the present application, wherein a micro-instruction sequence for processing the medium interface command analyzes the medium interface command and calls the first micro-instruction sequence; the micro-instruction sequence for processing the medium interface command also identifies the type of the NVM chip to be accessed by the medium interface; and the first micro-instruction sequence is executed to obtain a feature of the type of the NVM chip to be accessed from the NVM configuration register group corresponding to the type.

[0060] According to one of the second to fifth medium interface command processing methods of the third aspect of the present application, there is provided a sixth medium interface command processing method according to the third aspect of the present application, wherein the first micro-instruction sequence includes a micro-instruction for generating a command header of the storage medium access command, a micro-instruction for generating an address of the storage medium access command, and / or a micro-instruction for generating data of the storage medium access command.

[0061] According to the sixth medium interface command processing method of the third aspect of the present application, there is provided a seventh medium interface command processing method according to the third aspect of the present application, wherein the micro-instruction for generating the command header of the storage medium access command is executed to generate the command header of the storage medium access command, and time constraint information is also obtained from the time constraint configuration register of the NVM configuration register group to generate a command header ALE signal and / or a CLE signal for the storage medium access command on the channel.

[0062] According to the sixth or seventh media interface command processing method of the third aspect of the present application, an eighth media interface command processing method according to the third aspect of the present application is provided, wherein a micro-instruction for generating an address of a storage medium access command is executed, and an address format is obtained from an address format configuration register of an NVM configuration register group to generate DQ signals for multiple cycles of the address of the storage medium access command on a channel.

[0063] According to one of the sixth to eighth media interface command processing methods of the third aspect of the present application, a ninth media interface command processing method according to the third aspect of the present application is provided, wherein a micro-instruction for generating data of a storage medium access command is executed, and a data length is obtained from a data length configuration register of an NVM configuration register group to generate DQ signals for a specified number of cycles on a channel.

[0064] According to one of the first to ninth media interface command processing methods of the third aspect of the present application, a tenth media interface command processing method according to the third aspect of the present application is provided, wherein in response to obtaining a media interface command indicating data transfer from a first type of NVM chip to a second type of NVM chip, a micro-instruction sequence for a copy operation is executed to provide a read command to the first NVM chip, record the read data in a first buffer unit, and provide a programming command to the second NVM chip to write the data in the first buffer unit to the second NVM chip.

[0065] According to the tenth media interface command processing method of the third aspect of the present application, an eleventh media interface command processing method according to the third aspect of the present application is provided, wherein the first NVM chip serves as a cache for the second NVM chip; and the blocks of the second NVM chip are associated with one or more blocks of the first NVM chip in an entry of a block mapping table.

[0066] According to the eleventh media interface command processing method of the third aspect of the present application, a twelfth media interface command processing method according to the third aspect of the present application is provided, wherein in response to receiving a first media interface command indicating writing data to a first block of the second NVM chip, the block mapping table is accessed to obtain a second block of the first NVM chip associated with the first block; and the writing data indicated by the first media interface command is written to the second block through a micro-instruction sequence for providing a programming command to the first type of NVM chip.

[0067] According to the twelfth media interface command processing method of the third aspect of the present application, a thirteenth media interface command processing method according to the third aspect of the present application is provided, wherein in response to receiving a first media interface command indicating writing data to a first block of the second NVM chip, the association between the first block and a second block of the first NVM chip is recorded in the block mapping table.

[0068] According to the twelfth or thirteenth media interface command processing method of the third aspect of the present application, a fourteenth media interface command processing method according to the third aspect of the present application is provided, wherein the write data size indicated by the first media interface command is the physical page size of the first block; when executing the micro-instruction sequence for providing a programming command to the NVM chips of the first type, the conversion method of the physical page address of the second NVM chip and the physical page address of the first NVM chip is obtained through the address format configuration register of the NVM configuration register group corresponding to the same type of tag, and the physical page address of the second block is generated.

[0069] According to one of the twelfth to fourteenth media interface command processing methods of the third aspect of the present application, a fifteenth media interface command processing method according to the third aspect of the present application is provided, wherein according to the association relationship between the first block and the second block recorded in the block mapping table, the data of the second block is copied to the first block by executing the micro-instruction sequence for the copy operation; and the association relationship between the first block and the second block is cleared in the block mapping table.

[0070] According to one of the twelfth to fifteenth media interface command processing methods of the third aspect of the present application, a sixteenth media interface command processing method according to the third aspect of the present application is provided, wherein in response to receiving a second media interface command indicating writing data to a third block of the second NVM chip, the block mapping table is accessed and it is obtained that the third block is not recorded in the block mapping table; the writing data indicated by the second media interface command is written to the third block through the micro-instruction sequence for providing a programming command to the NVM chips of the second type.

[0071] According to one of the first to sixteenth media interface command processing methods of the third aspect of the present application, a seventeenth media interface command processing method according to the third aspect of the present application is provided, further including: scheduling a plurality of threads, wherein the executed micro-instruction sequence together with its state is called a thread; the first plurality of threads among the plurality of threads correspond one-to-one to the LUNs of the NVM chips, and each of the first plurality of threads corresponds to a micro-instruction sequence for providing a storage medium access command to the NVM chip.

[0072] According to one of the seventeenth media interface command processing methods of the third aspect of the present application, an eighteenth media interface command processing method according to the third aspect of the present application is provided, wherein the second thread of the plurality of threads corresponds to the LUN of the first NVM chip and the LUN of the second NVM chip for which data is to be copied, and the second thread corresponds to a micro-instruction sequence for the copy operation.

[0073] One of the seventeenth media interface command processing methods according to the third aspect of the present application provides the nineteenth media interface command processing method according to the third aspect of the present application, wherein in response to identifying a media interface command indicating a relocation operation, a first thread and a second thread are scheduled, and both the first thread and the second thread are allocated a first cache unit; the first thread reads data from a first NVM chip according to a micro-instruction sequence for providing a read command to the NVM chip and records the data in the first cache unit; the second thread writes the data in the first cache unit to a second NVM chip according to a micro-instruction sequence for providing a programming command to the NVM chip.

[0074] One of the nineteenth media interface command processing methods according to the third aspect of the present application provides the twentieth media interface command processing method according to the third aspect of the present application, wherein in response to the data to be written to the second NVM chip not being recorded in the first cache unit, the second thread yields; and / or in response to the data to be written to the second NVM chip being recorded in the first cache unit, the second thread is scheduled.

[0075] According to a fourth aspect of the present application, there is provided an information processing device according to a fourth aspect of the present application, the information processing device including a processor and a memory, wherein the processor stores a program, and when the program is executed by the processor, it implements one of the first to twentieth media interface command processing methods according to the third aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings.

[0077] Figure 1 A block diagram of a storage device of the prior art is shown;

[0078] Figure 2 A detailed block diagram of a control component of a storage device is shown;

[0079] Figure 3 A media interface controller is shown;

[0080] Figure 4A A hybrid channel media interface controller according to the present application is shown;

[0081] Figure 4B Another hybrid channel media interface controller according to the present application is shown;

[0082] Figure 5 A schematic diagram showing a programming operation implemented by a hybrid channel media interface controller according to the present application is shown;

[0083] Figure 6A Shows a schematic diagram of a micro-instruction according to another embodiment of the present application;

[0084] Figure 6B Shows an NVM configuration register bank according to another embodiment of the present application;

[0085] Figure 7 Shows a block diagram of a micro-instruction execution unit according to another embodiment of the present application;

[0086] Figure 8 Shows a block diagram of a media interface controller according to yet another embodiment of the present application;

[0087] Figure 9A Shows a block diagram of a media interface controller according to still another embodiment of the present application;

[0088] Figure 9B Shows a block diagram of a media interface controller according to still another embodiment of the present application; and

[0089] Figure 10 Shows a block diagram of a media interface controller according to another embodiment of the present application. Detailed implementation

[0090] Next, in combination with the accompanying drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application are clearly and completely described. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0091] Figure 4A Shows a hybrid channel media interface controller according to the present application.

[0092] The signal driver of the media interface controller couples one or more channels ( Figure 4A shown as channel 420 and channel 425 in Figure 4A ). Each channel is respectively coupled to one or more NVM chips. These NVM chips have the same or different types. By way of example,

[0093] Figure 4B Shows another hybrid channel media interface controller according to the present application.

[0094] Same as Figure 4A the hybrid channel media interface controller, Figure 4B the microinstruction memory of the hybrid channel media interface controller stores a plurality of microinstruction sequences, including, for example, a microinstruction sequence for media interface command processing, a microinstruction sequence 410 for issuing a programming command to an NVM chip of type 1, a microinstruction sequence 412 for issuing a programming command to an NVM chip of type 2, a microinstruction sequence 414 for issuing a read command to an NVM chip of type 3, and a microinstruction sequence 416 for issuing an erase command to an NVM chip of type 4. The microinstructions of the microinstruction sequences (410, 412, 414, and 416) each indicate the required parameters to satisfy the type of NVM chip to be operated. Understandably, the microinstruction memory also stores microinstruction sequences for other operations.

[0095] In response to the media interface command provided by the storage command processing unit (also see Figure 2 ), the microinstruction execution unit executes the microinstruction sequence for media interface command processing to identify the type of NVM chip and the type of operation indicated by the media interface command, and calls the corresponding microinstruction sequence to drive the signal driver to generate a storage media access command to the Target of the specified NVM chip. By providing corresponding microinstruction sequences for different types of NVM chips, a storage media access command corresponding to the type of NVM chip is generated on the channel when the microinstruction sequence is executed.

[0096] For example, when the media interface command indicates programming an NVM chip of type 1 on channel 420, the microinstruction sequence 410 for issuing a programming command to an NVM chip of type 1 is called through the microinstruction sequence for executing media interface command processing. Another example is that when the media interface command indicates erasing an NVM chip of type 4 on channel 425, the microinstruction sequence 416 for issuing an erase command to an NVM chip of type 4 is called through the microinstruction sequence for executing media interface command processing.

[0097] As another example, the media interface command indicates a variety of information, including the type of operation (e.g., read, program, erase, etc.), the accessed address (e.g., which NVM chip, which LUN, block number, page number, etc.), and an optional type tag. The type tag indicates, for example, a TLC operation, an MLC operation, or an SLC operation. Optionally or further, the type tag indicates the use of the ONFI protocol or the use of the Toggle protocol. By executing a micro-instruction sequence for media interface command processing, the micro-instruction sequence corresponding to the processing of the media interface command is identified. For example, if the type tag of the media interface command indicates an SLC operation, the micro-instruction sequence 410 is called to generate a storage media access command according to the media interface command; if the type tag of the media interface command indicates a TLC operation, the micro-instruction sequence 412 is called to generate a storage media access command according to the media interface command.

[0098] Figure 5 FIG. shows a schematic diagram of a hybrid channel media interface controller according to the present application implementing a programming operation.

[0099] As an example, the micro-instruction memory stores a micro-instruction sequence 510 for media interface command processing, a micro-instruction sequence 512 for issuing a programming command to an NVM chip of the SLC type, and a micro-instruction sequence 514 for issuing a programming command to an NVM chip of the TLC type.

[0100] In response to the storage command processing unit providing a media interface command to the media interface controller, the micro-instruction sequence 510 for media interface command processing is executed. The micro-instruction sequence 510 obtains the media interface command (520), identifies the NVM chip type and the operation type indicated by the media interface command according to the content of the media interface command, and calls the corresponding micro-instruction sequence (512 or 514) to drive the signal driver to generate a storage media access command for the Target of the specified NVM chip.

[0101] Optionally, when executing the micro-instruction sequence 510, corresponding parameters are also generated and the called micro-instruction sequence is configured according to the NVM chip type and operation type indicated by the media interface command. For example, for the programming command of an SLC type NVM chip, the data volume to be transmitted is 4KB, while for the programming operation of a TLC type NVM chip, the data volume to be transmitted is 16KB, 32KB, or 48KB. The size of the data volume to be transmitted is indicated in the parameters generated when executing the micro-instruction sequence 510. Still by way of example, the programming commands for SLC type NVM chips and TLC type NVM chips have different command formats and / or command encodings, and the command format and / or command encoding to be used is indicated in the parameters generated when executing the micro-instruction sequence 510. As yet another example, the programming commands for SLC type NVM chips and TLC type NVM chips have different timings or constraint conditions, such as their respective signal setup times and / or hold times, and the timing or constraint conditions to be used are indicated in the parameters generated when executing the micro-instruction sequence 510.

[0102] Still optionally, when executing the micro-instruction sequence 510, the physical address for accessing the NVM chip indicated by the media interface command is also checked or adjusted. For example, the programming order of multiple physical pages of a block of an NVM chip is inconsistent with its physical page number (for example, programming cannot be performed in the order of increasing or decreasing physical page numbers, but in a specified order, for example, programming each physical page in the order of physical page numbers 1 - 10 - 11 - 2 - 20). Accordingly, when executing the micro-instruction sequence 510, the physical page numbers to be programmed are generated based on the physical address indicated by the media interface command. As yet another example, different types of NVM chips have different numbers of physical pages within their respective blocks. For the convenience of managing the storage medium, the storage command processing unit manages the storage medium according to virtual NVM, the media interface command indicates the page address of the virtual NVM, and the page of the virtual NVM may be composed of two or more real physical pages, so the conversion between the page address of the virtual NVM and the real physical page number is implemented by the micro-instruction sequence 510.

[0103] By way of example, if it is recognized when executing the micro-instruction sequence 510 that the obtained media interface command indicates a programming operation on an SLC type NVM chip, the micro-instruction sequence 512 is called, and optionally the parameters required for programming the SLC type NVM chip are provided for it. In response, the micro-instruction execution unit (also refer to FIG. 4) executes the micro-instruction sequence 512.

[0104] As an example, for the programming operation of an SLC type NVM chip, the amount of data written is 4KB. When the micro-instruction sequence 512 is executed, 4KB of data to be written (the storage location of this data is provided by the media interface command) is obtained and stored in the programming data cache. Optionally, the micro-instruction sequence 512 only confirms that the 4KB of data to be written is available, without moving it to the cache, to reduce operations.

[0105] Executing the micro-instruction sequence 512 also generates a signal indicating the programming command for the SLC NVM chip, so as to provide the programming command together with the 4KB of data to the SLC NVM chip.

[0106] The signal indicating the programming command for the SLC NVM chip generated by executing the micro-instruction sequence 512 is compatible with the storage protocol supported by this SLC NVM chip and the timing and constraint conditions of the storage protocol.

[0107] Still as an example, if the micro-instruction sequence 510 recognizes that the obtained media interface command indicates a programming operation on a TLC type NVM chip, it calls the micro-instruction sequence 512 and optionally provides the parameters required for programming the TLC type NVM chip. In response, the micro-instruction execution unit (also see Figure 4) executes the micro-instruction sequence 514.

[0108] As an example, for the programming operation of a TLC type NVM chip, the amount of data written is 48KB. When the micro-instruction sequence 514 is executed, 48KB of data to be written (the storage location of this data is provided by the media interface command) is obtained and stored in the programming data cache. Optionally, the unit of data transfer for each time by the micro-instruction sequence 514 (including the micro-instruction sequence 512) is 4KB. Correspondingly, the micro-instruction sequence completes the acquisition of the data to be written to the TLC NVM chip through 16 data transfers. Optionally, the number of data transfers (16 times) is indicated by the parameters of the micro-instruction sequence 510, or the micro-instruction sequence 514 itself records this number.

[0109] Optionally, the micro-instruction sequence 514 only confirms that the 48KB of data to be written is available, without moving it to the cache, to reduce operations.

[0110] Executing the micro-instruction sequence 514 also generates a signal indicating the programming command for the TLC NVM chip, so as to provide the programming command together with the 48KB of data to the TLC NVM chip.

[0111] Figure 6A A schematic diagram of micro-instructions according to another embodiment of the present application is shown.

[0112] Also refer to Figure 3 With reference to Figure 4, the micro-instruction sequence includes multiple micro-instructions, and the media interface controller executes the micro-instructions in the micro-instruction sequence.

[0113] To support multiple types of NVM chips with mixed settings in a single channel, a "type tag" is set in one, multiple, or all microinstructions (601). The type tag indicates the type of NVM chip that the microinstruction operates on.

[0114] Figure 6A A table showing the meaning of the type tags is also provided. For example, a type tag with a value of "0x01" indicates an NVM chip type of low-latency flash memory that follows the Toggle protocol. The low-latency flash memory that follows the Toggle protocol includes various features, such as its storage cells being of the SLC type, the amount of data required for a programming operation on it being 4KB, the time (in microseconds) typically taken to query the completion of programming after issuing a programming command, and its signals following the timing requirements of the Toggle protocol. Another example, a type tag with a value of "0x02" indicates an NVM chip type of TLC flash memory that follows the Toggle protocol. The various features of the TLC flash memory that follows the Toggle protocol include, for example, its storage cells being of the TLC type, the amount of data required for a programming operation on it being 48KB, the time (tens of microseconds) typically taken to query the completion of programming after issuing a programming command, and its signals following the timing requirements of the Toggle protocol. Another example, a type tag with a value of "0x03" indicates an NVM chip type of TLC flash memory that follows the ONFI protocol. The various features of the TLC flash memory that follows the ONFI protocol include, for example, its storage cells being of the TLC type, the amount of data required for a programming operation on it being 16KB or 32KB, the time (tens of microseconds) typically taken to query the completion of programming after issuing a programming command, and its signals following the timing requirements of the ONFI protocol. Another example, a type tag with a value of "0x04" indicates an NVM chip type of TLC flash memory that follows the ONFI protocol but operates in the SLC mode. The various features of the TLC flash memory that follows the ONFI protocol when operating in the SLC mode include, for example, its storage cells being of the SLC type, the amount of data required for a programming operation on it being 16KB, the time (a few microseconds) typically taken to query the completion of programming after issuing a programming command, and its signals following the timing requirements of the ONFI protocol.

[0115] In the Chinese patent with the application number 201510253428.1 and the patent name "Micro-instruction sequence execution method and its device", the Chinese patent application with the application number 201610009789.6 and the patent name "Method and device for checking block page address", and the Chinese patent application with the application number "201610836531.3" and the patent name "Method and device for generating NVM chip interface commands", a variety of micro-instructions are provided, and their full texts are incorporated herein by reference. One or more existing micro-instructions, as well as one or more micro-instructions to be proposed in the future, can be additionally set with a "type tag" according to the embodiments of the present application to indicate the type of NVM chip to be operated on.

[0116] The "type tag" of the micro-instruction indicates the type of NVM chip, and one or more characteristics required for one or more "type tags" also need to be described for the media interface controller. According to the embodiments of the present application, the media interface controller further includes one or more NVM configuration register groups, and each NVM configuration register group includes a plurality of registers for describing the respective characteristics of the corresponding NVM chip.

[0117] Figure 6B Shows an NVM configuration register group according to another embodiment of the present application.

[0118] Figure 6B Among them, by way of example, the "type tag" has 4 values, namely "0x00", "0x01", "0x02" and "0x03" (also see Figure 6A ). Each value of the "type tag" corresponds to one of the one NVM configuration register groups (610, 620, 630 and 640). The respective registers of the NVM configuration register group are used to describe the characteristics of the NVM chip.

[0119] By way of example, each NVM configuration register group includes 4 registers (including a time constraint configuration register, an address format configuration register, a data length configuration register, and a command format configuration register).

[0120] The time constraint configuration register records, for example, the setup time, hold time, etc. of one or more signals required by the Toggle or ONFI protocol. The address format configuration register records, for example, the format of the address in the storage medium access command, such as the number of bus cycles occupied by the address transmission on the DQ signal, the meaning of the address transmitted in each cycle, etc. The data length configuration register records the data length required for the read command / programming command. The command format configuration register records, for example, the command encoding indicating the storage medium access command (for example, "0x80" represents the start of a programming command for a specific NVM chip type, and "0x10" represents the completion of the data transmission of the programming command).

[0121] Thus, a set of NVM configuration registers can be obtained according to the "type tag" field of the micro-instruction, and then a variety of configurable parameters used when generating a storage medium access command can be obtained, and a storage medium access command is generated on the channel according to the indication of the parameters.

[0122] Optionally still, the micro-instruction indicates the "type tag" field. For a specific micro-instruction, one or more configuration registers of the NVM configuration register group corresponding to the "type tag" field are used (without using all the configuration registers). For example, for a micro-instruction sequence (including one or more micro-instructions) for generating an erase command, it does not need to use the data length configuration register in the NVM configuration register group (the erase command does not need to transfer data).

[0123] Figure 7 A block diagram of a micro-instruction execution unit according to another embodiment of the present application is shown.

[0124] The micro-instruction to be executed is provided to the micro-instruction execution unit. The micro-instruction execution unit includes a micro-instruction decoding unit, a multiplexer, a selector, a plurality of NVM configuration register groups, and a plurality of signal generation units (for example, a command signal generation unit, an address signal generation unit, a data transfer signal generation unit).

[0125] The micro-instruction decoding unit provides the type tag field of the micro-instruction to the selector. The selector couples a plurality of NVM configuration register groups, and according to the value of the type tag field, selects one of the NVM configuration register groups and outputs it. For the selected NVM configuration register group, according to the characteristics described by its respective registers, it is coupled to one or more of the signal generation units. For example, time constraint information is used when encoding commands, addresses, and data for generating a storage medium access command, so the time constraint configuration register is coupled to the command signal generation unit, the address signal generation unit, and the data transfer signal generation unit; address format information is only used when generating the address of the storage medium access command, so the address format configuration register is only coupled to the address signal generation unit, and similarly, the data length register is only coupled to the data transfer signal generation unit.

[0126] The micro-instruction decoding unit also couples the command signal generation unit, the address signal generation unit, and the data transfer signal generation unit through a multiplexer. The signal generation units corresponding to micro-instruction operations with different meanings operate the signal driver to generate signals of a storage medium access command provided to the NVM chip on the channel.

[0127] For example, a micro-instruction is used to generate the command header of a storage medium access command (taking a programming command as an example, the part representing "0x80h"). Such a micro-instruction describes the values of signals such as ALE, CLE, and DQ (for example, ALE is 0, CLE is 1, and DQ is "0x80h"). The micro-instruction decoding unit provides such a micro-instruction to the command signal generation unit through a multiplexer. The command signal generation unit also receives the time constraint information provided by the time constraint configuration register from the selector. According to the time constraint information, the command signal generation unit operates the signal driver to set signals such as ALE, CLE, and DQ to the specified level states at the moments that meet the time constraints on the channel.

[0128] For another example, a micro-instruction is used to generate the address part of a storage medium access command (taking a programming command as an example, representing the physical address to be accessed). Such a micro-instruction describes, for example, the values of multiple cycles transmitted on the DQ signal, or describes a reference that indicates the storage location storing the values of multiple cycles transmitted on the DQ signal. The address also requires a format, such as the number of cycles for DQ signal transmission, which part of the address the value to be transmitted in each cycle corresponds to, etc. The micro-instruction decoding unit provides such a micro-instruction to the address signal generation unit through a multiplexer. The address signal generation unit also receives the address format provided by the address format configuration register from the selector. According to the address format, the address signal generation unit operates the signal driver to set signals such as DQ to the specified values on the channel. The address signal generation unit also receives the time constraint information provided by the time constraint configuration register and sets signals such as DQ to the specified level states at the moments that meet the time constraints. Optionally, according to the address format provided by the address format configuration register, the address indicated by the micro-instruction is also transformed. For example, the programming sequence number indicated by the medium interface command is transformed into a physical page number.

[0129] For another example, a micro-instruction is used to generate the data part of a storage medium access command (taking a programming command as an example, representing the data to be written into the NVM chip). Such a micro-instruction describes, for example, the values in multiple cycles transmitted on the DQ signal, or describes a reference that indicates the storage location in the cache where the values in multiple cycles of DQ signal transmission are stored. Transmitting data also requires the data length. For example, the SLC type of NVM chip corresponds to a programming data length of 4KB, while the TLC type of NVM chip corresponds to a programming data length of 48KB. The micro-instruction decoding unit provides such a micro-instruction to the data signal generation unit through a multiplexer. The data signal generation unit also receives the data length provided by the data length configuration register from the selector. According to the data length and the data to be transmitted, the data transmission signal generation unit operates the signal driver to set signals such as DQ to specified values on the channel and generate a specified number of DQ signals (for example, for transmitting 4096 bytes of data, 2048 or 4096 DQ signal transmission cycles are required). The address signal generation unit also receives the time constraint information provided by the time constraint configuration register and sets signals such as DQ to the specified level state at the moment when the time constraint is satisfied.

[0130] Optionally, the micro-instruction execution unit also executes other micro-instructions. Some micro-instructions are used to determine the position of the subsequent micro-instructions to be executed (referred to as control micro-instructions), and some micro-instructions are used to transfer data between the memory and the cache, and these micro-instructions do not operate the signal driver. Optionally, the control micro-instruction determines the number of DQ signal transmission cycles required for transmitting data to the NVM chip, and obtains the required number of DQ signal transmission cycles from the data length configuration register according to the type tag field of the control micro-instruction.

[0131] In an alternative embodiment, microinstructions for setting a type tag are provided instead of providing a type tag field in each microinstruction. The execution of the microinstruction for setting the type tag sets the microinstruction execution unit to use a specified NVM configuration register set, and this setting remains valid until it is changed next time. Thus, with the same microinstruction sequence, storage medium access commands for different types of NVM chips, for example, are processed, thereby reducing the number of microinstruction sequences that need to be stored. For example, TLC type NVM chips and SLC type NVM chips are coupled on the same channel. A programming operation needs to be performed on the SLC chip first and then on the TLC chip. And a microinstruction sequence for performing the programming operation is stored in the media interface controller. By using the microinstruction for setting the type tag, the NVM configuration register set corresponding to the SLC type is selected first. Thus, in the subsequent execution of the microinstruction sequence for performing the programming operation, the signal generation unit generates signals on the channel according to the NVM configuration register set corresponding to the SLC type. Next, by using the microinstruction for setting the type tag, the NVM configuration register set corresponding to the TLC type is selected. Thus, in the subsequent execution of the microinstruction sequence for performing the programming operation, the signal generation unit generates signals on the channel according to the NVM configuration register set corresponding to the TLC type.

[0132] Figure 8 FIG. 4 shows a block diagram of a media interface controller according to another embodiment of the present application.

[0133] When different types of NVM chips are mixed on a channel, an application scenario occurs where a high-speed low-storage-density NVM chip acts as a cache for a high-density NVM chip. In such an application scenario, there is a need to copy data within the channel from one NVM chip to another NVM chip, or from a high-speed low-density storage unit (e.g., an SLC page) to a high-density storage unit (e.g., a TLC page). Generally, the storage command processing unit of the control component issues a media interface command to the media interface controller to read data from the SLC page and temporarily store it in the storage unit of the control component; next, the storage command processing unit issues another media interface command to write the temporarily stored data to the TLC page. However, such an operation requires moving the data to be copied out of the media interface controller to the outside of the media interface controller. A longer data movement distance means higher power consumption and more time consumption.

[0134] According to Figure 8 the embodiment shown, data copying between different physical pages within the channel is completed inside the media interface controller.

[0135] Compared with the media interface controller shown in FIG. 4 Figure 8The media interface controller therein also shows multiple cache units (810 and 812). The cache units (810 and 812) are architecturally visible operating objects that the microinstructions of the media interface controller can describe as the source address or destination address for data transfer. The size of the cache units is suitable for accommodating the data corresponding to the read commands or programming commands of the NVM chips.

[0136] Channel 820 couples SLCNVM chip 840 and TLC NVM chip 842, and channel 825 couples SLCNVM chip 844 and TLC NVM chip 846.

[0137] To transfer the data of SLCNVM chip 840 to TLC NVM chip 842, according to Figure 8 the embodiment, the media interface controller issues a read command to SLCNVM chip 840, and the destination address of the read data is cache unit 810. Next, the media interface controller issues a programming command to TLC NVM chip 842, and the source address of the data to be written is cache 810 (the data to be transferred read from SLCNVM chip 840 before). Thus, the data transferred within the channel only moves within the media interface controller and is not transmitted outside the media interface controller. And the transfer operation is completed by combining and using the existing microinstruction sequences for reading data from the SLCNVM chip and programming data to the TLC NVM chip, without the need to provide a new microinstruction sequence.

[0138] Optionally, the page size of the SLCNVM chip (e.g., 4KB) is different from that of the TLC NVM chip (e.g., 16KB). To transfer data, the data is read from multiple pages (e.g., 4 pages) of the SLCNVM chip through multiple read commands and recorded in the cache unit, and then the data is programmed to the TLC NVM chip through a single programming command.

[0139] The cache units (810 and 812) are also used to process the normal operations of programming data to the NVM chips and reading data from the NVM chips. To program data, a microinstruction sequence is executed to first transfer the data to be programmed from outside the media interface controller to the cache unit, and then the data in the cache unit is transferred to the NVM chip through the operation signal driver. To read data, a microinstruction sequence is executed to first transfer the data read from the NVM chip to the cache unit, and then to outside the media interface controller.

[0140] Optionally, the cache units are associated with the channels. For example, cache unit 810 is dedicated to channel 820, and cache unit 812 is dedicated to channel 825. Thus, to copy the data of SLCNVM chip 844 to TLC NVM chip 846, cache unit 812 associated with channel 825 is used to temporarily store the data to be copied.

[0141] Still optionally, the cache units are allocated among the channels. Thus, copying data between NVM chips located in different channels can also be performed through the cache units of the media interface controller.

[0142] Still optionally, the media interface commands provided to the media interface controller indicate a copy operation, and the copy operation indicates the physical addresses of the NVM chips to be read and the NVM chips to be programmed. The microinstruction sequence for media interface command processing (also see Figure 4) identifies the media interface command indicating the copy operation, and successively invokes the microinstruction sequence for issuing a read command to the NVM chip and the microinstruction sequence for issuing a write command to the NVM chip. The data to be copied is transferred through the same cache unit in the front and back microinstruction sequences.

[0143] Figure 9A A block diagram of a media interface controller according to yet another embodiment of the present application is shown.

[0144] Figure 9A In the example, within the same channel, the SLC NVM chips are used as the write cache for the MLC NVM chips, and only the TLC NVM chips are used to provide the physical address space of the storage device. By way of example, the SLC NVM chips 940 and 944 have a capacity of 16 GB, and the MLC NVM chips 942 and 946 have a capacity of 128 GB. Although the channels 940 and 945 are coupled with NVM chips having a total capacity of 288 GB, the size of the physical address space used by the storage media management unit (also see Figure 2 ) is 256 GB (provided by the MLC NVM chips 942 and 946), so that the storage media management unit does not need to care about the internal structure of the SLC NVM chips and the allocation of their storage resources.

[0145] According to Figure 9A the embodiment, the media interface commands provided by the storage command processing unit to the media interface controller indicate the data attributes to be written, and the media interface controller determines whether to write the data indicated by the media interface to the SLC NVM chips or the MLC NVM chips according to the data attributes and the available space of the SLC NVM chips.

[0146] As an example, the media interface command indicates a programming operation and the data to be written is hot data (data that needs to be updated frequently) or data that requires low processing latency. The media interface command also indicates that the physical address to be written is physical block 2 of MLCNVM chip 942 (also denoted as M2, where M indicates the MLCNVM chip). The microinstruction sequence for media interface command processing (also see Figure 4) allocates an available physical block (e.g., physical block 0, also denoted as S0, where S indicates the SLCNVM chip) from the SLCNVM chip 940 for this media interface command, and invokes the microinstruction sequence that issues a programming command to the SLCNVM chip to write the data to physical block S0. Optionally, the microinstruction sequence also makes changes such as the physical page address through the corresponding type of NVM configuration register set to issue a programming command to the SLCNVM chip 940.

[0147] In response to allocating an available physical block S0 from the SLCNVM chip 940 for physical block M2, the microinstruction sequence for media interface command processing also records the association relationship between physical block T2 and physical block S0 in the block mapping table. According to Figure 9A the embodiment of, the media interface controller provides a block mapping table for each channel, and the entries therein record the physical blocks of the MLCNVM chip and the physical blocks of the SLCNVM chip that serve as its cache in an associated manner. It can be understood that the physical blocks of each MLCNVM chip may correspond to the physical blocks of multiple SLCNVM chips; and the address format configuration register of the NVM configuration register set records the mapping method from the physical page of the MLCNVM chip to the physical page of the SLCNVM chip.

[0148] Figure 9A In the example of, the entries of the block mapping table provide mapping at the physical block level. The number of physical blocks in the NVM chip is relatively small (compared with the number of physical pages), so the overall size of the block mapping table will not be very large and can be accommodated by the media interface controller. While the storage media management unit (also see Figure 2 ) maintains the mapping at the page level. For example, it records the corresponding physical address for each 4KB-sized section of the logical address space. For large-capacity storage devices, the mapping at the page level requires a large amount of memory space.

[0149] Returning to see Figure 9A , in response to receiving another media interface command (denoted as MI-1), which indicates writing data to physical block 2 (M2) of MLCNVM chip 942. Whether or not this media interface command indicates hot data or data that requires low processing latency, the microinstruction sequence for media interface command processing (also see Figure 4) identifies through the block mapping table that physical block M2 is mapped to physical block 0 (S0) of the SLCNVM chip 940, and it invokes the microinstruction sequence that issues a programming command to the SLCNVM chip to write the data to physical block S0.

[0150] Optionally or further, in response to receiving another media interface command (denoted as MI-2), which indicates reading data from physical block 2 (M2) of the MLCNVM chip 942. The microinstruction sequence for media interface command processing (also see FIG. 4) identifies through the block mapping table that physical block M2 is mapped to physical block 0 (S0) of the SLCNVM chip 940, and it invokes the microinstruction sequence for issuing a read command to the SLCNVM chip to read data from physical block S0 in response to the media interface command (MI-2). It can be understood that during the execution of the microinstruction sequence for issuing a read command to the SLCNVM chip, the physical address indicated by the media interface command (MI-2) is transformed into the physical address for the SLCNVM chip through the NVM configuration register set.

[0151] Further, the storage media management unit (also see Figure 2 ) in response to the processing of the media interface command (being MI-1), records in the page-level mapping table that the physical address used is still the address of physical block 2 of the MLCNVM chip 942, rather than the address of the SLCNVM chip 940. According to Figure 9A 's embodiment, the SLCNVM chips of each channel serve as caches for the MLCNVM chips of the same channel. The storage media management unit only uses the physical addresses of the MLCNVM chips in the page-level mapping table and does not use the physical addresses of the SLCNVM chips. It can be considered that the SLCNVM chips are invisible to the storage media management unit.

[0152] Still optionally, due to the inconsistent block sizes, block 0 and block 1 of the SLCNVM chip 940 (denoted as S0 and S1) are jointly mapped to block 2 (M2) of the MLCNVM chip 942, where the combined capacity of blocks S0 and S1 is not less than the capacity of block M2. In response to blocks S0 and S1 being filled, the media interface controller also copies the data of blocks S0 and S1 to block M2, for example, by combining Figure 8The embodiment shows a way to copy data. For example, the micro-instruction memory of the media interface controller also stores a micro-instruction sequence for managing the cache. In response to multiple physical blocks of the SLCNVM chip mapped to the physical blocks of the MLCNVM chip being filled, in response to the SLCNVM chip being filled (no available physical blocks and all used physical blocks are filled), periodically, or when channel 940 is idle, execute the micro-instruction sequence for managing the cache or call the micro-instruction sequence for the copy operation to implement the copy from the SLC NVM chip 940 to the MLCNVM chip 942. After the copy is completed, erase one or more physical blocks of the SLCNVM chip that have been copied, and also update the block mapping table to delete the physical blocks of the SLCNVM chip that have been copied from the block mapping table. Since it is deleted from the block mapping table, next, if a media interface command indicating a read operation is received, after the micro-instruction sequence for media interface command processing queries the block mapping table, it will identify that the data to be read is recorded in the MLCNVM chip rather than the SLCNVM chip, and thus call the micro-instruction sequence for issuing a read command to the MLCNVM chip. And optionally, the micro-instruction sequence for media interface command processing also sets the type flag field of the called micro-instruction sequence to indicate the type of NVM chip to be accessed.

[0153] Figure 9B Shows a block diagram of a media interface controller according to yet another embodiment of the present application.

[0154] Figure 9B In the example, the storage media management unit knows the internal structure of the SLCNVM chip and the allocation of its storage resources. Thus, the physical addresses of the SLCNVM chip will exist in the page-level mapping table maintained by the storage media management unit. Optionally, the page-level mapping table also marks the type or characteristics of the NVM chip for each physical address (for example, this physical address is provided by the MLCNVM chip or by the SLCNVM chip). See Figure 9B , which shows the physical address space managed by the storage media management unit. The physical address space ranges from physical address P0 to physical address Pn. Physical addresses P0 - Pm are provided by the SLCNVM chip, while physical addresses Pm + 1 to Pn are provided by the MLCNVM chip. Figure 9B In it, the second column of the physical address space table indicates which physical block provides the physical address of that row.

[0155] Subsequently, the media interface command provided by the storage command processing unit to the media interface controller indicates a physical address. The micro-instruction sequence for media interface command processing (also refer to FIG. 4) invokes the corresponding micro-instruction sequence to issue a storage media access command to the NVM chip according to the physical address indicated by the media interface command. There is no need for the media interface controller to maintain the mapping between the physical blocks of the SLC NVM chip and the MLC NVM chip.

[0156] Figure 10 FIG. shows a block diagram of a media interface controller according to another embodiment of the present application.

[0157] The media interface controller includes a micro-instruction memory, a micro-instruction execution unit, a signal driver, a scheduler, and a status register. The micro-instruction sequence to be executed by the micro-instruction execution unit together with its status data is called a thread. The scheduler is coupled to the status register, the micro-instruction memory, and the micro-instruction execution unit, and the micro-instruction execution unit is coupled to the signal driver. In this embodiment, the threads correspond one-to-one with the LUNs such as NVM chips. Each thread is used to process the storage media access command for accessing one LUN. For the media interface command indicating a copy operation, it accesses two different LUNs, and the NVM chips to which these two LUNs belong may have different types. According to an embodiment of the present application, the media interface command indicating a copy operation is processed by a single thread. The status register stores the status data of one or more threads. The thread also has a cache unit.

[0158] The running thread has the control right of the media interface controller. The thread makes itself yield by executing a yield micro-instruction. When the thread yields, its status data is recorded in the status register. And in response, as Figure 10 shown, the scheduler selects one of the threads from one or more threads for execution by the micro-instruction execution unit (this process is called scheduling, or scheduling a thread). The scheduled thread obtains its status data from the status register. For example, according to the media interface command for accessing a certain LUN to be processed, the scheduler schedules the thread corresponding to that LUN, so that the thread processes the media interface command during execution. Still by way of example, when thread A yields, it is processing media interface command C but has not completed the processing. When the scheduler schedules thread A again, based on the obtained status information, thread A can continue to process media interface command C from the position where it yielded.

[0159] Refer to Figure 10, the media interface controller includes channels (1020 and 1025). Channel 1020 couples the SLCNVM chip 1040 and the TLCNVM chip 1042. The SLCNVM chip 1040 includes two LUNs (denoted as LUN (B) and LUN (C) respectively). The TLCNVM chip 1042 includes two LUNs (denoted as LUN (A) and LUN (C) respectively). By way of example, 3 threads (denoted as thread A, thread B, and thread C respectively) are running in the media interface controller, each using a cache unit (denoted as cache unit A, cache unit B, and cache unit C respectively). Thread A is accessing LUN (A), thread B is accessing LUN (B), and thread C is copying data from LUN (C) of the SLCNVM chip 1040 to LUN (C) of the TLCNVM chip 1042.

[0160] Execute the microinstruction sequence of thread C. Send a read command to LUN (C) of the SLCNVM chip 1040 through the signal driver, move the read data to cache unit C, and then send a programming command to LUN (C) of the TLCNVM chip 1042 through the signal driver to write the data in cache unit C to LUN (C) of the TLCNVM chip 1042. During this process, thread C can yield. By using a single thread to access two LUNs for processing the copy command, when thread C yields, its cache unit C still belongs to thread C and will not be used by other threads, ensuring that the copied data will not be damaged.

[0161] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present application. Obviously, those skilled in the art can make various changes and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A control component, characterized in that, it includes a media interface controller for coupling multiple NVM chips; the media interface controller couples the multiple NVM chips through multiple channels; the first channel among the multiple channels couples multiple NVM chips; the first NVM chip of the multiple NVM chips has a first type, and the second NVM chip of the multiple NVM chips has a second type; wherein, the first type is different from the second type; the media interface controller includes a micro-instruction storage unit, a micro-instruction execution unit and a signal driver; the micro-instruction execution unit executes a micro-instruction sequence to operate the signal driver to provide signals to the multiple channels; the media interface controller further includes one or more cache units for caching data read from one of the multiple NVM chips or data to be written to one of the multiple NVM chips; the micro-instruction execution unit executes a micro-instruction sequence for a copy operation to provide a read command to the first NVM chip, record the read data in the first cache unit, and provide a programming command to the second NVM chip to write the data in the first cache unit to the second NVM chip.

2. The control component according to claim 1, characterized in that, the micro-instruction memory stores multiple micro-instruction sequences; the multiple micro-instruction sequences include a micro-instruction sequence for processing media interface commands and multiple micro-instruction sequences for providing storage media access commands to NVM chips; executing the micro-instruction sequence for processing media interface commands calls the micro-instruction sequence for providing storage media access commands to NVM chips corresponding to the media interface commands.

3. The control component according to claim 1 or 2, characterized in that, the micro-instruction execution unit further includes multiple NVM configuration register groups, and each NVM configuration register group includes multiple registers storing the characteristics of NVM chips; executing the micro-instruction sequence for processing media interface commands also sets a type flag; the micro-instruction execution unit accesses one of the multiple NVM configuration register groups according to the type flag and operates the signal driver to provide signals to the multiple channels using the characteristics of the NVM chips obtained by accessing one of the multiple NVM configuration register groups.

4. The control component according to claim 3, characterized in that, the micro-instruction execution unit further includes a micro-instruction decoder and multiple signal generation units; the micro-instruction decoder provides the micro-instruction to one of the multiple signal generation units according to the meaning of the micro-instruction; the micro-instruction decoder also selects multiple registers of one of the multiple NVM configuration register groups according to the type flag and provides them to one or more of the multiple signal generation units; the signal generation unit operates the signal driver to provide signals to one of the multiple channels according to the micro-instruction provided by the micro-instruction decoder and the characteristics obtained from one of the multiple NVM configuration register groups.

5. The control component according to claim 4, characterized in that, The multiple signal generation units include a command signal generation unit, an address signal generation unit, and / or a data transfer signal generation unit; The command signal generation unit generates a command header of a storage medium access command according to a micro-instruction, and also obtains time constraint information from a time constraint configuration register of the NVM configuration register group to generate an ALE signal and / or a CLE signal on the channel.

6. The control component according to claim 1, wherein, the first NVM chip serves as a cache for the second NVM chip; the media interface controller further includes a block mapping table, and entries of the block mapping table are associated with recording blocks of the second NVM chip and one or more blocks of the first NVM chip; in response to receiving a first media interface command indicating writing data to a first block of the second NVM chip, accessing the block mapping table to obtain a second block of the first NVM chip associated with the first block; writing the writing data indicated by the first media interface command to the second block through a micro-instruction sequence for providing a programming command to the first type of NVM chip.

7. The control component according to claim 6, wherein, the size of the writing data indicated by the first media interface command is the physical page size of the first block; when executing a micro-instruction sequence for providing a programming command to the first type of NVM chip, obtaining a conversion method between the physical page address of the second NVM chip and the physical page address of the first NVM chip through an address format configuration register of the NVM configuration register group corresponding to the same type of tag, and generating the physical page address of the second block.

8. The control component according to any one of claims 1-7, wherein, the media interface controller includes a scheduler for scheduling a plurality of threads to be executed by the micro-instruction execution unit, wherein an executed micro-instruction sequence together with its state is called a thread; a first plurality of threads among the plurality of threads correspond one-to-one to the LUNs of the plurality of NVM chips, and each of the first plurality of threads corresponds to a micro-instruction sequence for providing a storage medium access command to an NVM chip; a second thread of the plurality of threads corresponds to the LUN of the first NVM chip and the LUN of the second NVM chip for which data is to be copied, and the second thread corresponds to a micro-instruction sequence for a copy operation.

9. A storage device, comprising a control component and a plurality of NVM chips; wherein, the control component is the control component according to any one of claims 1-8.

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