Reusable core particle interposer for industrial control field

Abstract

The invention discloses a reusable core particle interposer for the industrial control field, which is characterized in that the surface of the interposer is arranged in an asymmetrical interconnection mode and is divided into a plurality of slot areas, each slot area is allocated with a slot type, each slot area is uniformly provided with a plurality of functional areas, and each functional area can be allocated with a functional type; and an eFPGA and an interconnection channel are embedded in the interposer, the eFPGA is coupled with the interconnection channel, and the interconnection channel is arranged among a plurality of slot areas in a hierarchical interconnection mode. According to the invention, the differentiated communication requirement of the industrial control system of the master-slave architecture is met by adopting the non-peer interconnection architecture, the fragmentation customization requirement of the specific application is met by embedding the eFPGA, and the interconnection requirements of different levels with respective characteristics are met by hierarchical interconnection; and a uniform slot with a downward compatibility characteristic is designed, so that the flexibility during core particle integration is improved, and the application performance requirement and the scene adaptation requirement in the industrial control field can be met at the same time.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing and packaging technology, and relates to a reusable chip interposer for industrial control applications. Background Technology

[0002] With the continuous development of the economy and society, the demand for high-end dedicated chips in the industrial control field is constantly increasing. In terms of industrial control chip design, the fragmented nature and multi-IP (Intellectual Property) integration characteristics present certain challenges. Chip-based design methods allow designers to pre-design and manufacture chips and assemble them on demand during application. They feature heterogeneous integration, reduced NRE (Network Execution Environment) costs, and agile development, effectively addressing the pain points of industrial control chip design. However, for the integration requirements of different chip combinations, although chips are reusable, custom interposers are often needed to adapt to the interconnection requirements of different scenarios. The development of custom interposers further increases the RE / NRE costs and extends the design time. In applications such as HPC, there are fewer product types, higher production volumes per unit, and lower sensitivity to cost. Higher production volumes per unit can, to some extent, reduce the RE / NRE cost of customized interposers. Therefore, customized interposers are currently widely used to implement chip systems.

[0003] For the industrial control / embedded systems field, there are many product types, and the industry is highly sensitive to cost and development cycle. Customized intermediary layers cannot be reused across product categories, which increases recurring engineering (RE) and non-recurring engineering (NRE) costs and design time, hindering the modular application of industrial control products.

[0004] For the reasons mentioned above, research on the reusability of intermediary layers is gradually gaining attention. Reusable intermediary layers offer high flexibility, serving as a universal foundation for chip integration, providing interconnectivity for chips, amortizing RE / NRE costs to a greater extent, and supporting agile development.

[0005] For reusable middleware layers, the main challenge lies in the design of the interconnect architecture, which needs to simultaneously meet application performance requirements and scenario adaptability. 1. The application performance meets and guarantees the availability of the chip system supported by the reusable intermediary layer in the target application field.

[0006] 2. Scene adaptability gives the reusable middleware layer greater reusability.

[0007] Achieving higher performance often means a decrease in scene adaptability, and vice versa.

[0008] Currently, reusable intermediary layer technologies include: (1) Reusable intermediary layer technology for embedded systems: It allows the intermediary layer to be reused across application domains, but it only realizes the connection of pins between chips. The architecture design cannot realize efficient system deconstruction and is mainly aimed at board-level applications. In fields such as industrial control, where signal chain performance is particularly important, it cannot meet the requirements.

[0009] zGlue technology targets the embedded field, based on a Crossbar structure, providing bump-to-bump (B2B) interconnects for the core. In the idle areas of the interposer layer, this design adds power management, self-test, and other functions. However, the Crossbar architecture suffers from low interconnect efficiency, complex architecture design, and a large number of configuration bits due to its high hardware complexity of O(N^2). Regarding ubumps, its oversaturated implementation means that multiple ubumps on the interposer layer correspond to only one actual ubump on the core, resulting in low actual ubump density and fewer usable ubumps, making it unsuitable for supporting high-performance, complex applications.

[0010] EMAB / S-EMAB are designed for embedded systems, based on a crossbar architecture, providing bump-to-bump (B2B) interconnects for core components. S-EMAB offers two types of crossbar networks: a checkerboard pattern supporting 100Mbps and a high-speed network supporting 1Gbps. This design can adapt to the characteristics of industrial control applications to some extent, but it cannot support hierarchical interconnection requirements with different communication ranges and characteristics. Regarding bump functionality, its unrestricted implementation requires complex power supply and signal switching circuitry, making it unsuitable for high-performance, complex applications.

[0011] (2) Reusable intermediate layer technology for high-performance computing (HPC): While pursuing high performance and high bandwidth in design, it faces significant challenges in application adaptability. In fields such as industrial control, where scenario adaptability is particularly important, existing intermediate layers have certain shortcomings and cannot meet the requirements.

[0012] SISL and GIA technologies, along with ZeroASIC's eFabric product targeting the HPC field, are based on a NoP (Network on Package) architecture, providing packet-level switching interconnects for the core components. This design employs a peer-to-peer interconnect architecture, providing the same interconnect resources / slots for all core components, such as... Figure 1As shown, this solution is suitable for the peer-to-peer interconnection requirements in the HPC field with many-core architectures. In such application scenarios, individual cores are relatively large in scale and have relatively fixed functions (such as CPU, NPU, MEM, etc.). In the industrial control field, there are a large number of relatively small functional IPs, which are more in line with the master-slave architecture communication paradigm.

[0013] Routerless intermediary layer (RFIA) technology is geared towards the HPC field. Based on a multi-layer switch local interconnect architecture, this design divides the intermediary layer into multiple basic units, with adjacent basic units providing the same interconnect channels. Similar to the aforementioned designs, this design adopts a peer-to-peer interconnect architecture, providing the same interconnect resources / slots for all core components, and cannot support the differentiated interconnections of industrial control core systems.

[0014] (3) Domain-specific reusable intermediary layer technology: By restricting reusability to a specific domain, it achieves high application adaptability, but its application is limited to a specific domain and may not be able to amortize RE / NRE costs.

[0015] This domain-specific chip platform technology for IRS (intelligent radar / sonar) is based on a NoP architecture. Compared to the reusable intermediary layers of general-purpose chips such as SISL, GIA, and ZeroASIC, which are also based on NoP architecture, this design is specifically designed for the characteristics of radar / sonar system applications, namely unidirectional streaming data transmission, and features a unidirectional ring topology. This architecture can fully meet the application characteristics of the target domain, namely intelligent radar / sonar, and can be reused within this domain. Furthermore, SRAM is added to the idle area of ​​the intermediary layer for chip system use. However, due to its high adaptability to the target domain, its flexibility is relatively low, making it difficult to reuse in a wider range of domains to amortize NRE / RE costs. In addition, it only provides additional communication capabilities for configuration / management to the CPU, providing the same interconnect resources / slots to non-CPU chips, and cannot support the differentiated interconnects of industrial control chip systems.

[0016] In summary, the existing solutions are compared as shown in the table below: . Summary of the Invention

[0017] To address the aforementioned technical problems in the existing technology, this invention proposes a reusable core interposer layer for the industrial control field, the specific technical solution of which is as follows: A reusable core interposer layer for industrial control is provided. The surface of the interposer layer is configured with non-peer interconnection to divide it into multiple slot regions. Each slot region is assigned a slot type, and multiple functional areas are uniformly arranged in each slot region. Each functional area can be assigned a functional type. An eFPGA and interconnect channels are embedded within the intermediary layer. The eFPGA is coupled to the interconnect channels, which are arranged in a hierarchical interconnection manner among multiple slot regions.

[0018] Furthermore, the slot types include computing, control, analog, and storage types, and each type of slot area is used to place the corresponding type of chip.

[0019] Furthermore, a single core can be placed in one or more slot areas, and all or some of the functional areas therein can be used as needed.

[0020] Furthermore, the arrangement of the functional areas has rotational symmetry.

[0021] Furthermore, within each slot area, the same / similar function types are assigned to function patches located in the same position.

[0022] Furthermore, the functional types include data types, event types, state types, and simulation types.

[0023] Furthermore, the eFPGA is located in the free area outside the slot area and the interconnect channel.

[0024] Furthermore, the input / output ports of the eFPGA communicate with the chips placed in the slot area via interconnect channels.

[0025] Furthermore, the hierarchical interconnection method involves dividing the interconnection channels according to their different functional types, including: High-speed parallel interconnect channels are responsible for data interconnection between short-distance cores; A universal interconnect channel is responsible for signal transmission between chips over long distances; The low-speed interconnect channel is responsible for signal interconnection between global chips.

[0026] Beneficial effects: In view of the contradiction between the characteristics of chip architecture in the industrial control field and the existing general / domain-specific intermediary layer architecture, this invention adopts a non-peer interconnection architecture to solve the differentiated communication needs of master-slave industrial control systems.

[0027] The fragmented customization requirements of specific applications are addressed by embedding eFPGAs in the idle portions of a reusable intermediary layer.

[0028] The interconnection needs of different levels with their own characteristics are addressed by providing interconnection channels with different features.

[0029] The design of a unified slot with backward compatibility improves the flexibility of core integration.

[0030] The above design can simultaneously meet the application performance requirements and scenario adaptation requirements in the industrial control field. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the interconnection methods of existing peer-to-peer interconnection solutions such as GIA / FPIA; Figure 2 This is a schematic diagram of the non-peer interconnection in this embodiment, illustrating the non-peer interconnection architecture proposed in this invention that adapts to the differentiated communication needs of industrial control systems; Figure 3 This is a schematic diagram of the unified slot design in this embodiment, illustrating the slot design proposed in this invention that adapts to non-peer interconnects and has backward compatibility. Figure 4 This is a schematic diagram of the embedded eFPGA in this embodiment, illustrating the solution proposed in this invention to increase the adaptability of industrial control scenarios by embedding an eFPGA in the idle part of the intermediary layer. Figure 5 This is a schematic diagram of the hierarchical interconnection in this embodiment, illustrating the hierarchical interconnection architecture proposed in this invention that adapts to the interconnection requirements of each level. Figure 6 It corresponds Figure 2 A specific instance of a non-peer interconnection; Figure 7 It corresponds Figure 5 A diagram of a hierarchical interconnection; Figure 8 It corresponds Figure 6 A diagram illustrating a specific example of functional area division in a document; Figure 9 It corresponds Figure 3 The diagram shows an instance of a specific function type assigned to a functional area. Detailed Implementation

[0032] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0033] This embodiment provides a reusable core interposer layer for industrial control applications, as detailed below: For the differentiated communication requirements of master-slave architecture industrial control systems, this embodiment adopts a non-peer-to-peer interconnection method to meet the interconnection needs of different functional types of core components. For the reusable intermediary layer design, its surface is divided into multiple slot areas, and the size / proportion of each slot area is unlimited. Depending on the application scenario requirements of the reusable intermediary layer, the sizes of different types of slots can be the same or different.

[0034] For a given reusable intermediary layer, each slot region is assigned a slot type. In terms of the interconnect architecture, resources are provided to each slot region to suit its slot type. Depending on the interconnect type and scale requirements of the actual reusable intermediary layer's target domain, the assigned slot types can be repeated or different, with no restrictions on the number / proportion / type. Figure 2 As shown.

[0035] like Figure 6 As shown, in one specific embodiment, the reusable interposer surface is divided into six slot regions. Two slots are assigned to computing-type cores, three slots are assigned to general-purpose cores, such as control and storage cores, and one slot is assigned to an analog core.

[0036] The aforementioned non-peer-to-peer interconnect design provides differentiated communication capabilities for the chip, aligning with its master-slave architecture. It supports the needs of subsystematized, fragmented, and heterogeneously integrated chip-level control chips. Compared to peer-to-peer interconnect solutions such as GIA / FPIA, this solution provides appropriate communication resources for the corresponding chip type, avoiding the waste caused by excessive resource usage in saturated interconnect solutions while ensuring that the corresponding chip receives the necessary communication resources. Compared to the limited non-peer-to-peer interconnect solutions of IRS and DSA, the differentiated communication capabilities of this solution are not limited to additional channels in the CPU chip being used only for system configuration / management; they can provide corresponding differentiated communication capabilities for the entire chip system. Compared to fully free interconnect solutions such as zGlue / EMAB, this solution requires a lower complexity interconnect architecture, achieves higher communication resource and pin utilization, and can support parallel bus communication.

[0037] For the different types of non-peer interconnects mentioned above, this embodiment is designed to provide corresponding slots, and the slots are backward compatible.

[0038] For a unified socket, its internal structure is divided into multiple functional areas of unlimited size / proportion, such as... Figure 3 As shown. Depending on the application requirements, the size of different types of slots can be the same or different. Optionally, the arrangement of functional areas has rotational symmetry, which allows the core to rotate 90 degrees, 180 degrees, or 270 degrees while maintaining its function.

[0039] For a specific non-peer interconnect type of slot, each functional area is assigned a functional type. Depending on the actual size requirements of the functional areas, the assigned functional types may be duplicated. The allocation of functional areas for different types of slots takes into account mutual compatibility, prioritizing the allocation of the same / similar functional types to functional areas located in the same position to ensure backward compatibility.

[0040] Depending on the interconnect scale requirements of the chip, a single chip can cover one or more slots. For the covered slots, the chip can use all or some of the functional areas as needed.

[0041] like Figure 8 As shown, in a specific embodiment, while referring to Figure 6 For example, the slot type corresponding to the computing core may have interconnection requirements for data, events, and states, where the normalized scale requirement for data / events / states is 5; the slot type corresponding to the control core may have interconnection requirements for data, events, and states, where the normalized scale requirement for data / events / states is 1; the slot type corresponding to the simulation core may have interconnection requirements for simulation, events, and states, where the normalized scale requirement for simulation / events / states is 1.

[0042] like Figure 9 As shown, in one specific embodiment, while referring to Figure 3 The aforementioned function types are sequentially assigned to the corresponding function areas of the slots to achieve backward compatibility. For example, control-type cores can be placed in compute-type core slots, and compute-type cores can be placed in control-type core slots, sacrificing some interconnect functions.

[0043] The aforementioned unified slot design not only supports the differentiated communication requirements of asymmetric interconnects and provides forward compatibility, but also maximizes the slot's compatibility with different types of chips, increasing the flexibility of chip integration and mitigating the reduced reuse flexibility caused by asymmetric interconnects. Compared to fully free interconnect solutions such as zGlue / EMAB, this solution eliminates the need for complex and large-scale Crossbar and MUX structures to switch pin power supply / analog / digital signals, achieving higher resource utilization.

[0044] For the highly fragmented needs of the industrial control field, this embodiment adopts an embedded eFPGA design to provide customized capabilities for different sub-scenarios without increasing the area, that is, by utilizing the idle part in the intermediary layer.

[0045] The eFPGA will be embedded within a reusable interposer layer, with no limit on the number, size, or location of embeddings, and will be tightly coupled to the interconnect channels. Based on the actual requirements of the reusable interposer layer, the eFPGA's input / output ports can flexibly communicate with the core chips via the interconnect channels, with no limit on the location or number of communication ports.

[0046] like Figure 4 As shown, in one specific embodiment, twelve eFPGA regions are divided in the free area outside the slots and interconnect channels. The eFPGAs are tightly coupled to the interconnect channels and can be used to implement customized logic functions.

[0047] The aforementioned embedded eFPGA design provides fragmented customization capabilities without increasing additional area, further enhancing its adaptability to specific domains. Compared to solutions with embedded SRAM such as DSA, this solution utilizes the idle portion of the interposer layer to improve scenario adaptability. Compared to off-chip FPGA solutions used in traditional applications, firstly, this solution eliminates the need for additional chips that occupy space and increase costs; secondly, it provides a high degree of configuration flexibility through tight coupling with interconnect channels, enhancing application flexibility.

[0048] To address the different interconnection characteristics in the industrial control field, this embodiment adopts a hierarchical interconnection approach, providing interconnection solutions that adapt to the characteristics of different types of interconnections.

[0049] In the design of interconnect architecture, the interconnect channels are divided into different types according to their functional types, such as... Figure 5 As shown, specific types of interconnect channels are adapted to corresponding functional characteristics. Low-speed interconnect channels, compared to high-speed channels, have lower timing requirements, thus receiving lower routing priority in the back-end process, and the adjustment range of synchronization modules can be reduced. Local interconnect channels consume fewer resources compared to global channels. A single slot may contain multiple types of interconnect channels, and a single interconnect channel can be used in multiple slots.

[0050] like Figure 7 As shown, in a specific embodiment, the interconnect channels are divided into three interconnect types. One group is a high-speed parallel interconnect channel, responsible for some inter-chip interconnects; another group is a general-purpose interconnect channel, responsible for signal transmission over a wider range; and the third group is a low-speed interconnect channel, responsible for global signal interconnects.

[0051] The hierarchical interconnect design described above provides multiple types of interconnect channels for the core system, adapting to the interconnect characteristics of different levels in industrial control systems. Compared with single interconnect architectures such as FPIA / zGlue, firstly, this solution is better suited to the interconnect requirements of industrial control applications; secondly, it can facilitate backend implementation, reduce layout resource usage, and lower intermediary layer power consumption by reducing the interconnect performance / communication range of some levels. Compared with limited multi-architecture interconnect solutions such as EMAB, the hierarchical interconnect capability of this solution is not limited to two different rates of global interconnect channels, and can provide hierarchical interconnect capabilities with different performance, communication ranges, and characteristics. Furthermore, high-speed internal parallel bus communication capability is provided through synchronizers and architectural design.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A reusable core interposer layer for industrial control applications, characterized in that: The intermediate layer surface is set up in a non-peer interconnection manner, dividing it into multiple slot areas. Each slot area is assigned a slot type, and each slot area has multiple functional areas arranged uniformly, each of which can be assigned a functional type. An eFPGA and interconnect channels are embedded within the intermediary layer. The eFPGA is coupled to the interconnect channels, which are arranged in a hierarchical interconnection manner among multiple slot regions.

2. The reusable core interposer layer for industrial control applications as described in claim 1, characterized in that: The slot types include computing, control, analog, and storage types, and each type of slot area is used to place the corresponding type of chip.

3. The reusable core interposer layer for industrial control applications as described in claim 2, characterized in that: A single core can be placed in one or more slot areas, and all or some of the functional areas can be used as needed.

4. The reusable core interposer layer for industrial control applications as described in claim 1, characterized in that: The arrangement of the functional areas has rotational symmetry.

5. The reusable core interposer layer for industrial control applications as described in claim 1, characterized in that: Within each slot area, the same / similar function types are assigned to function patches located in the same position.

6. The reusable core interposer layer for industrial control applications as described in claim 1, characterized in that: The functional types include data type, event type, status type, and simulation type.

7. The reusable core interposer layer for industrial control applications as described in claim 1, characterized in that: The eFPGA is located in the free area outside the slot area and the interconnect channel.

8. The reusable core interposer layer for industrial control applications as described in claim 7, characterized in that: The input / output ports of the eFPGA communicate with the chips placed in the slot area via interconnect channels.

9. The reusable core interposer layer for industrial control applications as described in claim 1, characterized in that: The hierarchical interconnection method involves dividing the interconnection channels according to their different functional types, including: High-speed parallel interconnect channels are responsible for data interconnection between short-distance cores; A universal interconnect channel is responsible for signal transmission between chips over long distances; The low-speed interconnect channel is responsible for signal interconnection between global chips.

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