Apparatus and method for controlling refresh operation

Abstract

Embodiments of the present disclosure relate to devices and methods for controlling refresh operations. Different banks of a memory array can perform different types of refresh operations for a pump in response to a refresh command or one or more pumps generated in response to the refresh command. In some examples, the type of refresh operation performed by a bank can vary from pump to pump of the refresh operation.

Description

Technical Field

[0001] This application generally relates to semiconductor devices. More specifically, this application relates to apparatus and methods for controlling refresh operations. Background Technology

[0002] Information can be stored as physical signals (e.g., the charge on a capacitor element) in individual memory cells. The memory may be volatile, and the physical signals may decay over time (which could degrade or corrupt the information stored in the memory cells). It may be necessary to periodically refresh the information in the memory cells, for example, by rewriting the information to restore the physical signals to their initial values.

[0003] As the size of memory components decreases, the density of memory cells has increased significantly. Automatic refresh operations are possible, in which sequences of memory cells are periodically refreshed. Repeated access to specific memory cells or groups of memory cells (often referred to as 'row hammers') can cause an increased rate of data degradation in nearby memory cells. In addition to automatic refresh operations, it may be desirable to identify and refresh memory cells affected by row hammers during targeted refresh operations. Targeted refresh operations can occur sequentially between automatic refresh operations. Summary of the Invention

[0004] On one hand, this application provides an apparatus comprising: a plurality of memory banks; and a plurality of refresh control circuits, each of the plurality of refresh control circuits being associated with a corresponding individual among the plurality of memory banks, wherein the individual among the plurality of refresh control circuits is configured to cause the corresponding individual among the plurality of memory banks to be performed at least partially in response to a refresh type signal, wherein the refresh operation type among the plurality of refresh operation types is at least partially based on the state of the refresh type signal; and a refresh type state control circuit configured to provide the refresh type signal to the plurality of refresh control circuits, wherein the refresh type signal includes a plurality of refresh type signals, wherein a first refresh type signal of the plurality of refresh type signals is provided to a first group of the plurality of first refresh control circuits and a second refresh type signal of the plurality of refresh type signals is provided to a second group of the plurality of first refresh control circuits, wherein the state of the first refresh type signal is different from the state of the second refresh type signal.

[0005] On the other hand, this application provides an apparatus comprising: a refresh control circuit including a first portion and a second portion comprising a plurality of portions, wherein the first portion includes a counter circuit configured to provide a first refresh type signal to at least one of the plurality of portions of the second portion and to provide a second refresh type signal to at least another of the plurality of portions of the second portion based at least in part on a count value, wherein the state of the first refresh type signal and the state of the second refresh type signal indicate a refresh operation type among a plurality of refresh operation types performed during a refresh operation, and wherein the second portion is configured to cause the refresh operation to be performed on a plurality of memory banks, wherein the refresh operation performed on an individual of the plurality of memory banks has the refresh operation type indicated by the first refresh type signal or the second refresh type signal.

[0006] On the other hand, this application provides a method comprising: providing a plurality of pumps with a refresh activation signal from a refresh pump generator; in response to a first pump of the plurality of pumps: providing a first refresh type signal having a first state to a first memory region, wherein the first state indicates a first type of refresh operation performed on a first memory cell in the first memory region; providing a second refresh type signal having a second state to a second memory region, wherein the second state indicates a second type of refresh operation performed on a second memory cell in the second memory region; further performing a first refresh operation of the first type on the first memory cell in response to the first refresh type signal; and further performing a second refresh operation of the second type on the second memory cell in response to the second refresh type signal, wherein the first refresh operation and the second refresh operation are performed simultaneously. Attached Figure Description

[0007] Figure 1A Illustrate examples of two different refresh operations in a memory device.

[0008] Figure 1B yes Figure 1A A timing diagram of an example refresh operation in a memory device.

[0009] Figure 2 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 This is an example layout diagram of at least a portion of a semiconductor device according to embodiments of the present disclosure.

[0011] Figure 4 This is a block diagram of at least a portion of a semiconductor device according to embodiments of the present disclosure.

[0012] Figure 5yes Figure 4 A block diagram of a semiconductor device.

[0013] Figure 6 This is a block diagram of a refresh type state control circuit according to an embodiment of the present disclosure.

[0014] Figure 7 This is a timing diagram illustrating an example operation of a memory device according to an embodiment of the present disclosure.

[0015] Figure 8A Examples of two different refresh operations in a memory device according to embodiments of the present disclosure are described.

[0016] Figure 8B yes Figure 8A A timing diagram of an example refresh operation in a memory device. Detailed Implementation

[0017] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form part of and illustrate by way of description specific embodiments in which the described system and method may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, certain features will not be described in detail where they are obvious to those skilled in the art so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of this disclosure is defined only by the appended claims.

[0018] Information in volatile memory devices can be stored in memory cells (e.g., as charge on capacitor elements) and may decay over time. Memory cells can be organized into rows (word lines) and columns (bit lines), and memory cells can be refreshed row by row. To prevent information from being lost or corrupted due to this decay, the memory can perform a refresh operation. During a refresh operation, information can be rewritten to the word line to restore its initial state. Automatic refresh operations can be performed sequentially on the word lines of the memory so that over time, each word line of the memory is refreshed at a rate faster than the expected data degradation rate.

[0019] Repeated access to a specific memory row (e.g., an aggressor row) may cause an increased decay rate in rows adjacent to the aggressor row (e.g., victim rows). These repeated accesses may be part of a deliberate attack on the memory and / or may be due to the memory's 'natural' access patterns. The increased decay rate in victim rows may require them to be refreshed as part of a targeted refresh operation. The memory device may periodically perform the targeted refresh operation. The targeted refresh operation may be an operation other than an automatic refresh operation. For example, the memory device may perform a set of refresh operations that include several automatic refresh operations and several targeted refresh operations and then repeat this cycle. In some embodiments, the targeted refresh operation may 'steal' a time slot that would otherwise be used for an automatic refresh operation. The memory device may typically cycle between performing an access operation for a period of time, performing a refresh operation for a period of time, performing an access operation, etc.

[0020] The refresh signal controls the timing of refresh operations. The refresh signal can be activated in response to a refresh command. The refresh signal can be activated multiple times in response to a refresh command. These multiple activations can be referred to as 'pumping'. A refresh operation can be performed in response to each pump. A refresh operation performed in response to multiple pumps associated with a refresh command can be referred to as a multi-pump refresh operation.

[0021] In response to the activation of a refresh signal, the memory bank may be able to perform more than one type of refresh operation, such as an automatic refresh operation and / or a targeted refresh operation. Some types of refresh operations can refresh multiple rows simultaneously. Simultaneously means that the refresh operations of multiple rows completely or almost completely overlap in time, either at the same time or nearly at the same time. Simultaneously refreshing multiple rows reduces the time required to refresh all rows in the memory. The rows may reside in the same or different memory banks. For example, multiple rows in each memory bank can be refreshed simultaneously. In another instance, one row in each memory bank can be refreshed simultaneously. Some types of refresh operations can refresh more rows simultaneously than other types of refresh operations.

[0022] Figure 1A This illustrates an example of two different refresh operations in a memory device. Memory device 100 includes a memory array divided into sixteen memory banks BK0-15. Pump A, in response to a refresh operation, refreshes each of the memory banks by... Figure 1AThe eight rows (e.g., word lines) are indicated by thick lines. In some instances, the refresh operation performed in response to Pump A may be an automatic refresh operation. Another pump, Pump B, in response to the refresh operation, refreshes one row in each of the memory banks. In some instances, the refresh operation performed in response to Pump B may be a target refresh operation in which the victim row from an invading row of a row hammer attack is refreshed. As illustrated, 128 rows in memory device 100 are refreshed in response to Pump A, while only 16 rows are refreshed in response to Pump B.

[0023] Figure 1B yes Figure 1A A timing diagram illustrating an example of a refresh operation in a memory device. In timing diagram 110, the top row indicates when a refresh command AREF is received. The second and third rows of timing diagram 110 illustrate, as illustrated by vertical lines, the refresh activation signal (e.g., pump) provided to the memory banks BK0-15 of memory device 100. Figure 1B In the examples shown, the pump is associated with one of two types of refresh operations: automatic refresh and target refresh. Figure 1A The different refresh states of Pump A and Pump B shown in the image correspond to... Figure 1B The stages of boxes A and B in the text. For example... Figure 1A and 1B Both demonstrate that the same type of refresh operation is performed on all memory banks during each pump.

[0024] like Figure 1A and 1B As illustrated, refreshing a large number of rows at once can cause an increase in peak current draw. High peak current can lead to undesirable voltage drops after a refresh operation, potentially causing errors in subsequent operations. Therefore, it may be desirable to reduce the number of rows refreshed simultaneously during a refresh operation.

[0025] This disclosure relates to apparatus, systems, and methods for performing various types of refresh operations in response to a pump of a refresh signal. Different types of refresh operations can be performed on different portions of a memory in response to a pump. For example, in response to a pump, one type of refresh operation (e.g., automatic refresh) can be performed on one or more rows, and another type of refresh operation (e.g., target refresh) can be performed on one or more other rows. In some embodiments, in response to a pump, one type of refresh operation can be performed on some memory banks, while another type of refresh operation can be performed on other memory banks. In response to a subsequent pump, different types of refresh operations can be performed on the memory banks. In some embodiments, the type of refresh operation performed on the memory banks in response to a pump can be alternated. By performing different types of refresh operations in response to a pump, the peak number of rows refreshed in response to a pump can be reduced. This, in turn, can reduce the peak current draw of the memory device.

[0026] While other techniques, such as time-interleaving of refresh operations across rows, banks, arrays, and / or dies, have been used to reduce peak current draw, these techniques require significant control circuitry. This can potentially increase design and / or manufacturing complexity. Extensive control circuitry can also require large layout areas, especially when significant control circuitry is required to be at bank logic levels—circuitry provided to control individual banks. When required to be at bank logic levels, the control circuitry can be required to replicate for each bank. In contrast, in some embodiments, different refresh operations performed on different rows during pumping can be implemented using minimal additional control circuitry. In some embodiments, the control circuitry of this disclosure may include counter circuitry (e.g., a bit counter circuitry) to generate control signals to cause different types of refresh operations to be performed on different banks. In some embodiments, the control circuitry of this disclosure may not be required to be at bank logic levels. Therefore, in some embodiments, the control circuitry of this disclosure may be shared by multiple banks.

[0027] Figure 2 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 200 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0028] Semiconductor device 200 includes memory array 218. Memory array 218 is shown as comprising multiple memory banks. Figure 2In this embodiment, memory array 218 is shown to comprise sixteen memory banks BANK0-BANK15. More or fewer memory banks may be included in memory array 218 in other embodiments. Each memory bank includes multiple word lines WL, multiple bit lines BL and / or BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / or BL. The selection of word lines WL is performed by row decoder circuitry 208, and the selection of bit lines BL and / or BL is performed by column decoder circuitry 210. Figure 2 In this embodiment, row decoder circuit 208 includes a corresponding row decoder circuit for each memory bank, and column decoder circuit 210 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to a corresponding sense amplifier (SAMP). Read data from bit line BL or / BL is amplified by the sense amplifier SAMP and transmitted to read / write amplifier 220 via complementary local data line (LIOT / B), transmission gate (TG), and complementary main data line (MIOT / B). Conversely, write data output from read / write amplifier 220 is transmitted to the sense amplifier SAMP via complementary main data line MIOT / B, transmission gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0029] The semiconductor device 200 may employ a plurality of external terminals, the plurality of external terminals including: a command and address (C / A) terminal coupled to a command and address bus to receive command and address and CS signals; a clock terminal for receiving clocks CK_t and CK_c; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ and VSSQ.

[0030] Clock terminals are supplied with external clocks CK_t and CK_c to input circuit 212. The external clocks may be complementary. Input circuit 212 generates an internal clock ICLK based on the CK_t and CK_c clocks. The ICLK clock is provided to command decoder circuit 210 and internal clock generator 214. Internal clock generator 214 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 222 to time the operation of circuits contained within input / output circuit 222, for example, to a data receiver to time the reception of written data.

[0031] The C / A terminal can be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 204 via command / address input circuitry 202. Address decoder 204 receives the address and supplies the decoded row address XADD to row decoder circuitry 208 and the decoded column address YADD to column decoder circuitry 210. Address decoder 204 can also supply a decoded bank address BADD, which indicates a bank of memory in memory array 218 containing the decoded row address XADD and column address YADD. Commands can be supplied to the C / A terminal. Examples of commands include access commands for accessing memory, such as commands for performing read operations and commands for performing write operations. Access commands can be associated with one or more of the row address XADD, column address YADD, and / or bank address BADD to indicate (a number of) memory cells to be accessed. In some embodiments, commands and / or addresses can be provided by components external to device 200, such as... Figure 2 The memory controller 201, which communicates with the device 200, is shown in the figure.

[0032] Commands can be provided as internal command signals to command decoder circuit 206 via command / address input circuit 202. Command decoder circuit 206 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder circuit 206 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0033] Device 200 can receive access commands for performing read operations. Upon receiving the command and immediately supplying it to the bank address, row address, and column address, read data is read from the memory cells corresponding to the row and column addresses in memory array 218. The command is received by command decoder circuit 206, which provides an internal command to supply the read data from memory array 218 to read / write amplifier 220. The read data is output to the outside via input / output circuit 222 from data terminal DQ.

[0034] Device 200 can receive access commands for performing write operations. When the command is received and is promptly supplied to the bank address, row address, and column address, write data supplied to the data terminal DQ is written to the memory cells in memory array 218 corresponding to the row and column addresses. The command is received by command decoder circuit 206, which provides an internal command causing the write data to be received by the data receiver in input / output circuit 222. A write clock can also be provided to an external clock terminal to time the reception of write data by the data receiver in input / output circuit 222. The write data is supplied to read / write amplifier 120 via input / output circuit 222 and then to memory array 218 for writing into memory cell MC.

[0035] As part of the self-refresh mode, device 200 may also receive commands that cause it to perform one or more refresh operations. Device 200 may be periodically placed in refresh mode. Therefore, refresh operations can be performed periodically whenever the memory device is in refresh mode. In some embodiments, a refresh mode command may be issued externally to memory device 200. In some embodiments, the refresh mode command may be generated periodically by components of the device. In some embodiments, a refresh signal AREF may also be activated when an external signal indicates a refresh mode entry command (e.g., an external refresh command). The refresh signal AREF may be a pulse signal activated when command decoder circuit 206 receives a signal indicating entry into self-refresh mode. The refresh signal AREF may be activated once immediately after command input and may thereafter be activated cyclically according to desired internal timing. In some embodiments, the refresh signal AREF may cause the execution of more than one refresh operation, which may be referred to as "multi-pump" refresh. In some embodiments, the refresh signal AREF may be active during refresh mode. In some embodiments, the refresh signal AREF may be active during multiple refresh operations. The refresh signal AREF can be used to control the timing of refresh operations during refresh mode. The self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and may cause device 200 to return to an idle state and / or resume other operations.

[0036] A refresh signal AREF is supplied to refresh control circuitry 216. Refresh control circuitry 216 supplies a refresh row address RXADD to row decoder circuitry 208, which refreshes one or more word lines WL indicated by the refresh row address RXADD. In some embodiments, refresh address RXADD may represent a single word line. In some embodiments, refresh address RXADD may represent multiple word lines, which may be refreshed sequentially or simultaneously by row decoder circuitry 208. In some embodiments, the number of word lines represented by refresh address RXADD may vary depending on the refresh address. Refresh control circuitry 216 can control the timing of the refresh operation and can generate and provide refresh address RXADD. Refresh control circuitry 216 can be controlled to change the details of refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address, the number of word lines represented by the address), or it can operate based on internal logic.

[0037] The refresh control circuit 216 can selectively output a target refresh address (e.g., specifying one or more victim addresses based on an aggressor) or an auto-refresh address (e.g., a sequence of auto-refresh addresses) as the refresh address RXADD. Based on the type of refresh address RXADD, the line decoder circuit 208 can perform a target refresh or auto-refresh operation. The auto-refresh address can be derived from an address sequence provided by a pump based on the activation of the refresh signal AREF and / or in response to AREF. The refresh control circuit 216 can repeatedly cycle the sequence of auto-refresh addresses at a rate determined by AREF. In some embodiments, the auto-refresh operation can typically occur at a certain timing such that the sequence of auto-refresh addresses is cycled so that no information is expected to degrade during the time between auto-refresh operations on a given word line. In other words, the auto-refresh operation can be performed such that each word line is refreshed at a rate faster than the expected rate of information decay.

[0038] As used herein, signal activation can refer to any part of the signal waveform in which a circuit responds. For example, if a circuit responds to a rising edge, then a signal switching from a low level to a high level might be considered activation. One type of activation is a pulse, where a signal switches from a low level to a high level for a period of time and then returns to a low level. This could trigger circuitry that responds to rising edges, falling edges, and / or signals at high logic levels.

[0039] The refresh control circuit 216 can also determine the target refresh address (e.g., the victim address corresponding to the victim row) as the address to be refreshed based on the access patterns of nearby addresses (e.g., the aggression address corresponding to the aggression row) in the memory array 218. The refresh control circuit 216 can use one or more signals from the device 200 to calculate the target refresh address. For example, the refresh address RXADD can be calculated based on the row address XADD provided by the address decoder 204.

[0040] In some embodiments, refresh control circuitry 216 may sample the current value of row address XADD provided by address decoder 204 along the row address bus and determine a target refresh address based on one or more of the sampled addresses. The sampled addresses may be stored in a data storage unit of the refresh control circuitry. When row address XADD is sampled, it may be compared with a stored address in the data storage unit. In some embodiments, an aggression address may be determined based on the sampled and / or stored addresses. For example, a comparison between the sampled and stored addresses may be used to update a count value associated with the stored address (e.g., an access count), and the aggression address may be calculated based on the count value. The refresh address RXADD may then be used based on the aggression address.

[0041] While this disclosure generally relates to identifying invading and victim word lines and addresses, it should be understood that, as used herein, an invading word line does not necessarily need to cause data degradation in adjacent word lines, and a victim word line does not necessarily need to suffer such degradation. The refresh control circuit 216 may use a criterion to determine whether an address is an invading address, which captures potential invading addresses rather than explicitly identifying which addresses cause data degradation in nearby victims. For example, the refresh control circuit 216 may determine potential invading addresses based on address access patterns, and this criterion may include some addresses that are not invading, while missing some addresses that are invading. Similar victim addresses may be identified based on which word lines are expected to be affected by invading, rather than explicitly identifying which word lines are experiencing an increased data decay rate.

[0042] The refresh address RXADD may have timing based on the timing of the refresh signal AREF. During periodic refresh operations in refresh mode, the refresh control circuit 216 may have time slots corresponding to the timing of AREF, and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the target refresh address may be issued in a time slot that would otherwise be assigned to an auto-refresh address (e.g., "stealing" the time slot). In some embodiments, certain time slots may be reserved for the target refresh address, and the refresh control circuit 216 may determine whether to provide the target refresh address, not provide an address during that time slot, or instead provide an auto-refresh address during said time slot.

[0043] The refresh control circuit 216 can use various methods to determine the timing of the target refresh operations. The refresh control circuit 216 can have periodic target refresh operations during refresh mode, wherein the refresh control circuit 216 performs automatic refresh operations and target refresh operations based on a periodic schedule (e.g., by providing a target refresh address as a refresh address RXADD). For example, after entering refresh mode, the refresh control circuit 216 can perform a certain number of automatic refresh operations, followed by (e.g., stealing) a certain number of target refresh operations. For multi-pump refresh operations, whenever a valid refresh signal AREF is received, the refresh control circuit 216 can perform M different refresh operations by providing M different refresh addresses RXADD. The refresh control circuit 216 can have a fixed pattern, where some pumps are assigned to automatic refresh operations and some pumps are assigned to target refresh operations.

[0044] In some embodiments, the pumps assigned to auto-refresh operations and the pumps assigned to target refresh operations may be different for different portions of the memory array 218. These portions may be defined by word lines, refresh addresses RXADD, and / or one or more memory banks. For example, in some embodiments, in response to a multi-pump refresh operation, an auto-refresh operation may be performed on some memory banks (e.g., BANK0-7), while a target refresh operation may be performed on other memory banks (e.g., BANK8-15). Continuing this example, in memory banks BANK0-7, the row address associated with the auto-refresh address may be refreshed, and in memory banks BANK8-15, the row address associated with the target refresh address may be refreshed. In response to a subsequent pump of the multi-pump refresh operation, a target refresh operation may be performed in memory banks BANK0-7, and an auto-refresh operation may be performed in memory banks BANK8-15. The refresh control circuitry 216 may provide the appropriate refresh address RXADD for each pump for the memory banks.

[0045] As described above, in response to a pump, some refresh operation types refresh more word lines than others. In some embodiments, the refresh address RXADD associated with an auto-refresh operation may correspond to more word lines than the refresh address RXADD associated with a target refresh operation. For example, multiple word lines per memory bank (e.g., 4, 8, 16) may be associated with the refresh address RXADD for an auto-refresh operation, while the refresh address RXADD associated with a target refresh operation may correspond to one word line per memory bank. Therefore, by performing multiple types of refresh operations (e.g., both auto-refresh and target refresh) in response to a pump, the peak number of word lines refreshed in response to a pump can be reduced. In some applications, this can reduce the peak current draw of device 200.

[0046] Power supply terminals are supplied with power potentials VDD and VSS. These potentials VDD and VSS are then supplied to an internal voltage generator circuit 224. The internal voltage generator circuit 224 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in the line decoder circuit 208, internal potentials VOD and VARY are primarily used in the sense amplifier SAMP contained in the memory array 218, and internal potential VPERI is used in many peripheral circuit blocks.

[0047] The power terminals are also supplied with power potentials VDDQ and VSSQ. Power potentials VDDQ and VSSQ are supplied to the input / output circuit 222. In an embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be the same as the power potentials VDD and VSS supplied to the power terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be different from the power potentials VDD and VSS supplied to the power terminals. The power potentials VDDQ and VSSQ supplied to the power terminals are used by the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 222 from propagating to other circuit blocks.

[0048] In some embodiments, some components of the device 200 may be shared by memory banks BANK0-15 (e.g., associated with multiple memory banks, provided for multiple memory banks). That is, the components may provide signals for controlling the operation of the multiple memory banks BANK0-15. Figure 2 In the example shown, address decoder 204 and command decoder 206 provide signals for operation in all memory banks BANK0-15. In some embodiments, components (e.g., associated with a subset of memory banks BANK0-15 or each memory bank BANK0-15) may be provided for a subset of memory banks BANK0-15 of the memory array 218. These components provide signals for controlling the operation of a particular memory bank or a subset of memory banks BANK0-15. Figure 2 In the example shown, each memory bank BANK0-15 is provided with a row decoder circuit 208, a column decoder circuit 210, and a read / write amplifier 220. Although Figure 2Only one refresh control circuit 216 is shown in this document, but in some embodiments, a separate refresh control circuit 216 may be provided for each memory bank BANK0-15. In some embodiments, some components of the apparatus 200 may include portions provided for individual memory banks BANK0-15, while other portions are shared among multiple memory banks BANK0-15. For example, as will be described in more detail herein, the refresh control circuit 216 may include separate components for each memory bank for determining a target refresh address for each memory bank BANK0-15, and may include shared components for providing one or more control signals to perform a refresh operation.

[0049] Figure 3 This is an example layout diagram of at least a portion of a semiconductor device according to embodiments of the present disclosure. In some embodiments, semiconductor device 300 may be included in semiconductor device 200. Semiconductor device 300 may include memory array 318. In some embodiments, memory array 318 may be included in... Figure 2 In the memory array 218. The memory array 318 includes several memory banks Banks0-15, which are arranged into memory bank groups BG0-3. Figure 3 In the example shown, memory array 318 includes sixteen memory banks arranged in four groups: Banks 0-3 in group BG0, Banks 4-7 in group BG1, Banks 8-11 in group BG2, and Banks 12-15 in group BG3. Other numbers of memory banks and / or memory bank groups and / or different arrangements of memory bank groups may be used in other examples. For example, memory banks assigned to memory bank groups do not need to be physically adjacent to each other.

[0050] In some embodiments, the memory cells and / or groups may be physically separated from each other by one or more peripheral regions of the device 300. The peripheral regions may contain various components of the memory, such as memory cell logic 302, DQ pads 306, and C / A pads (e.g., terminals) 308. In some embodiments, additional circuitry may also be included in the peripheral regions, such as command / address input circuitry, address decoders, and / or command decoders (not shown, see example, ...). Figure 2 , 4(and 5). The peripheral circuitry can transmit and receive signals to and from memory banks Bank0-15 to perform various memory operations (e.g., read, write, refresh). As will be described in more detail herein, in some embodiments, components provided for individual memory banks may be included in memory bank logic 302 and components provided for multiple memory banks may be included in other portions of the peripheral region. However, in other embodiments, components provided for multiple memory banks may be included in one or more of memory bank logic 302 and components provided for individual memory banks may be located outside of memory bank logic 302.

[0051] Each memory bank Bank0-15 contains multiple word lines and bit lines, with several memory cells arranged at their intersections. In some embodiments, rows (word lines) and columns (bit lines) may be further organized within the memory banks Bank0-15. For example, each memory bank Bank0-15 may contain several memory pads (not shown), each memory pad containing several rows and columns. The pads may be organized into pad groups. During an auto-refresh operation, an address may be provided, causing word lines in each pad of one or more memory banks Bank0-15 to be refreshed. Therefore, the number of word lines refreshed during an auto-refresh operation may be at least partially based on the number of pads in each memory bank Bank0-15.

[0052] In some embodiments, a refresh command may be issued jointly to all memory banks Bank0-15, and a refresh operation may be performed simultaneously on all memory banks Bank0-15 in response to one or more refresh signals, such as a pump of a refresh signal in response to a refresh command. In some embodiments, different refresh signals may be provided to memory banks Bank0-15, indicating the type of refresh operation to be performed (e.g., automatic or targeted). Thus, in response to a particular pump, one type of refresh operation may be performed in some memory banks Bank0-15, while another type of refresh operation may be performed simultaneously in other memory banks Bank0-15. For example, memory banks BG0 and BG2 may receive refresh signals indicating that an automatic refresh operation should be performed in response to a pump, and memory banks BG1 and BG3 may receive refresh signals indicating that a targeted refresh operation should be performed in response to a pump. Performing an automatic refresh operation may include refreshing the word line associated with the automatic refresh address, and performing a targeted refresh operation may include refreshing the word line associated with the target refresh address. Other partitioning of refresh operation types between memory banks can also be used (e.g., even-to-odd memory banks, separate signals for each memory bank group, etc.).

[0053] Each of the memory banks Bank0-15 can be used with the refresh control circuit ( Figure 3 Not shown in the text, see example Figure 2The refresh control circuit (216) or a portion thereof is associated with the memory bank Bank0-15, which may issue various refresh control signals and refresh addresses to that memory bank Bank0-15. Several refresh control circuits may be included in a peripheral area of ​​the device 300. In some embodiments, a portion or portions of the refresh control circuits may be included in memory bank logic 302 or other areas adjacent to memory banks Bank0-15. As will be described in more detail herein, the refresh control circuits may receive activation from AREF and may use one or more internal logic circuits to determine what refresh control signals are provided to indicate the refresh operation type and what refresh addresses are provided to individuals in memory banks Bank0-15. For example, the refresh control circuits may determine whether the refresh address provided to an individual in memory banks Bank0-15 should indicate an automatic refresh operation, a targeted refresh operation, or another type of refresh operation for a specific pump used for the refresh operation. In some embodiments, the type of refresh operation indicated by the refresh control signals and refresh addresses provided to the memory bank may vary depending on the pump used for the refresh operation.

[0054] Figure 4 This is a block diagram of at least a portion of a semiconductor device according to embodiments of the present disclosure. In some embodiments, semiconductor device 400 may be included in semiconductor device 200 and / or semiconductor device 300. Semiconductor device 400 may include a peripheral region 426 and one or more memory regions Bank_Region0-15. Peripheral region 426 may include one or more components for providing signals to and receiving signals from memory regions Bank_Region0-15 to perform memory operations. Individual memory regions Bank_Region0-15 may include memory banks (e.g., ...). Figure 2 storage bank BANK0-15 and / or Figure 3 The storage banks (Banks0-15) and one or more components for providing signals to and receiving signals from the storage banks. In some embodiments, the storage bank regions Bank_Region0-15 may contain at least a portion of the storage bank logic (e.g., storage bank logic 302). Although in Figure 4 The example shown illustrates sixteen memory areas, but other examples may contain more or fewer memory areas.

[0055] In some embodiments, peripheral area 426 may include command / address input circuit 402, address decoder circuit 404, and command decoder circuit 406. In some embodiments, command / address input circuit 402 may be included in command / address input circuit 102, address decoder circuit 404 may be included in address decoder circuit 104, and command decoder circuit 406 may be included in command decoder circuit 106. In some embodiments, peripheral area 426 may further include at least a portion of memory valid control circuit 442, control logic circuit 444, and refresh control circuit 416.

[0056] The memory bank valid control circuit 442 receives an activation and / or precharge signal ACT / Pre from the command decoder 406 and a memory bank address BADD from the address decoder 404. When a valid ACT signal is provided from the command decoder 406, the memory bank valid control circuit 442 can provide an activation control signal ACTQ based at least in part on the memory bank address BADD. The ACTQ signal can be received by control logic circuit 444, which can also receive a refresh activation signal RefACT. When either the ACTQ signal or the RefACT signal is valid, the control logic circuit 444 can provide a valid memory bank activation signal MBACT. The memory bank activation signal MBACT can activate (a number of) appropriate memory banks in the memory bank regions Bank_Region0-15. Figure 4 In the example shown, control logic circuit 444 includes OR logic circuitry. However, in other examples, alternative logic may be used.

[0057] For reference Figure 5 In further detail, in some embodiments, refresh control circuitry 416 may be part of refresh control circuitry. In some embodiments, refresh control circuitry 416 may include refresh pump generator circuitry 440 and refresh type state control circuitry 446. Refresh pump generator circuitry 440 may receive a refresh signal AREF from command decoder 406. In some embodiments, a valid refresh signal AREF may be provided in response to a refresh command, which may be generated externally (e.g., from a memory controller) or internally. In response to a valid refresh signal AREF, refresh pump generator circuitry 440 may provide one or more activations of a refresh activation signal RefACT. Activation of the RefACT signal may be referred to as “pumping” the RefACT signal. In some embodiments, refresh pump generator circuitry 440 may provide multiple pumps of RefACT in response to a valid AREF signal. The RefACT signal may be provided to control logic circuitry 444 and refresh type state control circuitry 446 as described above. Figure 5In more detail, in some embodiments, the AREF signal may also be provided to the storage area Bank_Region0-15.

[0058] The refresh type status control circuit 446 can provide a signal indicating the type of refresh operation performed by the memory bank in the corresponding memory bank region Bank_Region0-15 to the memory bank region Bank_Region0-15. The corresponding memory bank in the corresponding memory bank region Bank_Region0-15 can then perform a refresh operation of the type indicated by the refresh status control signal. This allows different types of refresh operations to be performed on different memory banks in response to the pumping of the RefACT signal. Figure 4 In the example shown, the refresh type status control circuit 446 provides two different refresh type signals, RHR_BKGA and RHR_BKGB, to the memory bank areas Bank_Region0-15. One state can be provided to the refresh type signals RHR_BKGA and RHR_BKGB to indicate one type of refresh operation, and another state can be provided to indicate another type of refresh operation. For example, a low logic state (e.g., '0') can indicate an automatic refresh operation, and a high logic state (e.g., '1') can indicate a target refresh operation.

[0059] The refresh type signal RHR_BKGA can be provided to one group of memory banks in memory bank region Bank_Region0-15, and the refresh type signal RHR_BKGB can be provided to another group of memory banks in memory bank region Bank_Region0-15. Figure 4 In the example shown, the refresh type signal RHR_BKGA is provided to memory regions Bank_Region0, Bank_Region1, Bank_Region4, Bank_Region5, Bank_Region8, Bank_Region9, Bank_Region12, and Bank_Region13, and the refresh type signal RHR_BKGB is provided to memory regions Bank_Region2, Bank_Region3, Bank_Region6, Bank_Region7, Bank_Region10, Bank_Region11, Bank_Region14, and Bank_Region15. Other divisions between refresh type signals may be used in other examples (e.g., RHR_BKGA may be provided to Bank_Regions0-7 and RHR_BKGB may be provided to Bank_Regions8-15). Furthermore, although... Figure 4 The example shows two refresh type signals, but in other instances, more refresh type signals may be available.

[0060] The refresh type state control circuit 446 can change the state of one or both of the refresh type signals RHR_BKGA and RHR_BKGB in response to different pumps of the RefACT signal. For example, in response to a pump, the refresh type state control circuit 446 can provide RHR_BKGA with a first state and RHR_BKGB with a second state. In response to a subsequent pump, the refresh type state control circuit 446 can provide RHR_BKGA with the second state and RHR_BKGB with the first state. The states of the refresh type signals RHR_BKGA and RHR_BKGB can be changed in a variety of ways (e.g., the states can be changed for each pump or every other pump).

[0061] Therefore, by providing different refresh type control signals to different memory banks for each pump, for example using refresh type state control circuit 446, different types of refresh operations can be performed simultaneously on different memory banks for each pump, and the type of refresh operation performed on different memory banks can be changed for different pumps performing multi-pump refresh operations. More details of the components of memory banks Bank_Regions0-15 will now be described.

[0062] Figure 5 yes Figure 4 A block diagram of a semiconductor device. Figure 5 The block diagram illustrates components of memory bank logic 518 in a memory bank region according to embodiments of the present disclosure. In some embodiments, memory bank logic 518 may include at least a portion of row control circuitry 516 and row decoder circuitry 508. Memory bank logic 518 may be included in Figure 4 The memory bank regions Bank_Region0-15 shown herein may be included. In some embodiments, each memory bank region Bank_Region0-15 may contain memory bank logic 518. That is, multiple refresh control circuits 516 and / or row decoder circuits 508 may exist, for example, one refresh control circuit 516 and / or row decoder circuit 508 per memory bank. For the sake of brevity, only the components of a single memory bank logic 518 will be described.

[0063] The row control circuit 516 may include a sampling timing circuit 530, an intruder detector circuit 532, a valid status decoder circuit 536, and a refresh address generator 534. Components in the peripheral area 426 may provide one or more control signals, such as the refresh signal AREF from the command decoder 406, the memory activation signal MBACT from the control logic circuit 444, the row address XADD from the address decoder 404, and the refresh type signal RHR_BKG (which may be such as...) from the refresh type status control circuit 446 to the row control circuit 516. Figure 4(RHR_BKGA or RHR_BKGB shown in the document). In some embodiments, the row control circuit 516 and the refresh control circuit 416 may be included in Figure 2 The refresh control circuit 216 is shown in the diagram. That is, the row control circuit 516 and the refresh control circuit 416 may be part of the refresh control circuit 216. In some embodiments, components of the refresh control circuit 416 may be shared by memory banks, while components of the row control circuit 516 are provided for individual memory banks. Although the refresh control circuit 416 provided for multiple memory banks is shown in the peripheral area 426 and the row control circuit 516 provided for individual memory banks is shown in the diagram... Figure 4 and 5 In the memory bank logic 518 of the memory bank region, however, in other embodiments, refresh control circuits 416, 516 may be located in other regions of the semiconductor device 400. For example, refresh control circuit 416 may be located in one of the memory bank regions Bank_Region0-15 and coupled to other memory bank regions.

[0064] The line control circuit 516 provides the refresh address RXADD to the line decoder 508 with timing based at least in part on the refresh signal AREF and the refresh type signal RHR_BKG, some of which is based on the received line address XADD. The line control circuit 516 may also provide additional control signals to the line decoder 508, as will be described in more detail.

[0065] Intruder detector circuit 532 can sample the current row address XADD in response to activation of sampling signal ArmSample. In some embodiments, the sampled address can be stored in intruder circuit 532 and / or compared with previously stored addresses. Intruder detector circuit 532 can provide a matching address HitXADD based on the currently sampled row address XADD and / or the previously sampled row address. Valid state decoder circuit 536 can provide a valid target refresh signal RHR_REF to indicate that a target refresh operation should occur (e.g., a refresh corresponding to the victim row of the identified intruder row, also known as a row hammer refresh). Valid state decoder circuit 536 can also provide an internal refresh signal IREF to indicate that an automatic refresh should occur. In response to activation of RHR_REF or IREF, refresh address generator 534 can provide a refresh address RXADD, which can be an automatic refresh address or one or more victim addresses corresponding to the victim row of the intruder row corresponding to the matching address HitXADD. The line decoder 508 can perform a refresh operation in response to the refresh address RXADD and the valid target refresh signal RHR_REF. The line decoder circuit 508 can perform an automatic refresh operation based on the refresh address RXADD and the valid internal refresh signal IREF. In some embodiments, the line decoder circuit 508 may be included in the line decoder circuit 208.

[0066] In embodiments where row access is monitored by sampling (as opposed to monitoring each access operation), sampling timing circuitry 530 provides a sampling arming signal ArmSample. The ArmSample signal may be a binary signal that is either at a high logic level (which may be represented by a first voltage, such as VDD) or at a low logic level (which may be represented by a second voltage, such as ground or VSS). Activation of ArmSample may be a 'pulse', wherein ArmSample rises to a high logic level and then returns to a low logic level. In some embodiments, sampling timing circuitry 530 may use one or more mechanisms to determine whether to provide activation of the ArmSample signal regularly (e.g., non-randomly), randomly, semi-randomly, or pseudo-randomly.

[0067] In some embodiments, the sampling timing circuit 230 may receive an activation signal ACT / Pre or an MBACT signal ( Figure 5 (Not shown in the text). In some embodiments, the activation of the signal ArmSample may be further based on the signal ACT / Pre to ensure that each activation of the signal ArmSample is associated with an access operation.

[0068] The intruder detector circuit 532 receives the row address XADD from the address decoder 404 and the signal ArmSample from the sampling timing circuit 530. The row address XADD on the row address bus can be changed to the memory cell array (e.g., ...) when the semiconductor device 400 directs access operations (e.g., read and write operations). Figure 2 Different rows of the memory cell array 218. Whenever the intruder detector circuit 532 receives the activation (e.g., pulse) of the signal ArmSample, the intruder detector circuit 532 can sample the current value of XADD. In some embodiments, the intruder detector circuit 532 can provide the current sampled value of XADD as the matching address HitXADD. The refresh address generator 534 can provide one or more victim addresses associated with the matching address HitXADD as the refresh address RXADD.

[0069] In some embodiments, in response to the activation of the signal ArmSample, the intruder detector circuit 532 may determine whether one or more rows are intrusive rows based on the sampled row address XADD, and may provide the identified intrusive row as a matching address HitXADD. As part of this determination, the intruder detector circuit 532 may record (e.g., by latching in a register and / or otherwise storing) the current value of XADD in response to the activation of ArmSample. The current value of XADD may be compared with previously recorded addresses in the intruder detector circuit 532 (e.g., addresses stored in latches / registers) to determine the access pattern of the sampled address over time. If the intruder detector circuit 532 determines that the address (in some embodiments, this may be the current address or a previously stored address) is an intrusive address, then the identified intruder may be provided as a matching address HitXADD. In some embodiments, the matching address HitXADD may be provided in response to the signal ArmSample. In some embodiments, when the refresh address generator 534 determines that a matching address is needed, the matching address (e.g., an aggression address) HitXADD can be stored in a latch circuit for later retrieval by the refresh address generator 534.

[0070] In one example embodiment, to determine whether the current address XADD is an aggressor address, a sampled value of the current row address XADD may be stored (e.g., latched in a latch circuit). Activation of ArmSample may also cause the aggressor detector circuit 532 to compare the currently sampled row address XADD with a previously stored address in the aggressor detector circuit 532. If the current row address XADD matches the stored address, then the current row address XADD can be provided as the matching address HitXADD.

[0071] In another embodiment, the intruder detector circuit 532 may store the value of the sampled address in a register and may have a counter associated with each of the stored addresses. When ArmSample is activated, the counter value may increment if the current row address XADD matches one of the stored addresses. In response to the activation of ArmSample, the intruder detector circuit 532 may provide the address associated with the highest value counter as the matching address HitXADD. Other methods for identifying intruder addresses may be used in other embodiments.

[0072] In embodiments that monitor each row access command, the sampling timing circuitry 530 may be omitted. In these embodiments, the aggressor detector circuitry 532 may perform the above functions in response to the ACT / Pre signal rather than the ArmSample signal.

[0073] The valid state decoder circuit 536 can receive the refresh signal AREF, the memory bank activation signal MBACT, and provide the row hammer refresh signal RHR_REF. The refresh signal AREF can be generated periodically and can be used to control the timing of the refresh operation. It can be applied to the memory bank (not shown, see example...). Figure 2 BANK0-15 and Figure 3 The sequence of BANK0-15 performs an automatic refresh operation to periodically refresh rows of the memory bank. The RHR_REF signal can be activated to indicate that a specific target row of the memory bank (e.g., the victim row) should be refreshed instead of the address from the sequence of automatic refresh addresses. The valid state decoder circuit 536 can use internal logic to provide the RHR_REF signal. In some embodiments, the valid state decoder circuit 536 can provide the RHR_REF signal at least in part based on the refresh type signal RHR_BKG. For example, the valid state decoder circuit 536 can provide a valid RHR_REF signal when RHR_BKG is valid. The valid state decoder circuit 536 can also provide a valid internal refresh signal IREF, which indicates that an automatic refresh operation should occur. In some embodiments, the signals RHR_REF and IREF can be generated such that they are not valid at the same time (e.g., not both at a high logic level at the same time).

[0074] In some embodiments, when the RHR_BKG signal, MBACT signal, and AREF signal are valid, the valid state decoder circuit 536 can provide a valid RHR_REF signal and an invalid IREF signal. In some embodiments, when the RHR_BKG signal is invalid and the MBACT and AREF signals are valid, the valid state decoder circuit 536 can provide an invalid RHR_REF signal and a valid IREF signal. In some embodiments, when MBACT or AREF is invalid, both the RHR_REF and IREF signals can be invalid, regardless of the state of the RHR_BKG signal. In some embodiments, the valid state decoder circuit 536 can further pass the MBACT signal to the line decoder 508, such as... Figure 5 As shown in the diagram, regardless of the state of any of the input signals. However, in other embodiments, the MBACT signal can be provided directly from the control logic circuit 444 to the line decoder circuit 508.

[0075] The refresh address generator 534 can receive a target refresh signal RHR_REF, an internal refresh signal IREF, and a matching address HitXADD. The matching address HitXADD can represent an aggressor row. The refresh address generator 534 can determine the location of one or more victim rows based on the matching address HitXADD and provide said location as a refresh address RXADD when the signal RHR_REF indicates a target refresh operation. In some embodiments, victim rows may include rows physically adjacent to the aggressor row (e.g., HitXADD+1 and HitXADD-1). In some embodiments, victim rows may also include rows physically adjacent to physically adjacent rows in the aggressor row (e.g., HitXADD+2 and HitXADD-2). In other instances, alternative or additional relationships between victim rows and identified aggressor rows can be used. For example, + / -3, + / -4, and / or other rows may also be refreshed or alternatively refreshed.

[0076] The refresh address generator 534 can determine the value of the refresh address RXADD based on the target refresh signal RHR_REF. In some embodiments, when the internal refresh signal IEF is active, the refresh address generator 534 can provide an auto-refresh address as a sequence of auto-refresh addresses. When the signal RHR_REF is active, the refresh address generator 534 can provide a target refresh address, such as a victim address, as the refresh address RXADD. In some embodiments, the refresh address generator 534 can count the activation of the signal RHR_REF and can provide closer victim lines (e.g., HitXADD+ / -1) more frequently than victim lines further away from the aggressor address (e.g., HitXADD+ / -2).

[0077] The row decoder 508 can perform one or more operations on the memory bank (not shown) based on received signals and addresses. For example, in response to the activation signal ACT and the row address XADD (and with IREF and RHR_REF invalid), the row decoder 508 can direct one or more access operations (e.g., read operations) at the specified row address XADD. In response to the RHR_REF or IREF signal being valid, the row decoder 508 can refresh the refresh address RXADD.

[0078] When the refresh address RXADD is associated with an auto-refresh operation, the refresh address RXADD can correspond to multiple word lines in the memory bank, for example, as referenced. Figure 3 The rows in each memory pad of the discussed memory bank. In some embodiments, when the refresh address RXADD is associated with a target refresh operation, the refresh address RXADD may correspond to fewer word lines than the number of word lines associated with the auto refresh address, for example, one word line in the memory bank. When different refresh operation types (e.g., auto and target) are performed on different memory banks for pumps, more word lines (e.g., one word line per pad) may be refreshed in some memory banks than in others (e.g., one word line in the memory bank). This allows for a reduction in the number of word lines refreshed for a given pump in the memory array (e.g., memory array 218), since the refresh of multiple word lines per memory bank can be spread across multiple pumps of a multi-pump refresh operation. This can reduce the peak current consumption of the semiconductor device 400.

[0079] exist Figure 4 and 5 In the example shown, the refresh type state control circuit 446 is shared across all Bank Regions 0-15 and is used to provide control signals (e.g., RHR_BKG, RHR_BKGA, RHR_BKGB) to Bank Regions 0-15 to induce different types of refresh operations in response to pumping of multi-pump refresh operations. Therefore, in some embodiments, only one refresh type state control circuit 446 may exist for all banks of the memory array (e.g., memory array 218), rather than one refresh type state control circuit 446 for each bank. This reduces the number of additional circuits required to implement different types of refresh operations. Furthermore, in some embodiments, the refresh type state control circuit may be implemented using circuitry with relatively few components, such as those described in Reference 10. Figure 6 As described.

[0080] Figure 6This is a block diagram of a refresh type state control circuit according to an embodiment of the present disclosure. In some embodiments, refresh type state control circuit 600 may be included in refresh type state control circuit 446. Refresh type state control circuit 600 may include inverter 648, one-bit counter circuit 650, and latches 656, 658. Refresh type state control circuit 600 may receive a refresh activation signal RefACT, for example, from a refresh pump generator, such as refresh pump generator 440, and provide refresh type signals RHR_BKGA, RHR_BKGB to one or more memory banks, such as memory banks Bank_Regions0-15.

[0081] Inverter 648 can receive a RefACT signal as input and provide an inverted RefACT signal as output, which can be received by a one-bit counter circuit 650. The one-bit counter circuit 650 may include a flip-flop 652 that receives the inverted RefACT signal from inverter 648 as a clock input. The state of flip-flop 652 can be provided as input to inverter 654, which provides the inverted state of flip-flop 652 as an output, which can be provided as the output RHRT of the one-bit counter circuit 650. A non-inverted state of flip-flop 652 is also provided as the output RHRF of the one-bit counter circuit 650. In some embodiments, RHRT and RHRF can be complementary. The output of inverter 654 can also be provided as a data input back to flip-flop 652. In operation, in response to a pump (e.g., activation) of the RefACT signal, the outputs RHRT and RHRF of the one-bit counter circuit 650 can transition between different states (e.g., low and high logic states, '0' and '1') with each pump.

[0082] The outputs RHRT and RHRF of the one-bit counter circuit 650 can be received by latches 656 and 658, respectively. Latches 656 and 658 can be triggered by the RefACT signal. The latched signal from the one-bit counter circuit 650 can be output by latches 656 and 658 as refresh type signals RHR_BKGA and RHR_BKGB, respectively. When RHRT and RHRF are complementary, RHR_BKGA and RHR_BKGB may also be complementary. That is, RHR_BKGA and RHR_BKGB can have different states, as described in reference... Figure 4 and 5 The aforementioned approach can correspond to different types of refresh operations. In some embodiments, the refresh type signal RHR_BKGA can be provided to a different memory bank region than the refresh type signal RHR_BKGB. Therefore, different memory bank regions can perform different types of refresh operations in response to the pumping of the RefACT signal.

[0083] Figure 7 This is a timing diagram illustrating an example operation of a memory device according to an embodiment of the present disclosure. Timing diagram 700 illustrates the operation of a refresh type state control circuit, for example... Figure 6 The refresh type state control circuit 600 shown receives and provides various signals over time, reflecting the signal state. Although... Figure 7 The states of the signals shown are not limited to the refresh type state control circuit 600, but for illustrative purposes, the characteristics of timing diagram 700 will be explained with reference to the refresh type state control circuit 600.

[0084] The first row of timing diagram 700 shows the state of the refresh activation signal RefACT, which may be provided by, for example, a refresh pump generator circuit 440. The second row of timing diagram 700 shows the state of the output of a counter circuit, such as a one-bit counter circuit 650. The third and fourth rows of timing diagram 700 show the outputs of refresh type state control circuits, such as refresh type state control circuit 600 and / or refresh type state control circuit 446.

[0085] The RefACT signal may have a rising edge r0 at or near time T0. That is, RefACT may transition from a low logic state (e.g., invalid) to a high logic state (e.g., valid). In some embodiments, the rising edge r0 may be at least partially responsive to the refresh signal AREF. At or near time T1, the RefACT signal may have a falling edge f0, where RefACT transitions from a high logic state to a low logic state. In response to the falling edge f0, the RHRT signal may transition from a low logic state to a high logic state at or near time T1. In some embodiments, the transition of RHRT may be at least partially responsive to the transition from a low logic state to a high logic state of the output provided from inverter 648 to flip-flop 652. Although not shown in timing diagram 700, at or near time T1, RHRF may transition from a high logic state to a low logic state in response to the transition of the RefACT signal.

[0086] Similarly, at or near time T1, in response to the transitions of RHRT and RHRF and the falling edge f0, RHR_BKGA can transition from a low logic state to a high logic state, and RHR_BKGB can transition from a high logic state to a low logic state. In some embodiments, this may be because latches 656 and 658 are triggered by the RefACT signal to latch the RHRT and RHRF signals, respectively. Figure 7As shown, the refresh type signal RHR_BKGA can have a different state than the refresh type signal RHR_BKGB. Different states can correspond to different refresh operation types. Therefore, in some embodiments, at the memory area receiving RHR_BKGA, a different refresh operation type can be performed on the memory area than the memory area receiving RHR_BKGB.

[0087] At or near time T2, the RefACT signal may have a rising edge rl. RHRT, RHRF, RHR_BKGA, and RHR_BKGB may maintain their current states. In some embodiments, this may be because flip-flop 552 is not triggered by the rising edge of the output of inverter 548 and / or in some embodiments latches 556, 558 are not triggered by the rising edge of the RefACT signal. At or near time T3, the RefACT signal may have a falling edge f1. In response to the falling edge f1, the RHRT signal may transition from a high logic state to a low logic state. In response to the falling edge f1, the RHRT signal may transition from a high logic state to a low logic state at or near time T3. Although not shown, the RHRF signal may transition from a low logic state to a high logic state at or near time T3. Also at or near time T3, in response to the transitions of RHRT and RHRF and the falling edge f1, RHR_BKGA may transition from a high logic state to a low logic state, while RHR_BKGB may transition from a low logic state to a high logic state. Figure 7 As shown, the refresh type signals RHR_BKGA and RHR_BKGB provided to the memory bank area can change with each pump of the RefACT signal. Therefore, in some embodiments, different refresh operations on the memory bank can be performed using different pumps of the RefACT signal at different memory bank areas.

[0088] As shown at times T4 and T5, the RefACT signal can continue to provide pumping, and the RHRT, RHR_BKGA, and RHR_BKGB signals can change in a manner similar to that described at reference times T0-3. The number of pumps provided by RefACT may vary. For example, the number of pumps may be based on the pre-programmed settings of the memory device, the number of pumps indicated by a refresh command, and / or one or more mode register settings of the memory device.

[0089] Figure 8A This describes examples of two different refresh operations in a memory device according to embodiments of the present disclosure. Memory device 800 includes a memory array divided into sixteen memory banks BK0-15. In some embodiments, memory device 800 may be included in semiconductor device 200, semiconductor device 300, and / or semiconductor device 400. In response to a refresh operation, Pump A refreshes one half of the memory bank by... Figure 8A The solid lines in the memory indicate eight rows (e.g., word lines), and one row is refreshed in the other half of the memory. In some instances, the refresh operation that refreshes eight rows can be an automatic refresh operation, and the refresh operation that refreshes one row can be a targeted refresh operation. In response to another refresh operation, Pump B refreshes one row in the half of the memory that previously refreshed eight rows and refreshes eight rows in the half of the memory that previously refreshed one row. As illustrated, 72 rows in the memory device 800 are refreshed in response to Pump A and 72 rows are refreshed in response to Pump B.

[0090] Figure 8B yes Figure 8A A timing diagram illustrating an example of a refresh operation in a memory device. In timing diagram 810, the top row indicates when a refresh command AREF is received. The second and third rows of timing diagram 810 illustrate, as vertical lines, the two groups of refresh activation signals (e.g., pumps) provided to the memory banks of memory device 800. Figure 8B In the examples shown, the pump is associated with one of two types of refresh operations: automatic refresh and target refresh. Figure 8A The different refresh states of PumpA and PumpB shown in the image correspond to... Figure 8B The stages of boxes A and B in the text. For example... Figure 8A and 8B Both demonstrate that during pumping, one type of refresh operation is performed on some memory banks and another type of refresh operation is performed on other memory banks, rather than as... Figure 1A and 1B As shown in the diagram, the same type of refresh operation is performed on all memory banks.

[0091] and Figure 1A and 1B In comparison, through such Figure 8A and 8B As explained, different pumps are used to perform different refresh operations in different memory banks, reducing the peak number of rows refreshed per operation from 128 to 72. In some applications, this may reduce peak current draw. In other applications, this may reduce the risk of errors in future memory operations.

[0092] Although the examples provided herein describe two different types of refresh operations (e.g., automatic refresh and targeted refresh operations), in some embodiments, additional types of refresh operations may be performed by the memory device (e.g., refresh-managed refresh operations). In these embodiments, more than two refresh type signals may be provided to memory banks. In some embodiments that perform more than two types of refresh operations, the refresh type state control circuitry may include a multi-bit counter (e.g., a two-bit counter) that can be used to generate refresh type signals for different memory banks. The count of the counter circuitry may change with one or more pumps of a multi-pump refresh operation. When the count changes, the state of the refresh type signal may also change.

[0093] This disclosure relates to apparatus, systems, and methods for performing multiple types of refresh operations in response to a pump of a refresh signal. Different portions of a memory may perform different types of refresh operations in response to a pump. For example, in response to a pump, one type of refresh operation (e.g., automatic refresh) may be performed on one or more rows, and another type of refresh operation (e.g., target refresh) may be performed on one or more other rows. In some embodiments, in response to a pump, one type of refresh operation may be performed on some memory banks, while another type of refresh operation may be performed on other memory banks. In response to a subsequent pump, different types of refresh operations may be performed on memory banks. In some embodiments, the type of refresh operation performed on memory banks in response to a pump may be alternated. By performing different types of refresh operations in response to a pump, the peak number of rows refreshed in response to a pump can be reduced. This, in turn, can reduce the peak current draw of the memory device. In some embodiments, the apparatus, systems, and methods may be implemented by circuitry having a relatively small number of components that can be shared by multiple memory banks.

[0094] Of course, it should be understood that any of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and / or processes, or may be performed separately and / or in a separate device or device portion, based on this system, apparatus and method.

[0095] Finally, the foregoing discussion is intended merely to illustrate the system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system has been described in particular detail with reference to exemplary embodiments, it should be understood that many modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and contemplated spirit and scope of the system as set forth in the appended claims. Thus, the specification and drawings should be regarded as illustrative and not intended to limit the scope of the appended claims.

Claims

1. A semiconductor device comprising: Multiple storage banks; and A plurality of refresh control circuits, each of which is associated with a corresponding individual in a plurality of memory banks, wherein the individual of the plurality of refresh control circuits is configured to cause one of a plurality of refresh operation types to be performed on the corresponding individual in the plurality of memory banks in at least part of a refresh type signal, wherein the refresh operation type of the plurality of refresh operation types is at least partly based on the state of the refresh type signal; and A refresh type state control circuit configured to provide the refresh type signal to the plurality of refresh control circuits, wherein the refresh type signal includes a plurality of refresh type signals, wherein a first refresh type signal of the plurality of refresh type signals is provided to a first group of the plurality of first refresh control circuits and a second refresh type signal of the plurality of refresh type signals is provided to a second group of the plurality of first refresh control circuits, wherein the state of the first refresh type signal is different from the state of the second refresh type signal, the refresh type state control circuit comprising: A trigger circuit, wherein the output of the trigger circuit provides the first refresh type signal; An inverter configured to receive the output of the flip-flop as an input and provide the output of the inverter as a second refresh type signal; A second inverter is configured to receive a pump signal as input and provide an inverted pump signal as output to the clock input of the flip-flop; A first latch, configured to latch the output of the inverter in response to a falling edge of the pump signal; and A second latch is configured to latch the output of the flip-flop in response to the falling edge of the pump signal.

2. The semiconductor device of claim 1, further comprising a refresh pump generator configured to provide at least one pump in at least part of response to a valid refresh signal, wherein the refresh type state control circuitry is configured to change at least one of the state of the first refresh type signal or the state of the second refresh type signal in response to the at least one pump.

3. The semiconductor device of claim 1, wherein each of the plurality of refresh type signals has a different state.

4. The semiconductor device of claim 1, wherein the refresh type state control circuitry includes a counter configured to generate the plurality of refresh type signals, the counter including a trigger and the inverter.

5. The semiconductor device of claim 4, wherein the counter is a bit counter.

6. The semiconductor device of claim 1, wherein the output of the inverter is further provided as a data input to the trigger.

7. A semiconductor device comprising: The refresh control circuit includes a first part and a second part comprising multiple parts. The first part includes: A counter circuit configured to provide a first refresh type signal to at least one of the plurality of portions of the second portion and a second refresh type signal to at least another of the plurality of portions of the second portion, based at least in part on a count value, wherein the state of the first refresh type signal and the state of the second refresh type signal indicate a refresh operation type among a plurality of refresh operation types performed during a refresh operation. An inverter configured to receive a pump signal as input and provide an output to the counter circuit; A first latch is configured to latch the first refresh type signal in response to the falling edge of the pump signal; and A second latch is configured to latch the second refresh type signal in response to the falling edge of the pump signal, and The second part is configured to cause the refresh operation to be performed on a plurality of memory banks, wherein the refresh operation performed on an individual of the plurality of memory banks has a refresh operation type indicated by the first refresh type signal or the second refresh type signal.

8. The semiconductor device of claim 7, wherein the first portion further comprises a refresh pump generator configured to provide a plurality of pumps in response to a refresh signal, wherein the counter circuitry is configured to change the count value in response to each of the plurality of pumps.

9. The semiconductor device of claim 8, wherein the counter circuit is configured to change the count value in response to the falling edge of each of the plurality of pumps.

10. The semiconductor device of claim 7, wherein the first portion is included in a peripheral region of the memory device and individual portions of the plurality of portions of the second portion are included in corresponding memory regions of a plurality of memory regions of the memory device, the plurality of memory regions being separated from the peripheral region, wherein individual portions of the plurality of memory are included in corresponding portions of the plurality of memory regions.

11. The semiconductor device of claim 10, further comprising command decoder circuitry included in the peripheral region, wherein the refresh operation is performed at least in part in response to a valid refresh signal provided by the command decoder.

12. The semiconductor device of claim 7, wherein the state of the first refresh type signal is complementary to the state of the second refresh type signal.

13. The semiconductor device of claim 7, wherein the counter circuit includes a trigger configured to receive the output of the inverter and provide the first refresh type signal.

14. The semiconductor device of claim 13, wherein the counter circuit further includes an inverter configured to receive the first refresh type signal and output the second refresh type signal.

15. A method for performing memory operations, comprising: Multiple pumps provide refresh activation signals from the refresh pump generator; In response to the first pump of the plurality of pumps: A first refresh type signal having a first state is provided to the first memory area, wherein the first state indicates a first type of refresh operation performed on the first memory of the first memory area; A second refresh type signal having a second state is provided to the second memory area, wherein the second state indicates a second type of refresh operation performed on the second memory of the second memory area; Further, in response to the first refresh type signal, a first refresh operation of the first type is performed on the first memory bank; and Further, in response to the second refresh type signal, a second refresh operation of the second type is performed on the second memory bank, wherein the first refresh operation and the second refresh operation are performed simultaneously. The first refresh type signal and the second refresh type signal are provided by a refresh type state control circuit including a counter circuit, and The refresh type state control circuit further includes: An inverter configured to receive the plurality of pumps and, based on the plurality of pumps, provide an inverted pump signal to the counter circuit; A first latch, configured to latch a first output of the counter circuit in at least a partial response to each of the plurality of pumps and to provide the first refresh type signal; and A second latch is configured to latch a second output of the counter circuit in at least a partial response to each of the plurality of pumps and to provide a second refresh type signal.

16. The method of claim 15, further comprising: In response to the second pump of the plurality of pumps: The first refresh type signal having the second state is provided to the first memory area; The second refresh type signal having the first state is provided to the second memory area; Further, in response to the first refresh type signal, a third refresh operation of the second type is performed on the first memory bank; and Further, in response to the second refresh type signal, a fourth refresh operation of the first type is performed on the second memory bank, wherein the third refresh operation and the fourth refresh operation are performed simultaneously.

17. The method of claim 15, wherein the count of the counter circuit changes with each of the plurality of pumps and wherein whenever the count changes, the state of the first refresh type signal and the state of the second refresh type signal change.

18. The method of claim 15, wherein the first type of refresh operation includes an automatic refresh operation and the second type of refresh operation includes a target refresh operation.

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