Heterojunction bipolar transistor and manufacturing method thereof

Abstract

The present invention provides a heterojunction bipolar transistor and a manufacturing method thereof. The fin replacement technology is used to form a fin structure on a substrate and a well region serving as a collector region in the substrate. The bottom of the fin is connected to the well region serving as a collector. The first portion of the fin corresponding to the well region is removed, that is, part of the fin is hollowed out to form a first opening, and then the base material is deposited to form a base fin. The remaining portion of the fin corresponding to the well region is removed, that is, the remaining portion of the fin is hollowed out to form a second opening, and then the base region is deposited, and then an emitter region is formed above the base region. A base epitaxial cap layer and an emitter epitaxial cap layer are formed outside the base fin and the emitter region, respectively. The above method is easy to integrate into the FinFET technology platform. The equivalent base and collector resistance of the heterojunction bipolar transistor of the present invention is small, and the transistor has low leakage current and excellent electrical performance. It is also easy to integrate with FinFET devices, thereby improving the integration of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a heterojunction bipolar transistor and a manufacturing method thereof. Background Art

[0002] Traditional vertical bipolar transistor (VBT) technology is a staple of high-speed computers. Its notable features include: 1) a polysilicon emitter, which allows the base width to be scaled below 100nm; 2) emitter-base self-alignment and deep and shallow trench isolation, which reduces device size and capacitance; and 3) a self-aligned, more heavily doped intrinsic collector region to further increase speed. Today, heterojunction bipolar transistors (HBTs) using BiCMOS technology are widely used in automotive radar, high-speed wireless and optical data links, and high-precision analog circuits. The HBT structure is similar to a conventional VBT, except that the base is replaced with a small amount of C-doped SiGe. Advanced CMOS and SiGe BiCMOS technologies may address future 5G communication standards with frequencies up to 40GHz, a strong contender for high-data-rate wireless or fiber-optic backhaul.

[0003] Fin pn junctions can be improved by deeper junctions. Optimized fin junction transistors show near-perfect ideality with low leakage current and stable temperature performance up to 125°C. The improved PN transistor performance at high temperatures can be attributed to the reduction of junction defects. Vertical pnp bipolar transistors using optimized fin junctions show excellent characteristics (β and linearity), low leakage current, high breakdown voltage BVCEO, and a near-perfect ideality factor η≈1.01, without leakage current typically caused by stacking faults in highly stressed eSiGep+ / n junctions.

[0004] The success of SiGe BiCMOS technology with (npn) HBT is mainly attributed to its ability to provide excellent performance (through the narrower bandgap of SiGe baseband) at a high integration density and yield, resulting in a very competitive cost, especially for the communications market. So far, the most advanced SiGe HBT can be integrated with 40nm CMOS. However, due to process complexity, there is no SiGe HBT technology available for devices of 14nm and below on the FinFET platform. Since 5G communication has become a reality, we need device structures and integration methods for high-performance SiGe HBTs on the FinFET platform. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a heterojunction bipolar transistor and a method for manufacturing the same. The method uses fin replacement technology to form a fin-type heterojunction bipolar transistor on a FinFET platform. Taking the formation of an npn-type transistor as an example, the fin replacement technology is used to deposit (p-type) SiGe:C in the fin as a base region, the bottom of the fin is connected to the n-well used as the collector region, and polysilicon is formed on the top of the fin as an emitter region. The equivalent base and collector resistance of the heterojunction bipolar transistor of the present invention is very small (smaller than the traditional HBT structure). In addition, the method of the present invention is simple and easy to integrate into the FinFET technology platform.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a heterojunction bipolar transistor, the method comprising:

[0007] Providing a substrate, forming a plurality of mutually parallel long strip fins on the substrate, and forming an isolation structure between adjacent fins, wherein the isolation structure is flush with the fins, the fins including a first fin region, and the first fin region including the plurality of fins;

[0008] Performing ion doping on the substrate to form a well region having a second conductivity type in the substrate to form a collector region, wherein the well region corresponds to the first fin region;

[0009] removing a first portion of the fin in the first fin region to form a first opening;

[0010] forming a first semiconductor material layer having a first conductivity type in the first opening to form a base fin, wherein the second conductive line type is opposite to the first conductivity type;

[0011] removing a second portion of the fin in the first fin region to form a second opening;

[0012] forming the first semiconductor material layer in the second opening, wherein the base fin formed in the first opening and the first semiconductor material layer formed in the second opening form a base region, and the thickness of the first semiconductor material layer is less than the height of the second opening;

[0013] A second semiconductor material layer having a second conductivity type is formed over the base region to form an emitter region.

[0014] Optionally, forming a first semiconductor material layer having a first conductivity type in the first opening to form a base fin further includes the following steps:

[0015] cleaning the bottom and side walls of the first opening;

[0016] P-type SiGe is selectively epitaxially grown in the first opening.

[0017] Optionally, forming the base region and the emitter region further comprises the following steps:

[0018] cleaning the bottom and side walls of the second opening;

[0019] selectively epitaxially growing P-type SiGe in the second opening;

[0020] N-type doped polysilicon is formed on the P-type SiGe.

[0021] Optionally, the P-type SiGe is C-doped SiGe.

[0022] Optionally, the N-type doped polysilicon is As-doped polysilicon.

[0023] Optionally, the manufacturing method further comprises the following steps:

[0024] removing the isolation structure to expose at least a portion of the base fin and a portion of the emitter region;

[0025] forming a base region epitaxial cap layer outside the base fin, wherein the epitaxial cap layer is connected to the base fin;

[0026] An emitter region epitaxial cap layer is formed outside the emitter region, and the emitter region epitaxial cap layer is connected to the emitter region.

[0027] Optionally, the base region epitaxial capping layer is P-type SiGe, and the emitter region epitaxial capping layer is n-type polysilicon.

[0028] Optionally, the manufacturing method further includes:

[0029] forming a base electrode above the base epitaxial cap layer;

[0030] forming an emitter electrode above the emitter region epitaxial cap layer;

[0031] A collector electrode is formed above the substrate.

[0032] Optionally, the fin further includes a second fin region, and the manufacturing method further includes the following steps:

[0033] forming a replacement gate stack in the channel region of the fin in the second fin region;

[0034] forming a source region and a drain region at both ends of the channel region;

[0035] removing the replacement gate stack to form a gate opening exposing the channel region;

[0036] A gate structure is formed in the gate opening.

[0037] Optionally, the second opening portion is formed in the base fin.

[0038] According to another aspect of the present invention, there is provided a heterojunction bipolar transistor, the heterojunction bipolar transistor comprising:

[0039] A substrate, with a plurality of parallel long strip fins formed on the substrate, the fins including a first fin region, and the first fin region including the plurality of fins;

[0040] A collector region formed in the substrate, the collector region corresponding to the first fin region;

[0041] forming a base fin in the first fin region;

[0042] A base region is formed in the first fin region, the base region and the base fin forming a continuous structure;

[0043] An emitter region is formed above the base region.

[0044] Optionally, the material of the base fin and the base region is P-type GeSi.

[0045] Optionally, the material of the base fin and the base region is C-doped SiGe.

[0046] Optionally, the material of the emitter region is N-type doped polysilicon.

[0047] Optionally, the material of the emitter region is As-doped polysilicon.

[0048] Optionally, the heterojunction bipolar transistor further includes:

[0049] A base epitaxial cap layer is formed outside the base fin, wherein the base epitaxial cap layer is connected to the base fin;

[0050] An emitter region epitaxial cap layer is formed outside the emitter region, and the emitter region epitaxial cap layer is connected to the emitter region.

[0051] Optionally, the heterojunction bipolar transistor further includes:

[0052] a base electrode formed above the base epitaxial cap layer;

[0053] an emitter electrode formed above the epitaxial cap layer of the emitter region;

[0054] A collector electrode is formed above the substrate.

[0055] Optionally, the fin further includes a second fin region, wherein a MOS device is formed in the second fin region, and the MOS device includes:

[0056] A source region and a drain region formed at both ends of the fin in the second fin region, and a channel region located between the source region and the drain region;

[0057] A gate structure is formed around the channel region.

[0058] As described above, the heterojunction bipolar transistor and the manufacturing method thereof provided by the present invention have at least the following beneficial technical effects:

[0059] The present invention adopts fin replacement technology when manufacturing heterojunction bipolar transistors. A fin structure is formed on the substrate and a well region is formed in the substrate as the collector region. The bottom of the fin is connected to the well region used as the collector. The base material is deposited in the fin used as the base fin to form the base fin. The base material is first deposited in the fin forming the heterojunction to form the base region. The base fin and the base region are connected by an outer cap layer. Then, a different material is deposited above the base region to serve as the emitter region. For example, in an npn heterojunction transistor, the well region in the substrate is an n-type doped well region, the base region material is C-doped p-type SiGe, and the emitter region material is As-doped n-type polysilicon Si. The contacts of the emitter, base, and collector can all be on the surface. The above method is simple and easy to integrate into the FinFET technology platform. The technology of this application realizes the formation of 14nm and the most advanced heterojunction based on FinFET technology, filling the gap in integrating SiGe HBT on the 14nm and more advanced FinFET platforms.

[0060] The heterojunction bipolar transistor formed by the above method has small equivalent base and collector resistances, low leakage current, and excellent electrical performance. It is also easy to integrate with FinFET devices, thereby improving the integration of the devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 Shown is a schematic flow chart of a method for manufacturing a heterojunction bipolar transistor provided in the first embodiment of the present invention.

[0062] Figure 2 Shown is a schematic diagram of the structure of forming fins on a substrate.

[0063] Figure 3 Shown as Figure 2 Schematic diagram of the structure in which a well region is formed in the structure shown.

[0064] Figure 4 Shown as Figure 3 Schematic diagram of a structure in which a first mask layer is formed above the structure shown.

[0065] Figure 5 Shown as Figure 4The diagram shows a structure in which a first mask layer forms a first opening in a fin in a first fin region.

[0066] Figure 6 Shown is a schematic structural diagram of forming a base fin at the first opening position.

[0067] Figure 7 Shown as Figure 6 Schematic diagram of a structure in which a second mask layer is formed above the structure shown.

[0068] Figure 8 It is a schematic diagram showing the comparison between the second mask layer and the first mask layer, wherein Figure 8 Displayed as Figure 7 The top view of the XY plane is shown.

[0069] Figure 9 Shown as Figure 7 The diagram shows a structure in which a second mask layer forms a second opening in the fin of the first fin region.

[0070] Figure 10 A schematic structural diagram showing a base region formed in the second opening is shown.

[0071] Figure 11 Shown as Figure 10 Schematic diagram of the structure in which an emitter region is formed above the base region.

[0072] Figure 12 It is a schematic diagram showing a structure in which an epitaxial cap layer is formed outside the base fin and the emitter region. Figure 12 It is shown as a cross-sectional view along the XZ plane as shown in 11.

[0073] Reference Signs List

[0074] 100 substrate 1071' first window

[0075] 101 bottom of fin 107' second mask layer

[0076] 102 fin 1072' second window

[0077] 1021 first fin 1071 first opening

[0078] 1022 Second fin 108 Base fin

[0079] 1023 third fin 1072 second opening

[0080] 103 first fin region 109 base region

[0081] 104 second fin region 110 emitter region

[0082] 105 well region, collector region 111 base region epitaxial cap

[0083] 106 Isolation structure 112 Emitter region epitaxial cap layer

[0084] 107 first mask layer DETAILED DESCRIPTION

[0085] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0086] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solution of this party, and the component layout form may also be more complicated.

[0087] Example 1

[0088] This embodiment provides a method for manufacturing a heterojunction bipolar transistor, such as Figure 1 As shown, the method includes the following steps:

[0089] Step S101: providing a substrate, forming a plurality of mutually parallel long strip fins on the substrate, and forming an isolation structure between adjacent fins, wherein the isolation structure is flush with the fins, the fins including a first fin region, and the first fin region including the plurality of fins;

[0090] The substrate of this embodiment can be selected according to the actual needs of the device, for example, it can include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon-on-insulator) substrate or a GOI (Germanium-on-Insulator) substrate, etc. Figure 2 As shown, in a preferred embodiment of this embodiment, the provided substrate 100 is a silicon substrate.

[0091] Still refer to Figure 2, forming a plurality of fins 102 on the substrate. In an optional embodiment, a SiN mask layer, for example, is first formed on the surface of the substrate, and then a photoresist layer is coated on the mask layer. The photoresist layer is exposed, developed, baked, and other steps are performed to form a patterned photoresist layer. The pattern of the photoresist layer is then transferred to the mask layer, and the substrate is etched under the action of the mask layer to form a plurality of mutually parallel long strip-shaped fins 102 on the substrate 100. The height of the fins 102 is approximately 10 to 100 nm, the top width is approximately 5 to 25 nm, and the fin length is greater than 10 nm. The plurality of fins 102 include a first fin region 103 for forming a heterojunction bipolar transistor. The first fin region 103 includes a plurality of fins 102. In this embodiment, as Figure 2 As shown, the first fin region 103 exemplarily includes three fins 102: a first fin 1021, a second fin 1022, and a third fin 1023. It should be understood that the number of fins 102 included in the first fin region 103 can be selected according to actual conditions and is not limited to the number shown in this embodiment.

[0092] like Figure 3 As shown, after forming the fins 102, isolation structures 106 are formed between the fins 102. This can be achieved by depositing an insulating material between the fins, such as silicon oxide, silicon nitride, etc. In this embodiment, the isolation structure 105 is silicon oxide.

[0093] Step S102: performing ion doping on the substrate to form a well region of the second conductivity type and a collector region in the substrate, wherein the well region corresponds to the first fin region;

[0094] Also refer to Figure 3 , after forming the isolation structure, the substrate is ion doped. In this embodiment, after depositing the insulating material to form the isolation structure 106, the substrate is ion doped using the insulating material formed above the fin as a mask to form a well region 105 in the substrate. In this embodiment, taking the formation of an npn-type heterojunction bipolar transistor as an example, the well region 105 formed in the substrate is an n-type well region, and the n-type well region forms the collector region 105 of the heterojunction bipolar transistor. The n-type well region 105 is also formed in the corresponding fin 102, at least at the bottom of the fin 102. As Figure 3 As shown, the n-type well region 105 corresponds to the first fin region 103 and is formed at least at the bottoms of the first fin 1021 , the second fin 1022 and the third fin 1023 corresponding to the first fin region 103 .

[0095] Step S103: removing a first portion of the fin in the first fin region to form a first opening;

[0096] Step S104: forming a first semiconductor material layer having a first conductivity type in the first opening to form a base fin, wherein the second conductive line type is opposite to the first conductivity type;

[0097] After forming the well region 105, Figure 4 As shown, a first mask layer 107 is first formed on the substrate, and a first window 1071' is formed on the first mask layer to expose the first part of the fin in the first fin region. Under the shielding of the first mask layer 107, the first part of the fin in the first fin region (such as the first fin 1021, the second fin 1022 and the third fin 1023 shown in this embodiment) is etched. Figure 5 As shown, a first opening 1071 is formed in the first portion of the fin in the first fin region. When etching the first portion of the fin in the first fin region, the bottom 101 of the fin connected to the well region 105 is retained (refer to FIG. Figure 3 ). Then, as Figure 6 As shown, a first semiconductor material layer is deposited in the first opening 1071 to form the base fin 108. In this embodiment, the first semiconductor material layer is a p-type material layer. Preferably, the first semiconductor material layer is C-doped SiGe. When forming the first semiconductor material layer, the first opening is first cleaned to remove impurities therein, and then p-type SiGe:C is selectively grown. The Ge content of the p-type SiGe:C is approximately 10-15%, and the C content is approximately 1-5%. The first material layer fills the entire first opening 1071 to form the base fin 108. The height of the base fin 108 is approximately 10-100 nm.

[0098] Step S105: removing a second portion of the fin in the first fin region to form a second opening;

[0099] Step S106: forming the first semiconductor material layer in the second opening, wherein the base fin formed in the first opening and the first semiconductor material layer formed in the second opening form a base region, and the thickness of the first semiconductor material layer is less than the height of the second opening;

[0100] After forming the base fin 108, as shown in FIG. Figure 7 As shown, a second mask layer 107' is formed above the substrate. The second mask layer 107' is formed with a second window 1072' exposing the remaining portion of the fins in the first fin region (such as the first fin 1021, the second fin 1022 and the third fin 1023 shown in this embodiment), that is, the second portion. The remaining portion of the fins in the first fin region is etched under the shielding of the second mask layer 107', as shown in FIG. Figure 8As shown, a second opening 1072 is formed. When etching the remaining portion of the fin in the first fin region, the bottom 101 of the fin connected to the well region 105 is also retained. In an alternative embodiment, since the base region and the emitter region are intended to form an emitter junction, as shown in FIG. Figure 7 As shown, the second mask layer 107' and the first mask layer 107 can slightly overlap, that is, the second window 1072' on the second mask layer 107' slightly overlaps the first window 1071' on the first mask layer 107. This ensures that the fins 102 are completely etched to prevent residual fins 102 from affecting subsequent device performance. It also ensures that the subsequently formed base region and base fin form a continuous structure, ensuring the electrical performance of the device.

[0101] Then, if Figure 9 As shown, a first semiconductor material layer is deposited in the second opening 1072. The first material layer partially fills the second opening 1072, that is, the thickness of the first material layer is less than the height of the second opening. The first semiconductor material layer filled in the second opening 1072 forms the base region 109. As described above, the first semiconductor material layer is a p-type material layer. Preferably, the first semiconductor material layer is C-doped SiGe. When forming the first semiconductor material layer, the second opening is first cleaned to remove impurities therein, and then p-type SiGe:C is selectively grown. The Ge content of the p-type SiGe:C is approximately 10-15%, and the C content is approximately 1-5%. The height of the base region 109 is approximately 10-100 nm.

[0102] Step S107: forming a second semiconductor material layer having a second conductivity type above the base region to form an emitter region.

[0103] After forming the base region 109, Figure 10 As shown, a second semiconductor material layer is deposited above the base region 109 to form an emitter region 110. In this embodiment, the second semiconductor material layer is n-type doped polysilicon, for example, As-doped polysilicon. The height of the emitter region is between 10 and 30 nm.

[0104] After forming the above-mentioned base fin, base region and emitter region, the isolation structure above the substrate is removed by etching to expose at least a portion of the base fin 108 and the emitter region 110. Figure 12 As shown, a base epitaxial cap layer 111 is formed outside the base fin, and the base epitaxial cap layer 111 connects the base fins together. The base epitaxial cap layer 111 is also p-type SiGe, such as B-doped SiGe. Then, a base (not shown in detail) connected to the base is formed above the base epitaxial cap layer. The base epitaxial cap layer can be formed simultaneously with the P-type source region and drain region of the MOS device. Also refer to Figure 12, an emitter epitaxial cap layer 112 connected to the emitter region 110 is formed on the outside of the emitter region 110, and the emitter epitaxial cap layer 112 connects the emitter regions together. The emitter epitaxial cap layer 112 is also n-type Si, such as As-doped polysilicon. Then, an emitter (not shown in detail) connected to the emitter region is formed above the emitter epitaxial cap layer 112. The emitter epitaxial cap layer can be formed simultaneously with the N-type source region and drain region of the MOS device. In addition, a collector (not shown in detail) connected to the well region (collector region) 105 in the substrate is formed above the substrate.

[0105] As described above, an npn heterojunction bipolar transistor is formed in the fin. The base width of this transistor can be defined by the epitaxial deposition thickness of p-type SiGe:C (i.e., base height) in the range of 10nm to 100nm. The Ge content for bandgap tuning ranges from 5% to 20% to improve emitter injection efficiency. To suppress the diffusion of boron in the epitaxial cap layer from the base fin to the emitter and collector regions, the C doping level in the base fin and base region is 1% to 5%.

[0106] Emitter-base junction area: The fin top width (5-25nm) and the total fin length (>10nm) define the total area of ​​the emitter-base junction. Because the emitter-base junction forms a vertical topology, the heterojunction bipolar transistor of this embodiment eliminates the emitter edge effect compared to traditional bipolar transistors.

[0107] Base-Collector Junction Area: The width and total length of the fin base define the total area of ​​the base-collector junction. The collector doping level can be independently adjusted by n-well doping.

[0108] In this embodiment, the step of forming a fin field effect transistor (Fin FET) is also included. For example, a gate oxide layer covering the fin 102 is first formed on the outside of the fin in the second fin region 1032, and then a replacement gate polysilicon is deposited and patterned to form a replacement polysilicon covering the channel region, and a spacer is formed on the sidewall of the replacement gate polysilicon. Under the action of the spacer layer, the fin is halo doped to form an n-type or p-type doped region. Then, epitaxial SiGe is formed on both sides of the replacement gate polysilicon, and in-situ doping or p-type heavy doping is performed to form a p-type source region and drain region. Alternatively, epitaxial Si is formed on both sides of the replacement gate polysilicon, and in-situ doping or n-type heavy doping is performed to form an n-type source region and drain region. The process of forming the n-type or p-type source region and drain region can simultaneously form the emitter region epitaxial cap layer and the base region epitaxial cap layer of the above-mentioned heterojunction bipolar transistor, thereby integrating the manufacturing process of the heterojunction bipolar transistor into the manufacturing process of the FinFET device, saving manufacturing steps and reducing manufacturing costs.

[0109] An interlayer dielectric layer is then deposited and planarized to expose the replacement gate polysilicon. The replacement gate polysilicon is then removed to form a gate opening. A high-k gate dielectric layer is deposited in the gate opening. A work function metal layer suitable for nMOS or pMOS devices is formed above the gate dielectric layer, followed by a gate metal layer. The source, drain, and gate electrodes are then formed.

[0110] This embodiment takes the formation of an npn-type heterojunction bipolar transistor as an example and describes in detail a method for forming a heterojunction bipolar transistor by using the fin replacement technology. It should be understood that this method is also applicable to forming a pnp-type heterojunction bipolar transistor.

[0111] The above method is easy to integrate into the FinFET technology platform and is easy to implement. The heterojunction bipolar transistor formed has good electrical properties.

[0112] Example 2

[0113] This embodiment provides a heterojunction bipolar transistor, also referring to Figures 1 to 12 , the heterojunction bipolar transistor comprises:

[0114] A substrate, with a plurality of parallel long strip fins formed on the substrate, the fins including a first fin region, and the first fin region including the plurality of fins;

[0115] The substrate 100 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon-on-insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. Figure 2 As shown, in a preferred embodiment of this embodiment, the substrate 100 is a silicon substrate.

[0116] a collector region formed in the substrate, the collector region corresponding to the first fin region;

[0117] forming a base fin in the first fin region;

[0118] A base region formed in the first fin region, the base region and the base fin forming a continuous structure;

[0119] An emitter region is formed above the base region.

[0120] like Figure 11 and Figure 12As shown, a well region 105 serving as a collector region is formed in the substrate 100. In this embodiment, the well region 105 is an n-type doped well region. The well region 105 corresponds to the first fin region 103 on the substrate 100. The first fin region 103 includes a plurality of fins. In this embodiment, the first fin 1021, the second fin 1022 and the third fin 1023 are illustrated as an example. In this embodiment, the base fin and the base region are formed of p-type SiGe, such as SiGe:C. The height of the base fin 108 is the height of the entire fin, which is between 10 and 100 nm. The height of the base region is less than the height of the fin (i.e., the base fin). The emitter region is formed above the base region. The height of the base region is between 10 and 100 nm, the height of the emitter region is between 10 and 30 nm, and the width of the emitter is between 5 and 25 nm. In this embodiment, the emitter region is formed of n-type polysilicon, such as As-doped polysilicon.

[0121] like Figure 12 As shown, a base epitaxial cap layer 111 is formed outside the base fin, and the base epitaxial cap layer 111 connects the base fins together. The base epitaxial cap layer 111 is also p-type SiGe, such as B-doped SiGe. A base fin is formed above the base epitaxial cap layer 111, thereby connecting the base of the base region. Figure 12 As shown, an emitter epitaxial cap layer 112 is formed outside the emitter region 110. This emitter epitaxial cap layer connects the emitter regions together. This emitter epitaxial cap layer 112 is also made of n-type Si, such as As-doped polysilicon Si. An emitter electrode connected to the emitter region 110 is formed above the emitter epitaxial cap layer. In addition, a collector electrode connected to the collector region (well region 105) is formed above the substrate.

[0122] As described above, an npn heterojunction bipolar transistor is formed in the fin. The base height of this transistor can be defined by the epitaxial deposition thickness of p-type SiGe:C (i.e., base height) ranging from 10nm to 100nm. The Ge content used for bandgap tuning ranges from 5% to 20% to improve emitter injection efficiency. To suppress the diffusion of boron from the epitaxial base cap layer from the base fin to the emitter and collector regions, the C doping level in the base fin and base region is 1% to 5%.

[0123] Emitter-base junction area: The fin top width (5-25nm) and the total fin length (>10nm) define the total area of ​​the emitter-base junction. Because the emitter-base junction forms a vertical topology, the heterojunction bipolar transistor of this embodiment eliminates the emitter edge effect compared to traditional bipolar transistors.

[0124] Base-Collector Junction Area: The width and total length of the fin base define the total area of ​​the base-collector junction. The collector doping level can be independently adjusted by n-well doping.

[0125] In addition, the heterojunction bipolar transistor further comprises a MOS device formed in a second fin region on the substrate, wherein the MOS device comprises an nMOS and / or pMOS device. The MOS device comprises a channel region formed in the middle region of the fin, and a source region and a drain region located on both sides of the channel region, a gate structure is formed on the outer layer of the channel region, and a source electrode and a drain electrode are formed on the outer sides of the source region and the drain region, respectively. The base epitaxial cap layer and the emitter epitaxial cap layer of the heterojunction bipolar transistor can be formed simultaneously with the p-type source region and the drain region and the n-type source region and the drain region, respectively, thereby simplifying the device formation process, making the heterojunction bipolar transistor easy to integrate with the FinFET, and the integrated device has excellent electrical performance.

[0126] This embodiment is also described using an npn-type heterojunction bipolar transistor. It should be understood that the heterojunction bipolar transistor may also be a pnp-type heterojunction bipolar transistor.

[0127] As described above, the heterojunction bipolar transistor and the manufacturing method thereof provided by the present invention have at least the following beneficial technical effects:

[0128] The present invention utilizes fin replacement technology to fabricate heterojunction bipolar transistors. A fin structure is formed on a substrate, and a well region serving as the collector region is formed in the substrate. The bottom of the fin is connected to the well region serving as the collector. Base material is deposited in the first portion of the fin to form a base fin. In the second portion of the fin, base material is first deposited to form the base region, and then a different material is deposited above the base region to serve as the emitter region. A base epitaxial cap layer is formed outside the base fin, and an emitter epitaxial cap layer is formed outside the emitter region. For example, in an npn heterojunction transistor, the well region in the substrate is an n-type doped well region, the base material is C-doped p-type SiGe, and the emitter material is As-doped n-type polysilicon Si. The emitter, base, and collector contacts can all be on the surface. This method is simple, and the base epitaxial cap layer and emitter epitaxial cap layer can be formed simultaneously with the p-type source and drain regions and the n-type source and drain regions, respectively. This method is easily integrated into FinFET technology platforms. The technology of this application realizes the formation of 14nm and the most advanced heterojunction based on FinFET technology, filling the gap of integrating SiGe HBT on FinFET platforms of 14nm and above.

[0129] The heterojunction bipolar transistor formed by the above method has small equivalent base and collector resistances, low leakage current, and excellent electrical performance. It is also easy to integrate with FinFET devices, thereby improving the integration of the devices.

[0130] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a heterojunction bipolar transistor, characterized in that: The steps include: Providing a substrate, forming a plurality of mutually parallel long strip-shaped fins on the substrate, and forming an isolation structure between adjacent fins, wherein the isolation structure is flush with the fins, the fins including a first fin region, the first fin region including the plurality of fins, and the fins being divided into a first portion and a second portion along a length direction; Performing ion doping on the substrate to form a well region having a second conductivity type in the substrate to form a collector region, wherein the well region corresponds to the first fin region; removing a first portion of the fin in the first fin region to form a first opening; forming a first semiconductor material layer having a first conductivity type in the first opening to form a base fin, wherein the second conductivity type is opposite to the first conductivity type; removing a second portion of the fin in the first fin region to form a second opening; forming the first semiconductor material layer in the second opening, wherein the first semiconductor material layer in the second opening forms a base region, and a thickness of the first semiconductor material layer in the second opening is less than a height of the second opening; A second semiconductor material layer having a second conductivity type is formed in the second opening above the base region to form an emitter region.

2. The manufacturing method according to claim 1, characterized in that forming a first semiconductor material layer having a first conductivity type in the first opening to form a base fin, further comprising the following steps: cleaning the bottom and side walls of the first opening; selectively epitaxially growing P-type SiGe in the first opening; The height of the base fin is the same as that of the first opening.

3. The manufacturing method according to claim 2, characterized in that Forming the base region and the emitter region further comprises the following steps: cleaning the bottom and side walls of the second opening; selectively epitaxially growing P-type SiGe in the second opening; N-type doped polysilicon is formed on the P-type SiGe.

4. The manufacturing method according to claim 2 or 3, characterized in that: The P-type SiGe is C-doped SiGe.

5. The manufacturing method according to claim 3, characterized in that The N-type doped polysilicon is As-doped polysilicon.

6. The manufacturing method according to claim 1, characterized in that The following steps are also included: removing the isolation structure to expose at least a portion of the base fin and a portion of the emitter region; forming a base region epitaxial cap layer outside the base fin, wherein the epitaxial cap layer is connected to the base fin; An emitter region epitaxial cap layer is formed outside the emitter region, and the emitter region epitaxial cap layer is connected to the emitter region.

7. The manufacturing method according to claim 1, characterized in that The base region epitaxial capping layer is P-type SiGe, and the emitter region epitaxial capping layer is n-type polysilicon.

8. The manufacturing method according to claim 6, characterized in that Also includes: forming a base electrode above the base epitaxial cap layer; forming an emitter electrode above the emitter region epitaxial cap layer; A collector electrode is formed above the substrate.

9. The manufacturing method according to claim 1, characterized in that The fin further includes a second fin region, and the manufacturing method further includes the following steps: forming a replacement gate stack in the channel region of the fin in the second fin region; forming a source region and a drain region at both ends of the channel region; removing the replacement gate stack to form a gate opening exposing the channel region; A gate structure is formed in the gate opening.

10. The manufacturing method according to claim 1, characterized in that the second opening portion being formed in the base fin; The sum of the thicknesses of the emitter region and the base region is the same as the height of the second opening.

11. A heterojunction bipolar transistor, characterized in that: include: A substrate, with a plurality of parallel long strip fins formed on the substrate, the fins including a first fin region, and the first fin region including the plurality of fins; a collector region formed in the substrate, the collector region corresponding to the first fin region; a base fin formed on one side of the first fin region along the length direction of the fin; A base region is formed on the other side of the first fin region along the length direction of the fin, wherein the base region on the same fin forms a continuous structure with the base fin, and the height of the base region is smaller than the height of the base fin, and along the length direction of the fin, the side surface of the base region on the same fin contacts the side surface of the base fin; An emitter region is formed above the base region, and along the length direction of the fin, a side surface of the emitter region on the same fin contacts a side surface of the base fin.

12. The heterojunction bipolar transistor according to claim 11, wherein: The base fin and the base region are made of P-type GeSi.

13. The heterojunction bipolar transistor according to claim 11 or 12, characterized in that: The base fin and the base region are made of C-doped SiGe.

14. The heterojunction bipolar transistor according to claim 11, wherein: The material of the emitter region is N-type doped polysilicon.

15. The heterojunction bipolar transistor according to claim 11 or 14, characterized in that: The material of the emitter region is As-doped polysilicon.

16. The heterojunction bipolar transistor according to claim 11, wherein: Also includes: A base epitaxial cap layer is formed outside the base fin, wherein the base epitaxial cap layer is connected to the base fin; An emitter region epitaxial cap layer is formed outside the emitter region, and the emitter region epitaxial cap layer is connected to the emitter region.

17. The heterojunction bipolar transistor according to claim 16, wherein: Also includes: a base electrode formed above the base epitaxial cap layer; an emitter electrode formed above the epitaxial cap layer of the emitter region; A collector electrode is formed above the substrate.

18. The heterojunction bipolar transistor according to claim 11, wherein: The fin further includes a second fin region, wherein a MOS device is formed in the second fin region, and the MOS device includes: A source region and a drain region formed at both ends of the fin in the second fin region, and a channel region located between the source region and the drain region; A gate structure is formed around the channel region.

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