Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a mark region and a device region; performing ion implantation on a portion of the substrate in the mark region to form a zero-layer alignment mark in the mark region, wherein the top surface of the zero-layer alignment mark is flush with the top surface of the substrate in the device region. The method for forming a semiconductor structure provided in an embodiment of the present invention can form a zero-layer alignment mark whose top surface is flush with the top surface of the substrate, providing a flat process platform for subsequent semiconductor device formation processes, and facilitating improved performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Photolithography is a key process in semiconductor integrated circuit manufacturing, used to transfer the pattern on the mask onto the wafer surface. However, as the feature size of semiconductor devices continues to decrease and the integration density continues to increase, the precision requirements of the photolithography process are also increasing. In the semiconductor manufacturing process, in order to accurately transfer the pattern on the mask to the wafer surface, wafer alignment must be performed before each photoresist exposure.

[0003] Currently, most methods of using alignment marks for photolithography alignment are to etch a zero-layer mark groove in the semiconductor substrate. The bottom of the groove has a certain step height difference with the top surface of the substrate. During photolithography alignment, the exposure equipment provides a light source to illuminate the entire semiconductor substrate. The diffraction pattern generated by the light projected on the zero-layer mark is received by the alignment sensor of the exposure equipment. The bottom of the groove has a certain step height difference with the top surface of the substrate. The intensities of the diffracted light generated by the groove and the top surface of the substrate are different. The exposure equipment identifies the zero-layer mark by judging the change in the intensity of the diffracted light or the change boundary of the diffracted light intensity, thereby completing the photolithography alignment process.

[0004] However, in the semiconductor manufacturing process, due to the existence of the zero-layer marking groove, the substrate surface is uneven. When structures such as fins are subsequently formed on the semiconductor substrate, it is easy for residues of sidewalls or other material layers to remain in the groove, seriously affecting the performance of the final semiconductor structure. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can form a zero-layer alignment mark whose top surface is flush with the top surface of the substrate, providing a flat process platform for the subsequent fin formation process, which is conducive to improving the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a marking area and a device area; a zero-layer alignment mark, located in the substrate in the marking area, and the top surface of the zero-layer alignment mark is flush with the top surface of the substrate in the device area.

[0007] Optionally, the zero-layer alignment mark is a damaged layer, and the damaged layer has first doping ions.

[0008] Optionally, the first doping ions include one or more combinations of P ions, Si ions or Ar ions.

[0009] Optionally, the zero-layer alignment mark is a modified layer, and the modified layer has second doping ions.

[0010] Optionally, the second doping ions include N ions or O ions, or a combination of both.

[0011] Correspondingly, an embodiment of the present invention also provides a method for forming the above-mentioned semiconductor structure, including: providing a substrate, the substrate including a marking area and a device area; performing ion implantation on a portion of the substrate in the marking area to form a zero-layer alignment mark in the marking area, and the top surface of the zero-layer alignment mark is flush with the top surface of the substrate in the device area.

[0012] Optionally, first doping ions are implanted into the substrate in a portion of the mark area to form a damaged layer, and the damaged layer serves as a zero-layer alignment mark.

[0013] Optionally, the first doping ions include one or more combinations of P ions, Si ions or Ar ions.

[0014] Optionally, second doping ions are implanted into the substrate in a portion of the mark area to form a modified layer, and the modified layer serves as a zero-layer alignment mark.

[0015] Optionally, the second doping ions include N ions or O ions, or a combination of both.

[0016] Optionally, the process parameters of the ion implantation include: an ion implantation dose of 1E10 to 1E20 atoms / cm 2 , the injection energy is 10~400KeV.

[0017] Optionally, before forming the zero-layer alignment mark, the method further includes: forming a first mask layer on the surface of the substrate, wherein the first mask layer has an opening, and the opening exposes a portion of the substrate surface in the mark area.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] The formation method provided by the embodiment of the present invention forms a zero-layer alignment mark by injecting ions into the substrate in the mark area. On the one hand, the reflectivity of the substrate to light after the ion injection changes, which is different from the reflectivity of the substrate to light without the ion injection. During the photolithography alignment process, the light emitted by the exposure equipment is irradiated on the entire substrate, and the reflection signal intensity of the light in the ion injection area and the non-ion injection area is different, thereby completing the photolithography alignment process; on the other hand, the ion injection does not cause a change in the height of the substrate surface, and the top surface of the formed zero-layer alignment mark is flush with the top surfaces of other areas, which is better suitable for self-aligned multiple patterning processes. In the subsequent process of forming fins on the substrate, various material layers will not be formed in the grooves, and will not remain in the grooves after etching, thereby eliminating the source of defects and being able to obtain fins with consistent morphology, which is beneficial to improving the performance of the semiconductor structure.

[0020] In the semiconductor structure provided by the embodiment of the present invention, on the one hand, the zero-layer alignment mark can provide an alignment reference for the subsequent photolithography alignment process; on the other hand, the top surface of the zero-layer alignment mark is flush with the top surface of the substrate in the device area, providing a good and flat process platform for subsequent processes, improving the adaptability to the self-aligned multiple patterning process, and being beneficial to the performance of the finally formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 7 is a structural schematic diagram of a semiconductor structure forming process in one embodiment;

[0022] Figures 8 to 18 Schematic diagram of the structures corresponding to each step of the semiconductor structure formation process in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] As known from the background art, the current method for forming a zero-layer alignment mark is to form a zero-layer mark groove in the substrate, which serves as an alignment mark in the subsequent photolithography process. However, the zero-layer mark groove will result in poor performance in forming the fin.

[0024] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 7 A structural schematic diagram of a semiconductor structure forming process in one embodiment is shown.

[0025] refer to Figure 1 , providing a substrate 10, the substrate 10 including a marking area 11 and a device area 12; forming a patterned photoresist layer 13 on the substrate 10, the opening of the patterned photoresist layer 13 exposing the surface of the substrate 10 where the zero-layer marking groove is to be formed in the marking area 11.

[0026] refer to Figure 2, using the patterned photoresist layer 13 as a mask to etch the substrate 10 in the mark area 11 to form a zero-layer mark groove 14, the zero-layer mark groove 14 serves as an alignment mark for subsequent photolithography alignment; and removing the patterned photoresist layer 13.

[0027] refer to Figure 3 A hard mask layer 15, a core layer 16, a sacrificial layer 17 and a mask layer are sequentially formed on the bottom and sidewall surfaces of the substrate 10 and the zero-layer mark groove 14, and the mask layer includes a first mask layer 18 located on the zero-layer mark groove 14 of the mark area 11, and a second mask layer 19 separately arranged on the substrate 10 of the device area 12.

[0028] refer to Figure 4 , using the mask layer as a mask, etching the sacrificial layer 17 and the core layer 16 until the surface of the hard mask layer 15 is exposed, forming a first core layer pattern 21 with grooves in the mark area 11, and forming a discretely arranged second core layer pattern 22 in the device area 12; removing the mask layer and the sacrificial layer 17; forming a spacer material layer 23 on the sidewalls and top surfaces of the first core layer pattern 21 and the second core layer pattern 22.

[0029] refer to Figure 5 The sidewall material layer 23 on the surface of the hard mask layer 15 and the top surfaces of the first core layer pattern 21 and the second core layer pattern 22 is removed by etching, and sidewalls 24 are formed on the sidewall surfaces of the first core layer pattern 21 and the second core layer pattern 22.

[0030] refer to Figure 6 , remove the first core layer pattern 21 and the second core layer pattern 22.

[0031] refer to Figure 7 , using the sidewall spacer 24 as a mask, the hard mask layer 15 and the substrate 10 are etched to form a fin 25 on the substrate 10 .

[0032] The inventors discovered that when using the zero-layer mark groove 14 as an alignment mark, there is a certain step height difference between the zero-layer mark groove 14 and other areas of the substrate 10 surface. In the subsequent process of forming the fin 25 on the substrate 10 using a self-aligned multi-patterning process, it is necessary to deposit multiple material layers, such as a hard mask layer 15, a core layer 16, and a sacrificial layer 17. These material layers will grow along the sidewalls and bottom surface of the zero-layer mark groove 14 until the entire zero-layer mark groove is filled. However, when etching the above material layers and the substrate 10 to form the fin 25, since the various material layers grow on the sidewalls and bottom of the zero-layer mark groove 14, they are likely to remain in the zero-layer mark groove 14 after etching. In subsequent processes such as wet cleaning, the residue remaining in the zero-layer mark groove 14 will flow out of the groove with the wet cleaning liquid, becoming a source of defects on the wafer surface, thereby seriously affecting the performance of the formed semiconductor structure.

[0033] If the zero-layer mark groove 14 is filled and the top surface of the zero-layer mark groove 14 is smoothed by chemical mechanical polishing before etching to form the fin, on the one hand, the complexity of the process is increased and the production cost is increased; on the other hand, the chemical mechanical polishing process cannot completely guarantee the consistency of the flatness of the top surface, and the size of the fins finally formed will still be different.

[0034] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, in which ion implantation is performed on a substrate in an area where a zero-layer alignment mark is to be formed, and the substrate with implanted ions is used as a zero-layer alignment mark. On the one hand, by implanting ions into the substrate, the reflectivity of the substrate in this area is changed, which is different from the reflectivity of other substrates without ion implantation. In the subsequent photolithography process, the exposure equipment can still complete the photolithography alignment process by judging the difference in the reflection signal intensity between the ion implantation area and the non-ion implantation area; on the other hand, ion implantation into the substrate does not change the surface height of the substrate, and the top surface of the formed zero-layer alignment mark is flush with the top surface of the substrate in the device area. When the substrate is subsequently etched to form a fin, it has better adaptability to the self-aligned multiple patterning process, eliminates the source of wafer surface defects, and is beneficial to improving the performance of the semiconductor structure.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 8 to 18 It is a structural schematic diagram corresponding to each step of the semiconductor structure formation process in one embodiment of the present invention.

[0037] refer to Figure 8 , providing a substrate 100, wherein the substrate 100 includes a marking region I and a device region II.

[0038] In this embodiment, a zero-layer alignment mark is subsequently formed in the mark area I.

[0039] In this embodiment, the substrate 100 is made of silicon.

[0040] In other embodiments, the material of the substrate 100 may also be semiconductor materials such as germanium, silicon germanium, gallium arsenide, indium arsenide, silicon on insulator (SOI), and germanium on insulator (GOI).

[0041] A zero-layer alignment mark is formed in the substrate 100 .

[0042] In this embodiment, the step of forming the zero layer alignment mark includes:

[0043] refer to Figure 8 , forming an initial mask layer (not shown) covering the surface of the substrate 100; patterning the initial mask layer to form a first mask layer 101, wherein the first mask layer 101 has an opening 102, and the opening 102 exposes a portion of the surface of the substrate 100 in the marking area I.

[0044] In this embodiment, the opening 102 exposes the surface of the substrate 100 where the zero-layer alignment mark is to be formed.

[0045] In this embodiment, the first mask layer 101 is a photoresist layer; in other embodiments, the first mask layer 101 may also be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride or boron nitride.

[0046] After forming the first mask layer 101, ion implantation is performed on a portion of the substrate 100 in the mark area I to form a zero-layer alignment mark in the substrate 100 in the mark area I, and the top surface of the zero-layer alignment mark is flush with the top surface of the substrate 100 in the device area II.

[0047] In this embodiment, ion implantation is specifically performed on the substrate 100 in the marking area I exposed by the opening 102 of the first mask layer 101 .

[0048] Ion implantation is performed on part of the substrate 100 in the mark area I, which can change the reflectivity of the substrate 100 to light after the ion implantation. During the subsequent photolithography alignment, the exposure equipment provides a light source to illuminate the entire semiconductor substrate. The substrate 100 after ion implantation and the substrate 100 without ion implantation have different reflection signal intensities to light. The exposure equipment identifies the zero-layer alignment mark by judging the change in the intensity of the diffracted light or the change boundary of the intensity of the diffracted light, thereby completing the photolithography alignment process.

[0049] The process parameters of the ion implantation include: ion implantation dose of 1E10-1E20 atoms / cm 2 The implantation energy is 10 to 400 KeV. By controlling the energy and dose of the ion implantation, the depth and reflectivity of the zero-layer alignment mark can be controlled, and the ratio of the reflectivity of the zero-layer alignment mark to the reflectivity of other areas of the substrate 100 can be controlled to be greater than 1:1.5.

[0050] If the ion implantation dose is too small, the reflectivity of the zero-layer alignment mark formed cannot meet the above conditions, resulting in the inability to complete the photolithography alignment process; if the ion implantation dose is too large, the doping ion concentration of the zero-layer alignment mark formed is too high, and in the subsequent high-temperature process, the doping ions are likely to diffuse far, affecting the performance of the semiconductor structure in the device area. Therefore, in this embodiment, the ion implantation dose is 1E10~1E20 atoms / cm 2 .

[0051] If the ion implantation energy is too low, a zero-layer alignment mark with the required reflectivity cannot be formed. If the ion implantation energy is too high, the substrate will be severely damaged during the implantation process, causing the substrate surface height to change, making it impossible to form a zero-layer alignment mark with a top surface flush with the substrate. Therefore, in this embodiment, the ion implantation energy is 10 to 400 KeV.

[0052] refer to Figure 9 In this embodiment, first doping ions are implanted into a portion of the substrate 100 in the mark region I to form a damaged layer 110 , and the damaged layer 110 serves as a zero-layer alignment mark.

[0053] The first doping ion includes one or more combinations of P ions, Si ions, or Ar ions. In this embodiment, the first doping ion is P ions, and the ion implantation dose is 1E14 to 2E16 atoms / cm 2 , the injection energy is 20~80KeV.

[0054] In other embodiments, when the first doping ion is Si ion, the ion implantation dose is 1E15 to 1E17 atoms / cm 2 , the implantation energy is 100-200 KeV; when the first doping ion is Ar ion, the ion implantation dose is 1E10-1E15 atoms / cm 2 , the injection energy is 50~100KeV.

[0055] In this embodiment, by injecting first doping ions, the first doping ions bombard the substrate 100 in the mark area I. The first doping ions collide with the lattice atoms in the substrate 100, causing atomic displacement, resulting in a large number of defects, and forming a damaged layer 110 in the substrate 100 in the mark area I. The reflectivity of the damaged layer 110 to light is different from the reflectivity of the substrate 100 without ion injection, so that the damaged layer 110 can be used as an alignment mark.

[0056] In another embodiment, reference Figure 10 , second doping ions are implanted into the substrate 100 in a portion of the mark area I to form a modified layer 120, and the modified layer 120 serves as a zero-layer alignment mark.

[0057] The second doping ions include O ions or N ions, or a combination of both.

[0058] When the second doping ion is O ion, the ion implantation dose is 1E15-1E18 atoms / cm 2 , the injection energy is 20~60KeV.

[0059] When the second doping ion is N ion, the ion implantation dose is 1E17-1E19 atoms / cm 2 , the injection energy is 150~400KeV.

[0060] In this embodiment, second dopant ions are implanted, reacting with the substrate 100 in the marking region I to form a modified layer 120 within the substrate 100 in the marking region I. When the second dopant ions are O ions, the modified layer 120 is silicon oxide; when the second dopant ions are N ions, the modified layer 120 is silicon nitride. The reflectivity of the modified layer 120 differs from that of the substrate 100 without ion implantation, allowing the modified layer 120 to serve as an alignment mark.

[0061] refer to Figure 11 In this embodiment, after forming the zero-layer alignment mark, the first mask layer 101 is removed.

[0062] After forming the zero-layer alignment mark, the method further includes forming a plurality of discretely arranged fins on the substrate 100 in the mark area I and the device area II.

[0063] In this embodiment, the fin is formed by a self-aligned double patterning process; in other embodiments, the fin may be formed by a self-aligned multiple patterning process to obtain a fin with a smaller line width.

[0064] In this embodiment, the steps of forming the fins specifically include:

[0065] refer to Figure 12 A hard mask layer 201, an initial core layer 202, a sacrificial layer 203, an anti-reflection layer 204 and an initial second mask layer 205 are sequentially formed on the surface of the substrate 100 in the zero-layer alignment mark, the mark area I and the device area II.

[0066] In this embodiment, the material of the hard mask layer 201 is silicon oxide; in other embodiments, the material of the hard mask layer 201 may also be one or more of silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbonitride oxide.

[0067] In this embodiment, the hard mask layer 201 is formed by chemical vapor deposition. In other embodiments, the hard mask layer 201 may be formed by atomic layer deposition.

[0068] In this embodiment, the hard mask layer 201 is a single-layer structure; in other embodiments, the hard mask layer 201 may also be a stacked-layer structure.

[0069] In this embodiment, the initial core layer 202 is amorphous silicon; in other embodiments, the material of the initial core layer 202 may also be silicon dioxide, silicon nitride, or silicon carbide.

[0070] The material of the initial core layer 202 is different from that of the hard mask layer 201 , so that the hard mask layer 201 will not be damaged when the initial core layer 202 is subsequently etched.

[0071] In this embodiment, the initial core layer 202 is formed by chemical vapor deposition. In other embodiments, the initial core layer 202 may be formed by atomic layer deposition.

[0072] In this embodiment, the material of the sacrificial layer 203 is a carbon-containing compound.

[0073] In this embodiment, the sacrificial layer 203 is formed by spin coating. In other embodiments, the sacrificial layer 203 may be formed by chemical vapor deposition.

[0074] In this embodiment, the material of the anti-reflection layer 204 is silicon oxynitride; in other embodiments, the anti-reflection layer 204 may also be silicon oxide.

[0075] In this embodiment, the anti-reflection layer 204 is formed by chemical vapor deposition. In other embodiments, the anti-reflection layer may be formed by physical vapor deposition or the like.

[0076] In this embodiment, the initial second mask layer 205 is a photoresist layer; in other embodiments, the initial second mask layer 205 may also be one or more of silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride or silicon carbonitride oxynitride.

[0077] In this embodiment, the method for forming the initial second mask layer 205 is chemical vapor deposition; in other embodiments, the initial second mask layer 205 may also be formed by atomic layer deposition.

[0078] refer to Figure 13 , patterning the initial second mask layer 205, forming a third mask layer 206 in the mark area I, and forming a fourth mask layer 207 in the device area II, the third mask layer 206 covers the surface of the zero-layer alignment mark in the mark area I, and the fourth mask layer 207 is separately arranged on the surface of the substrate 100 in the device area II.

[0079] In this embodiment, the third mask layer 206 covers the surface of the zero-layer alignment mark, and can protect the zero-layer alignment mark from being damaged in a subsequent etching process.

[0080] The boundary of the third mask layer 206 may just cover the boundary of the zero-layer alignment mark, or may be larger than the boundary of the zero-layer alignment mark.

[0081] In this embodiment, the fourth mask layer 207 is used to define the spacing distance of the fins subsequently formed in the device region II.

[0082] refer to Figure 14 , using the third mask layer 206 and the fourth mask layer 207 as masks, etching the anti-reflection layer 204, the sacrificial layer 203 and the initial core layer 202 until the surface of the hard mask layer 201 is exposed to form a core layer 210; removing the third mask layer 206, the fourth mask layer 207, the anti-reflection layer 204 and the sacrificial layer 203.

[0083] In this embodiment, the core layer 210 includes a first core layer 211 and a second core layer 212. The first core layer 211 covers the surface of the zero-layer alignment mark in the mark area I, and the second core layer 212 is separately arranged on the surface of the substrate 100 in the device area II.

[0084] refer to Figure 15 In the core layer 210 (reference Figure 14 ) sidewalls and top surfaces, and surfaces of the substrate 100 in the marking area I and the device area II form a spacer material layer 220.

[0085] In this embodiment, a spacer material layer 220 is formed on the sidewalls and top surfaces of the first core layer 211 and the second core layer 212 and on the surface of the substrate 100 in the marking area I and the device area II.

[0086] In this embodiment, the material of the spacer material layer 220 is silicon nitride; in other embodiments, the material of the spacer material layer 220 may also be silicon oxynitride or silicon carbide.

[0087] In this embodiment, the spacer material layer 220 is formed by atomic layer deposition, so that the formed spacer material layer 220 has better uniformity and a smoother surface.

[0088] In other embodiments, the spacer material layer 220 may be formed by chemical vapor deposition.

[0089] refer to Figure 16 , remove the spacer material layer 220 on the top surface of the core layer 210 and the surface of the substrate 100 in the marking area I and the device area II, and form a spacer 221 on the sidewall surface of the core layer 210; remove the core layer 210.

[0090] In this embodiment, a dry etching process is used to remove the spacer material layer 220 on the top surface of the core layer 210 and the surface of the substrate 100 .

[0091] In this embodiment, a dry etching process is used to remove the core layer 210 ; in other embodiments, a wet etching process may also be used to remove the core layer 210 .

[0092] refer to Figure 17 Using the sidewall 221 as a mask, the hard mask layer 201, the zero-layer alignment mark, and the substrate 100 in the mark area I and the device area II are etched to form a fin 230 on the substrate 100 in the mark area I and the device area II.

[0093] In this embodiment, specifically, the hard mask layer 201 is etched using the sidewall 221 as a mask to form a discretely arranged patterned hard mask layer 208; the sidewall 221 is removed; and the zero-layer alignment mark and the substrate 100 are etched using the patterned hard mask layer 208 as a mask to form a fin 230.

[0094] refer to Figure 18 In this embodiment, after forming the fin 230 , the method further includes: removing the remaining zero-layer alignment mark.

[0095] In other embodiments, the remaining zero-layer alignment mark may not be removed.

[0096] In this embodiment, after the fins 230 are formed, the method further includes: forming an isolation layer (not shown) on the substrate 100 between adjacent fins 230 .

[0097] In an embodiment of the present invention, ion implantation is used to form a zero-layer alignment mark in the substrate 100 of the mark area I, so that the top surface of the zero-layer alignment mark is flush with the top surface of the substrate of the device area II. On the one hand, the reflectivity of the substrate to light changes after ion implantation, which is different from the reflectivity of other substrates that have not been implanted with ions, so that the ion-implanted area can be used as a zero-layer alignment mark to complete the lithography alignment; on the other hand, ion implantation does not change the surface height of the substrate, and the surface of the formed zero-layer alignment mark is flush with the surface of the substrate in other areas, which improves the adaptability to the self-aligned multiple patterning process. When the fin is subsequently formed on the substrate, since the process platform is flat, no other material layers will remain in the groove, thereby eliminating the source of defects and improving the performance of the semiconductor structure. There is no need to fill the groove and perform chemical mechanical polishing, which can simplify the process flow and reduce process costs.

[0098] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned formation method.

[0099] refer to Figure 9 The semiconductor structure includes: a substrate 100, the substrate 100 including a mark area I and a device area II; a zero-layer alignment mark, located in the substrate 100 in the mark area I, and the top surface of the zero-layer alignment mark is flush with the top surface of the substrate 100 in the device area II.

[0100] In this embodiment, the zero-layer alignment mark is a damaged layer 110 , and the damaged layer 110 has first doping ions.

[0101] The first doping ions include one or more combinations of P ions, Si ions, and Ar ions.

[0102] refer to Figure 10 In another embodiment, the zero-layer alignment mark is a modified layer 120 , and the modified layer 120 has second doping ions.

[0103] The second doping ions include one or a combination of O ions and N ions.

[0104] The semiconductor structure provided by the embodiment of the present invention has a top surface of the zero-layer alignment mark formed that is flush with the top surface of the substrate 100 in other areas, providing a flat process platform for subsequent lithography processes, improving adaptability to self-aligned multiple patterning processes, and facilitating the performance of subsequently formed semiconductor devices.

[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a marking region and a device region; a zero-layer alignment mark, located in the substrate of the mark area, with a top surface of the zero-layer alignment mark flush with a top surface of the substrate of the device area, and the zero-layer alignment mark is formed by ion implantation into a portion of the substrate of the mark area; A fin portion, wherein the fin portion is located on the substrate in the mark area and the device area, the fin portion located in the mark area is located on both sides of the zero-layer alignment mark, the sidewalls of the fin portion are aligned with the boundaries of the zero-layer alignment mark, and the bottom surface of the fin portion is higher than the bottom surface of the zero-layer alignment mark.

2. The semiconductor structure according to claim 1, wherein The zero layer alignment mark is a damaged layer, and the damaged layer has first doping ions, wherein the first doping ions include one or more combinations of P ions, Si ions, or Ar ions.

3. The semiconductor structure according to claim 1, wherein: The zero-layer alignment mark is a modified layer, and the modified layer has second doping ions, wherein the second doping ions include one of N ions and O ions, or a combination of both.

4. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a marking area and a device area; Performing ion implantation on a portion of the substrate in the mark area to form a zero-layer alignment mark in the mark area, wherein a top surface of the zero-layer alignment mark is flush with a top surface of the substrate in the device area; forming a hard mask layer on the substrate surface of the zero-layer alignment mark, the mark area, and the device area; forming a core layer on the hard mask layer, the core layer comprising a first core layer and a second core layer, the first core layer just covering the boundary of the zero-layer alignment mark in the mark area, and the second core layer being discretely arranged on the surface of the substrate in the device area; forming sidewalls on the sidewall surfaces of the core layer; removing the core layer; Using the side wall as a mask, the hard mask layer, the zero-layer alignment mark, and the substrate in the mark area and the device area are etched to form fins on the substrate in the mark area and the device area. The fins in the mark area are located on both sides of the zero-layer alignment mark, and the sidewalls of the fins are aligned with the boundaries of the zero-layer alignment mark. The bottom surface of the fins is higher than the bottom surface of the zero-layer alignment mark.

5. The method for forming a semiconductor structure according to claim 4, wherein: First doping ions are implanted into the substrate in a portion of the mark area to form a damaged layer, and the damaged layer serves as a zero layer alignment mark. The first doping ions include one or more combinations of P ions, Si ions or Ar ions.

6. The method for forming a semiconductor structure according to claim 4, wherein: Second doping ions are implanted into the substrate in a portion of the mark area to form a modified layer, which serves as a zero-layer alignment mark. The second doping ions include N ions or O ions, or a combination of both.

7. The method for forming a semiconductor structure according to claim 4, wherein: The process parameters of the ion implantation include: ion implantation dose of 1E10~1E20 atoms / cm 2 , the injection energy is 10~400KeV.

8. The method for forming a semiconductor structure according to claim 4, wherein: Before forming the zero-layer alignment mark, the method further includes: forming a first mask layer on the surface of the substrate, wherein the first mask layer has an opening, and the opening exposes a portion of the substrate surface of the mark area.

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