Semiconductor die with decoupling capacitor

Abstract

The present disclosure provides a semiconductor die with decoupling capacitors. The semiconductor die includes a plurality of first bonding pads, a plurality of second bonding pads, a plurality of bonding metals, and a plurality of decoupling capacitors. The plurality of first and second bonding pads are coupled to a power supply voltage and a reference voltage, respectively. The plurality of bonding metals are disposed on a plurality of central regions of the plurality of first and second bonding pads. The plurality of decoupling capacitors are disposed under the plurality of first and second bonding pads and overlap a plurality of peripheral regions of the plurality of first and second bonding pads. The plurality of decoupling capacitors are connected in parallel. First endpoints of the plurality of decoupling capacitors are electrically connected to the plurality of first bonding pads, and second endpoints of the plurality of decoupling capacitors are electrically connected to the plurality of second bonding pads.

Description

[0001] This invention claims priority and benefits to U.S. Patent Application No. 17 / 031,477, filed on September 24, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a semiconductor die and a method for manufacturing the same. More particularly, it relates to a semiconductor die with a decoupling capacitor and a method for manufacturing the same. Background Technology

[0003] The semiconductor industry has experienced rapid growth over the past few decades. In addition to advancements in materials and process technologies, progress in integrated circuits over the decades has included continuously shrinking feature sizes and the use of higher clock pulse frequencies. The use of higher clock pulse frequencies has brought about problems such as power supply oscillation, which can lead to noise generated and propagated within the chip.

[0004] For example, the charge stored in dynamic random access memory (DRAM) may change due to power supply fluctuations, causing read errors. Furthermore, these problems become more severe when the operating voltage of DRAM is reduced due to the use of portable electronic products and / or communication devices (e.g., to 1.0V or lower).

[0005] The above description of "prior art" is merely a background description and does not acknowledge that the subject matter of this disclosure is disclosed. It does not constitute prior art in this disclosure, and no description of the above "prior art" should be considered part of this invention. Summary of the Invention

[0006] The purpose of this disclosure is to provide a semiconductor die with a decoupling capacitor to solve at least one of the above-mentioned problems.

[0007] One aspect of this disclosure provides a semiconductor die, including a memory array disposed within a cell region of the semiconductor die; a plurality of first bonding pads and a plurality of second bonding pads disposed within an input / output region of the semiconductor die, wherein the plurality of first bonding pads are coupled to a power supply voltage and the plurality of second bonding pads are coupled to a reference voltage; a plurality of decoupling capacitors disposed below the plurality of first bonding pads and the plurality of second bonding pads and connected in parallel between the plurality of first bonding pads and the plurality of second bonding pads; and a plurality of bonding metals disposed on the plurality of first bonding pads and the plurality of second bonding pads, wherein the plurality of decoupling capacitors overlap the plurality of first bonding pads and the plurality of second bonding pads and are located outside of a plurality of portions of the semiconductor die overlapping the plurality of bonding metals.

[0008] Another aspect of this disclosure provides a semiconductor die comprising: a plurality of dielectric layers stacked on a substrate; a plurality of decoupling capacitors formed in the plurality of dielectric layers; a plurality of first bonding pads and a plurality of second bonding pads disposed on the plurality of dielectric layers, wherein the plurality of first bonding pads are coupled to a power supply voltage, the plurality of second bonding pads are coupled to a reference voltage, a group of the plurality of decoupling capacitors is located below one of the plurality of first bonding pads, a plurality of first terminals of the group of the plurality of decoupling capacitors are electrically connected to the one of the plurality of first bonding pads, and a plurality of second terminals of the group of the plurality of decoupling capacitors are connected to one of the plurality of second bonding pads; and a plurality of bonding metals disposed on the plurality of first bonding pads and the plurality of second bonding pads, wherein the plurality of decoupling capacitors overlap the plurality of first bonding pads and the plurality of second bonding pads, and laterally surround the plurality of dielectric layers and overlap a plurality of portions of the plurality of bonding metals.

[0009] Another aspect of this disclosure provides a semiconductor die, comprising: a plurality of first bonding pads and a plurality of second bonding pads, wherein the plurality of first bonding pads are coupled to a power supply voltage and the plurality of second bonding pads are coupled to a reference voltage; a plurality of bonding metals disposed on a plurality of central regions of the plurality of first bonding pads and the plurality of second bonding pads; and a plurality of decoupling capacitors disposed below the plurality of first bonding pads and the plurality of second bonding pads and overlapping a plurality of peripheral regions of the plurality of first bonding pads and the plurality of second bonding pads, wherein the plurality of decoupling capacitors are connected in parallel with each other, a plurality of first terminals of the plurality of decoupling capacitors are electrically connected to the plurality of first bonding pads, and a plurality of second terminals of the plurality of decoupling capacitors are electrically connected to the plurality of second bonding pads.

[0010] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0011] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0012] Figure 1A A schematic plan view of a semiconductor die illustrating some embodiments of this disclosure is shown.

[0013] Figure 1B for Figure 1A A magnified diagram of region X.

[0014] Figure 1C Circuit diagrams illustrating power supply decoupling schemes of some embodiments of this disclosure are shown.

[0015] Figure 1D A cross-sectional schematic diagram illustrating some embodiments of the decoupling capacitor of this disclosure is shown.

[0016] Figure 1E for Figure 1D The diagram shows a top view of the decoupling capacitor.

[0017] Figure 2A A plan view illustrating a bonding pad, an overlying bonding metal, an underlying decoupling capacitor, and a winding, exemplifying some embodiments of this disclosure.

[0018] Figure 2B For along Figure 2A A cross-sectional view of line A-A'.

[0019] Figure 3A A plan view illustrating another bonding pad, an overlying bonding metal, an underlying decoupling capacitor, and a winding, exemplifying some embodiments of this disclosure.

[0020] Figure 3B For along Figure 3A A cross-sectional view of line B-B'.

[0021] Figure 4 Manufacturing of some embodiments of this disclosure is illustrated Figure 2B The flowchart shows the method for preparing a semiconductor die.

[0022] Figures 5A to 5K Example Figure 4 The diagram shows a cross-sectional view of the structure at each stage of the manufacturing process.

[0023] The attached figures are labeled as follows:

[0024] 10: Semiconductor die

[0025] 10a: Cellular region

[0026] 10b: I / O area

[0027] 100: Base

[0028] 102: Winding

[0029] 104: Insulation Structure

[0030] 106: Dielectric layer

[0031] 106': Part

[0032] 106a: Dielectric layer

[0033] 106b: Dielectric layer

[0034] 106c: Dielectric layer

[0035] 108: Winding unit

[0036] 110: Polymer Pattern

[0037] 112: Conductive plug

[0038] BM: Joining Metal

[0039] BP: Joint pad

[0040] BP1: Joint pad

[0041] BP2: Joint pad

[0042] C: Decoupling capacitor

[0043] CM: Conductor material

[0044] DL: Capacitor dielectric layer

[0045] DL': Dielectric material layer

[0046] E1: First electrode

[0047] E2: Second electrode

[0048] EL: Electrode layer

[0049] MA: Memory Array

[0050] PP: Columnar portion

[0051] RL: winding

[0052] RP: Groove portion

[0053] S11: Steps

[0054] S13: Steps

[0055] S15: Steps

[0056] S17: Steps

[0057] S19: Steps

[0058] S21: Steps

[0059] S23: Steps

[0060] S25: Steps

[0061] S27: Steps

[0062] S29: Steps

[0063] S31: Steps

[0064] S33: Steps

[0065] TR: Trench

[0066] V DD Power supply voltage

[0067] V SS Reference voltage

[0068] X: Area Detailed Implementation

[0069] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form a part of this specification, illustrates embodiments of this disclosure; however, this disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0070] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” indicate that the embodiments described in this disclosure may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0071] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0072] Figure 1A A schematic plan view of a semiconductor die 10 illustrating some embodiments of this disclosure is shown. Figure 1B for Figure 1A A magnified diagram of region X.

[0073] Please refer to Figure 1A The semiconductor die 10 may be a memory die. In some embodiments, the semiconductor die 10 is a dynamic random access memory (DRAM) die. For example, the DRAM die may be a first-generation, second-generation, third-generation, or fourth-generation double data rate (DDR) DRAM die (or referred to as DDR1, DDR2, DDR3, or DDR4 DRAM die). Furthermore, the aforementioned DDR DRAM die may be designed to operate under low power supply conditions and may be referred to as a low-power double data rate (LPDDR) DRAM die, such as a fourth-generation low-power double data rate DRAM die (LPDDR4). LPDDR DRAM dies are preferably used in portable electronic products. Moreover, in these embodiments, the semiconductor die 10 may operate at clock pulse frequencies from 2133 Hz to 4266 Hz.

[0074] In some embodiments, the semiconductor die 10 includes two cell regions 10a. These cell regions 10a may be spaced apart from each other. In embodiments where the semiconductor die 10 is a DRAM die, a DRAM array is formed within each cell region 10a. The DRAM array includes multiple memory cells, each including an access transistor and a storage capacitor (not shown) connected to the access transistor. Furthermore, the DRAM array includes multiple word lines and multiple bit lines. The gate terminal of each access transistor is connected to a word line. The source and drain terminals of each access transistor are connected to a bit line and a storage capacitor, respectively. Additionally, the other terminal of each storage capacitor is coupled to a reference voltage (e.g., ground).

[0075] Please refer to Figure 1AThe semiconductor die 10 also includes an input / output (I / O) region 10b extending between two cell regions 10a. I / O circuitry (not shown) and a bonding pad BP are formed within the I / O region 10b. The I / O circuitry and the bonding pad BP are coupled to the cell region 10a to connect the cell region 10a to external circuitry (e.g., a processor). The bonding pad BP is exposed on the surface of the semiconductor die 10 and configured to bond to another semiconductor die or package assembly. Alternatively, the I / O circuitry is disposed within the semiconductor die 10 and connected to the cell region 10a and the bonding pad BP. In some embodiments, the I / O region 10b is an elongated region traversing the central region of the semiconductor die 10. In these embodiments, the bonding pad BP within the I / O region 10b may be referred to as the central bonding pad. Figure 1B As shown, the bonding pads BP are arranged separately along a straight line. Multiple bonding pads BP are configured to transmit different signals. For example, some bonding pads BP are configured to transmit instructions for memory cells within the programmed cell region 10a or instructions for reading data from these memory cells. Furthermore, other bonding pads BP (labeled as bonding pad BP1) are coupled to a power supply voltage (e.g., a reference voltage). Figure 1C The described power supply voltage V DD And some bonding pads BP (labeled as bonding pad BP2) are coupled to a reference voltage (e.g., the reference voltage is...). Figure 1C The described reference voltage V SS As an example, more than 30 pairs of mating pads BP1 and BP2 are disposed within the I / O area 10b.

[0076] In some embodiments, the memory array within cell region 10a is configured to operate at a high clock pulse frequency. In these embodiments, the rapidly switching power supply may generate noise at the switching frequency, and this noise may cause power supply oscillation. Power supply oscillation may inadvertently cause changes in the charge stored in the storage capacitors, thus potentially leading to erroneous reads. Methods to prevent this problem may include decoupling the power supply voltage from the noise.

[0077] Figure 1C Circuit diagrams illustrating power supply decoupling schemes of some embodiments of this disclosure are shown.

[0078] Please refer to Figure 1C In some embodiments, the decoupling capacitor C is disposed at the power supply and memory array MA (i.e., reference 1). Figure 1A The memory array (within the described cell region 10a) is used to remove noise from the power supply to the memory array MA. The power supply can be a DC power supply and can be expressed as the power supply voltage V.DD With reference voltage V SS The voltage difference between (e.g., ground voltage). Power supply voltage V DD Can be coupled to, as referenced Figure 1B The described bonding pad BP1, and the reference voltage V SS Can be coupled to, as referenced Figure 1B The described bonding pad BP2. A decoupling capacitor C can be connected in parallel to the power supply and memory array MA. If noise is generated as the power supply to the memory array MA is supplied, the noise charge can be stored in the decoupling capacitor C and released to ground. In this way, power supply disturbances (or fluctuations) can be effectively reduced. It should be noted that, although only when… Figure 1C A single decoupling capacitor C is shown, but in reality, more than two decoupling capacitors C may be placed between the power supply and the memory array MA, and these decoupling capacitors C are connected in parallel to the power supply voltage V. DD With reference voltage V SS between.

[0079] Figure 1D A cross-sectional schematic diagram of a decoupling capacitor C is shown, illustrating some embodiments of the present disclosure. Figure 1E for Figure 1D The diagram shows a top view of the decoupling capacitor C.

[0080] Please refer to Figure 1D The decoupling capacitor C is a two-terminal element, comprising a first electrode E1, a second electrode E2, and a dielectric layer DL extending between the first electrode E1 and the second electrode E2. The first electrode E1 is one of the two terminals of the decoupling capacitor C, and the second electrode E2 is the other terminal. The first electrode E1 and the second electrode E2 can be coupled to as shown in the reference. Figure 1C The power supply voltage V described DD With reference voltage V SS In other words, the first electrode E1 and the second electrode E2 are electrically connected as shown in the reference. Figure 1BThe bonding pads BP1 and BP2 are described. In some embodiments, the first electrode E1 has a columnar portion PP and a recessed portion RP standing on the columnar portion PP. The area occupied by the recessed portion RP may be larger than the area occupied by the columnar portion PP, so that the columnar portion PP can completely overlap the recessed portion RP. Furthermore, the recessed portion RP defines a recess, and the capacitor dielectric layer DL and the second electrode E2 are disposed within this recess. In some embodiments, the capacitor dielectric layer DL conformally covers the inner surface of the recessed portion RP of the first electrode E1. Furthermore, the second electrode E2 covers the inner surface of the capacitor dielectric layer DL and fills the recess. The first electrode E1 and the second electrode E2 are made of the same or different conductor materials, while the capacitor dielectric layer DL is made of a dielectric material. For example, the conductor material may include polysilicon, titanium, tungsten, and aluminum, while the dielectric material may include silicon oxide, aluminum oxide, and zirconium oxide.

[0081] Please refer to Figure 1D and Figure 1E In some embodiments, the top surface of the first electrode E1, the top surface of the capacitor dielectric layer DL, and the top surface of the second electrode E2 are substantially coplanar and together define the top surface of the decoupling capacitor C. For example... Figure 1E As shown, the second electrode E2 is laterally surrounded by the capacitor dielectric layer DL, and the capacitor dielectric layer DL is laterally surrounded by the first electrode E1. Although the decoupling capacitor C is shown in a circular top view, those skilled in the art can modify the shape of the decoupling capacitor C, and this disclosure is not limited thereto.

[0082] Figure 2A A plan view illustrating a bonding pad, an overlying bonding metal, an underlying decoupling capacitor, and a winding, exemplifying some embodiments of this disclosure. Figure 2B For along Figure 2A A cross-sectional view of line A-A'.

[0083] Please refer to Figure 2A Some decoupling capacitors C are placed on a bonding pad BP1 (i.e., coupled to the power supply voltage V). DD Below the bonding pad BP1. The second electrode E2 of these decoupling capacitors C is electrically connected to the bonding pad BP1, while the first electrode E1 of these decoupling capacitors C can be wound around at least one bonding pad BP2 (not shown in the figure). Figure 2AIn some embodiments, the second electrodes E2 of these decoupling capacitors C are electrically connected to each other via wires RL, and the wires RL are electrically connected to the bonding pad BP1. In some embodiments, the bonding pad BP1 is electrically connected to another package assembly (not shown) via a wire bonding process. In these embodiments, bonding metal BM (e.g., gold balls) is formed on the bonding pad BP1, and wires (not shown) may extend from the bonding metal BM to the other package assembly. Furthermore, the decoupling capacitors C below the bonding pad BP1 may be located in an area that does not overlap with the bonding metal BM. In some embodiments, these decoupling capacitors C overlap in the peripheral area of ​​the bonding pad BP1, while the bonding metal BM overlaps in the central area of ​​the bonding pad BP1. Furthermore, the wires RL may be formed in a loop and overlap in the peripheral area of ​​the bonding pad BP1. Pressure may be applied to the bonding pad BP1 during the formation of the bonding metal BM. If the decoupling capacitors C are located in the area overlapping the bonding metal BM, the aforementioned pressure may cause damage to the decoupling capacitors C, resulting in the decoupling capacitors C being deemed unqualified during testing. Alternatively, this damage may not be detected during testing, potentially leading to a decrease in the reliability of the semiconductor die. Therefore, in this embodiment of the disclosure, by placing the decoupling capacitor C in a region that does not overlap with the bonding metal BM, damage to the decoupling capacitor C caused by the pressure generated during the formation of the bonding metal BM can be effectively avoided.

[0084] Please refer to Figure 2B The semiconductor die 10 includes a substrate 100 and a decoupling capacitor C, a bonding pad BP1, and a bonding metal BM formed on the substrate 100. The substrate 100 may be a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. In some embodiments, the semiconductor die 10 further includes a winding 102 buried in the substrate 100. The winding 102 is electrically connected to a first electrode E1 of the decoupling capacitor C, and the first electrode E1 is connected by the winding 102 to a reference voltage V. SS One or more bonding pads BP2 (as per reference) Figure 1B and Figure 1C (As described). It should be noted that, for the sake of brevity, the winding 102 is not shown in the diagram. Figure 2A In some embodiments, the winding 102 is formed in the bottom region of a recess on the surface of the substrate 100. Furthermore, an insulating structure 104 is formed on the winding 102 and fills the recess. Additionally, the columnar portion PP of the first electrode E1 can pass through the insulating structure 104 to establish an electrical connection with the winding 102. In some embodiments, the winding 102 is simultaneously formed (as shown in the reference). Figure 1A The described I / O area extends within 10b and is similarly referenced. Figure 1AThe word lines of the memory array within the cell region 10a are described. Alternatively, the winding 102 and the word lines can be formed in different process steps. The winding 102 is made of a conductor material, such as Cu, Ti, TiN, Ta, TaN, W, the like, or combinations thereof. On the other hand, the insulating structure 104 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0085] In some embodiments, the semiconductor die 100 further includes multiple stacked dielectric layers 106. A decoupling capacitor C is located within the stack of dielectric layers 106, while bonding pads BP1 and bonding metal BM are disposed on the stack of dielectric layers 106. For example, the decoupling capacitor C may be formed in the bottom dielectric layer 106 (e.g., in the bottom two dielectric layers 106) and may extend through the insulating structure 104 to the winding 102. The pillar-shaped portion PP of the first electrode E1 of the decoupling capacitor C may pass through a dielectric layer 106 (e.g., the bottom dielectric layer 106), and the recessed portion RP of the first electrode E1, the capacitor dielectric layer DL, and the second electrode E2 are formed in another dielectric layer 106 located above the pillar-shaped portion PP of the first electrode E1. (See reference...) Figure 2A As explained, the decoupling capacitor C does not overlap with the region where the bonding metal BM is formed, in order to avoid damage to the decoupling capacitor C during the formation of the bonding metal BM. Figure 2B As shown, a portion 106' of the dielectric layer 106 overlaps the bonding metal BM, and this portion 106' of the dielectric layer 106 is laterally surrounded by the decoupling capacitor C. In some embodiments, the dielectric layer 106 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof.

[0086] In some embodiments, the semiconductor die 10 further includes a winding unit 108. The winding unit 108 is formed in the stack of dielectric layers 106 and configured to connect a decoupling capacitor C to a bonding pad BP (including those shown in…). Figure 2B The bonding pad BP1 in the middle), and transmit signals to the memory array in cell region 10a (as shown in the reference). Figure 1A (As described) or transmit the signal back from the memory array. For example... Figure 2B As shown, a portion of the winding unit 108 is formed above the decoupling capacitor C and configured to connect the second electrode E2 of the decoupling capacitor C to the bonding pad BP1. The winding unit 108 includes conductive traces and conductive vias. Each conductive trace extends on a dielectric layer 106, and each conductive via passes through one or more dielectric layers 106 and is electrically connected to at least one conductive trace. (Refer to...) Figure 2AThe described winding RL may be one of the conductive traces of the winding unit 108. In some embodiments, similar to the decoupling capacitor C, the winding RL overlaps the peripheral region of the bonding pad BP1, while the bonding metal BM overlaps the central region of the bonding pad BP1. Alternatively, the winding RL may at least partially overlap the bonding metal BM. The winding unit 108 may be made of one or more conductive materials, such as Cu, Ti, TiN, Ta, TaN, W, Al, the like, or combinations thereof.

[0087] In some embodiments, a polymer pattern 110 is further formed over the stack of dielectric layers 106. In these embodiments, the polymer pattern 110 may cover the bonding pad BP1 and has an opening in which the bonding metal BM is disposed. In other words, the location of the bonding metal BM may be defined in the opening of the polymer pattern 110. The polymer pattern 110 is made of a polymer material, such as polyimide.

[0088] Figure 3A A schematic plan view illustrating a bonding pad BP, an overlying bonding metal BM, an underlying decoupling capacitor C, and a winding is shown in some embodiments of this disclosure. Figure 3B For along Figure 3A A schematic cross-sectional view of line B-B'. (Shown in...) Figure 3A and Figure 3B A portion of semiconductor die 10 is similar to a reference to semiconductor die 10. Figure 2A and Figure 2B The description only covers the differences; similarities or differences will not be elaborated upon.

[0089] Please refer to Figure 3A and Figure 3B Some decoupling capacitors C are disposed on a bonding pad BP2 (i.e., coupled to the reference voltage V). SS Below the bonding pad BP2. The first electrode E1 of these decoupling capacitors C is electrically connected to the overlying bonding pad BP2, while the second electrode E2 of these decoupling capacitors C may be connected to at least one bonding pad BP1 (not shown in the figure). Figure 3A and Figure 3B (in some embodiments). The first electrodes E1 are electrically connected to each other via windings 102 embedded in the substrate 100, and the windings 102 are electrically connected to the overlying bonding pad BP2 via portions of the winding unit 108. In these embodiments, the winding unit 108 further includes a conductive plug 112 for providing a longitudinal conductive path from this portion of the winding unit 108 extending over the decoupling capacitor C to the windings 102 in the substrate 100. For example, the conductive plug 112 may pass through the underlying dielectric layer 106 and the insulating structure 104, and is located on one side of the decoupling capacitor C. Additionally, similar to reference... Figure 2A The described winding RL, Figure 3A The winding 102 shown can also be formed as a ring and overlap the peripheral area of ​​the bonding pad BP2.

[0090] In some embodiments, the area occupied by bonding pad BP1 / bonding pad BP2 is approximately 3600 μm. 2 The decoupling capacitor occupies an area of ​​approximately 120 nm. 2 In these embodiments, tens of thousands of decoupling capacitors C are disposed beneath each bonding pad BP1 / bonding pad BP2. If the capacitance of each decoupling capacitor C is approximately 15 fF, then the equivalent capacitance of all decoupling capacitors C beneath each bonding pad BP1 / bonding pad BP2 can be approximately 100 pF to approximately 450 pF. However, those skilled in the art can adjust the dimensions of the bonding pads BP and decoupling capacitors C according to design requirements, and this disclosure is not limited thereto.

[0091] As described above, the semiconductor die 10 according to some embodiments of this disclosure includes a decoupling capacitor C for reducing disturbances in the power supply to the memory array. The decoupling capacitor C is disposed coupled to the power supply voltage V. DD With reference voltage V SS The decoupling capacitor C is disposed below the bonding pads BP (i.e., bonding pads BP1 and BP2). Furthermore, the decoupling capacitor C, located below bonding pads BP1 and BP2, overlaps the peripheral areas of bonding pads BP1 and BP2, while the bonding metal BM, formed on bonding pads BP1 and BP2 and used in the bonding process, overlaps the central area of ​​bonding pads BP1 and BP2. This prevents the decoupling capacitor C from being damaged by the pressure applied to bonding pads BP1 and BP2 during the formation of the bonding metal BM. Therefore, the power supply stability capability of the decoupling capacitor C is less affected by the bonding process. Thus, the yield and reliability of the semiconductor die 10 are improved.

[0092] Figure 4 Manufacturing of some embodiments of this disclosure is illustrated Figure 2B The flowchart shows the method for the semiconductor die 10. Figures 5A to 5K To show in Figure 4 The diagram shows a cross-sectional view of the structure at each stage of the manufacturing process.

[0093] Please refer to Figure 4 and Figure 5A Step S11 is performed to form a trench TR on the surface of the substrate 100. Figure 5A The dashed lines shown indicate the portion of substrate 100 that has been removed to form the trench TR. In some embodiments, the method for forming the trench TR includes a photolithography process and an etching process. The etching process is, for example, an anisotropic etching process.

[0094] Please refer to Figure 4 and Figure 5B Step S13 is performed to form a winding 102 at the bottom of the trench TR. The top surface of the winding 102 is lower than the top of the trench TR (i.e., the surface of the substrate 100). In some embodiments, the method of forming the winding 102 includes filling the trench TR with a conductor material. This conductor material may fill the trench TR completely and may or may not extend to the surface of the substrate 100. Subsequently, the upper portion of this conductor material is removed, leaving the portion of the conductor material as the winding 102. For example, the method of removing the upper portion of the conductor material may include an etching process (e.g., an isotropic etching process), or may include a polishing process (e.g., a chemical mechanical polishing (CMP) process) combined with the etching process.

[0095] Please refer to Figure 4 and Figure 5C Step S15 is performed to form an insulating structure 104 on the winding 102. The insulating structure 104 may fill the trench TR, and the top surface of the insulating structure 104 may be substantially coplanar with the surface of the substrate 100. Alternatively, the top surface of the insulating structure 104 may be slightly lower than the top surface of the substrate 100. In some embodiments, the method of forming the insulating structure 104 includes filling the upper portion of the trench TR with an insulating material by a deposition process (e.g., a chemical vapor deposition (CVD) process). This insulating material may fill the trench TR and may or may not extend further to the surface of the substrate 100. Subsequently, the portion of this insulating material above the surface of the substrate 100 may be removed by a planarization process, and the remaining portion of this insulating material becomes the insulating structure 104. For example, the planarization process may include a polishing process (e.g., a CMP process), an etching process (e.g., an isotropic etching process), or a combination thereof.

[0096] Please refer to Figure 4 and Figure 5DStep S17 is performed to form a dielectric layer 106 (hereinafter referred to as dielectric layer 106a) and a columnar portion PP of the first electrode E1 of the decoupling capacitor C. The columnar portion PP of the first electrode E1 may extend through the dielectric layer 106a and the insulating structure 104 to establish an electrical connection with the winding 102. In some embodiments, the dielectric layer 106 is formed by a deposition process (e.g., CVD). Then, vias through the dielectric layer 106a can be formed by a photolithography process and an etching process (e.g., anisotropic etching). Next, conductive material is filled into the vias by a deposition process (e.g., physical vapor deposition, PVD), a plating process, or a combination thereof. Furthermore, a planarization process (e.g., a polishing process, an etching process, or a combination thereof) can be performed to remove the portion of this conductive material above the top surface of the dielectric layer 106a. The remaining portion of this conductive material becomes the columnar portion PP of the first electrode E1.

[0097] Please refer to Figure 4 and Figure 5E Step S19 is performed to form another dielectric layer 106 (hereinafter referred to as dielectric layer 106b) and an electrode layer EL on the current structure. Dielectric layer 106b has openings overlapping the columnar portions PP of the first electrode E1. The area occupied by each opening of dielectric layer 106b may be larger than the area occupied by each columnar portion PP of the first electrode E1. Electrode layer EL may conformally cover the exposed surfaces of dielectric layer 106b, dielectric layer 106a, and the columnar portions PP of the first electrode E1. Accordingly, electrode layer EL is recessed corresponding to the openings of dielectric layer 106b. In some embodiments, the method of forming dielectric layer 106b includes a deposition process, such as a CVD process. Furthermore, the method of forming electrode layer EL may include a deposition process (e.g., a CVD process or a PVD process), a plating process, or a combination thereof.

[0098] Please refer to Figure 4 and Figure 5F Step S21 is performed to form a dielectric material layer DL'. The dielectric material layer DL' conformally covers the electrode layer EL. Accordingly, the dielectric material layer DL' may be recessed to correspond to a recess in the electrode layer EL. In some embodiments, the method of forming the dielectric material layer DL' includes a deposition process, such as a CVD process.

[0099] Please refer to Figure 4 and Figure 5G In step S23, a conductor material CM is formed on the dielectric material layer DL'. The conductor material CM can fill the depressions in the dielectric material layer DL' and can cover the top surface of the dielectric material layer DL'. In some embodiments, the method of forming the conductor material CM includes a deposition process (e.g., a CVD process or a PVD process), a plating process, or a combination thereof.

[0100] Please refer to Figure 4 and Figure 5H Step S25 is performed to remove the portions of the electrode layer EL, dielectric material layer DL', and conductor material CM located above the top surface of the dielectric material layer 106b. This leaves the portions of the electrode layer EL, dielectric material layer DL', and conductor material CM within the opening of the dielectric layer 106b. The retained portion of the electrode layer EL becomes the recessed portion RP of the first electrode E1. The retained portion of the dielectric material layer DL' becomes the capacitor dielectric layer DL. The retained portion of the conductor material CM forms the second electrode E2. Thus, a decoupling capacitor C has been formed according to some embodiments. In some embodiments, the method of patterning the electrode layer EL, dielectric material layer DL', and conductor material CM includes a planarization process. For example, the planarization process may include a polishing process, an etching process, or a combination thereof.

[0101] Please refer to Figure 4 and Figure 5I Step S27 is then performed to form more dielectric layers 106 (hereinafter referred to as dielectric layer 106c) and winding units 108. In some embodiments, the method of forming dielectric layer 106c and winding units 108 includes performing multiple damascene processes. Each damascene process may include depositing one or more dielectric layers 106c; forming vias and / or trenches in dielectric layer 106c; filling the vias and / or trenches with a conductive material; and removing the portion of the conductive material above dielectric layer 106c.

[0102] Please refer to Figure 4 and Figure 5J Step S29 is performed to form a bonding pad BP1 on the stack of dielectric layers 106. The bonding pad BP1 is electrically connected to the uppermost wire-wound unit 108 located in the stack of dielectric layers 106. In some embodiments, the method of forming the bonding pad BP1 includes forming a conductor layer over the dielectric layer 106 by a deposition process, a plating process, or a combination thereof, and then patterning the conductor layer by a photolithography process and an etching process to form the bonding pad BP1. In an alternative embodiment, the bonding pad BP1 can be formed by a metal damascene process, and another dielectric layer (not shown) will laterally surround the bonding pad BP1.

[0103] Please refer to Figure 4 and Figure 5KStep S31 is performed to form a polymer pattern 110 on the current structure. The polymer pattern 110 has an opening overlapping a portion of the bonding pad BP1. In some embodiments, the polymer pattern 110 is made of a photosensitive material. In these embodiments, the method of forming the polymer pattern 110 includes forming a polymer layer over the entire structure and patterning this polymer layer using a photolithography process. Retained portions of the polymer layer form the polymer pattern 110. In alternative embodiments, the polymer pattern 110 is not made of a photosensitive material. In these alternative embodiments, the overly formed polymer layer is patterned using a photolithography process and an etching process to form the polymer pattern 110.

[0104] Please refer to Figure 4 and Figure 2B Step S33 is performed to form bonding metal BM on the exposed surface of bonding pad BP1. In embodiments where bonding metal BM is provided for wire bonding processes, bonding metal BM may be a metal ball, and the end of a metal wire (e.g., gold wire) carried by a bonding device (called a capillary) may be melted using electronic flame-off (EFO) technology. This molten portion is then brought into contact with bonding pad BP1 to form bonding metal BM. The bonding device may then be lifted and moved to form a wire (not shown).

[0105] At this point, the semiconductor die 10 has been formed. Figure 2B A portion shown. According to some embodiments, it can be achieved through a method similar to that described in the reference. Figure 4 and Figures 5A to 5K The described method forms the semiconductor die 10 as follows: Figure 3B Another portion is shown, except that a conductive plug 112 is formed within the stack of dielectric layers 106. In some embodiments, a decoupling capacitor C (as shown in the reference) is formed. Figure 5H After the formation of dielectric layer 106c and winding unit 108 (as described above) Figure 5I Before the process described, conductive plugs 112 are formed. In these embodiments, vias can be formed in dielectric layers 106a and 106b by photolithography and etching processes (e.g., anisotropic etching), and conductive material is filled into the vias by deposition processes (e.g., PVD), plating processes, or combinations thereof. Subsequently, a portion of the conductive material above dielectric layer 106b is removed by planarization processes (e.g., polishing, etching, or combinations thereof) to leave the remaining portion of the conductive material forming the conductive plugs 112.

[0106] In summary, a semiconductor die according to some embodiments of this disclosure includes a memory array and a decoupling capacitor connected in parallel to the memory array for reducing disturbances in the power supply to the memory array. The decoupling capacitor is disposed below a bonding pad coupled to a power supply voltage and a bonding pad coupled to a reference voltage. Furthermore, the decoupling capacitor disposed below the bonding pad overlaps in the peripheral region of the bonding pad. On the other hand, the bonding metal formed on the bonding pad overlaps in the central region of the bonding pad. This prevents the decoupling capacitor from being damaged by pressure that may be applied to the bonding pad during the formation of the bonding metal. Therefore, the power supply stabilization capability of the decoupling capacitor is less affected by the bonding process. Thus, the yield and reliability of the semiconductor die are improved.

[0107] One aspect of this disclosure provides a semiconductor die, comprising: a memory array disposed within a cell region of the semiconductor die; a plurality of first bonding pads and a plurality of second bonding pads disposed within an input / output region of the semiconductor die, wherein the plurality of first bonding pads are coupled to a power supply voltage and the plurality of second bonding pads are coupled to a reference voltage; a plurality of decoupling capacitors disposed below the plurality of first bonding pads and the plurality of second bonding pads and connected in parallel between the plurality of first bonding pads and the plurality of second bonding pads; and a plurality of bonding metals disposed on the plurality of first bonding pads and the plurality of second bonding pads, wherein the plurality of decoupling capacitors overlap the plurality of first bonding pads and the plurality of second bonding pads and are located outside the plurality of portions of the semiconductor die overlapping the plurality of bonding metals.

[0108] Another aspect of this disclosure provides a semiconductor die, comprising: a plurality of dielectric layers stacked on a substrate; a plurality of decoupling capacitors formed in the plurality of dielectric layers; a plurality of first bonding pads and a plurality of second bonding pads disposed on the plurality of dielectric layers, wherein the plurality of first bonding pads are coupled to a power supply voltage, the plurality of second bonding pads are coupled to a reference voltage, a group of the plurality of decoupling capacitors is located below one of the plurality of first bonding pads, a plurality of first terminals of the group of the plurality of decoupling capacitors are electrically connected to the one of the plurality of first bonding pads, and a plurality of second terminals of the group of the plurality of decoupling capacitors are connected to one of the plurality of second bonding pads; and a plurality of bonding metals disposed on the plurality of first bonding pads and the plurality of second bonding pads, wherein the plurality of decoupling capacitors overlap the plurality of first bonding pads and the plurality of second bonding pads, and laterally surround the plurality of dielectric layers overlapping a plurality of portions of the plurality of bonding metals.

[0109] Another aspect of this disclosure provides a semiconductor die, comprising: a plurality of first bonding pads and a plurality of second bonding pads, wherein the plurality of first bonding pads are coupled to a power supply voltage and the plurality of second bonding pads are coupled to a reference voltage; a plurality of bonding metals disposed on a plurality of central regions of the plurality of first bonding pads and the plurality of second bonding pads; and a plurality of decoupling capacitors disposed below the plurality of first bonding pads and the plurality of second bonding pads and overlapping on a plurality of peripheral regions of the plurality of first bonding pads and the plurality of second bonding pads, wherein the plurality of decoupling capacitors are connected in parallel with each other, a plurality of first terminals of the plurality of decoupling capacitors are electrically connected to the plurality of first bonding pads, and a plurality of second terminals of the plurality of decoupling capacitors are electrically connected to the plurality of second bonding pads.

[0110] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0111] Furthermore, the scope of this invention is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this invention that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments of this invention can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this invention.

Claims

1. A semiconductor die with a decoupling capacitor, comprising: A memory array is disposed within a cell region of the semiconductor die; A plurality of first bonding pads and a plurality of second bonding pads are disposed in an input / output region of a semiconductor die, wherein the plurality of first bonding pads are coupled to a power supply voltage and the plurality of second bonding pads are coupled to a reference voltage; Multiple decoupling capacitors are disposed below multiple first bonding pads and multiple second bonding pads, and are connected in parallel between multiple first bonding pads and multiple second bonding pads; as well as Multiple bonding metals are disposed on multiple first bonding pads and multiple second bonding pads, wherein multiple decoupling capacitors overlap multiple first bonding pads and multiple second bonding pads and are located outside multiple portions of the semiconductor die that overlap multiple bonding metals.

2. The semiconductor die with decoupling capacitors as claimed in claim 1, wherein the memory array is connected in parallel to a plurality of the decoupling capacitors.

3. The semiconductor die with decoupling capacitors as claimed in claim 1, wherein a first group of the plurality of decoupling capacitors is located below one of the plurality of first bonding pads, and a second group of the plurality of decoupling capacitors is located below one of the plurality of second bonding pads.

4. The semiconductor die with decoupling capacitors as claimed in claim 3, wherein a plurality of first terminals of the first group of the plurality of decoupling capacitors are electrically connected to one of a plurality of first bonding pads, and a plurality of second terminals of the first group of the plurality of decoupling capacitors are connected to one of a plurality of second bonding pads.

5. The semiconductor die with decoupling capacitors as claimed in claim 4, wherein a plurality of the first terminals of the first group of the plurality of decoupling capacitors are connected by a winding, and the winding is also connected to one of the plurality of first bonding pads.

6. The semiconductor die with decoupling capacitors as claimed in claim 5, wherein the first group of the plurality of decoupling capacitors is arranged along a ring pattern and the winding is formed in a ring.

7. The semiconductor die with decoupling capacitor as claimed in claim 6, wherein the winding laterally surrounds one of the plurality of portions of the plurality of bonding metals overlapping the semiconductor die.

8. The semiconductor die with decoupling capacitor as claimed in claim 1, wherein the plurality of said bonding metals are respectively connected to a bonding wire.

9. The semiconductor die with decoupling capacitor as claimed in claim 1, wherein the memory array is a dynamic random access memory array.

10. A semiconductor die with a decoupling capacitor, comprising: Multiple dielectric layers are stacked on a substrate; Multiple decoupling capacitors are formed in multiple dielectric layers; A plurality of first bonding pads and a plurality of second bonding pads are disposed on a plurality of dielectric layers, wherein the plurality of first bonding pads are coupled to a power supply voltage, the plurality of second bonding pads are coupled to a reference voltage, a group of a plurality of decoupling capacitors is located below one of the plurality of first bonding pads, a plurality of first terminals of the group of a plurality of decoupling capacitors are electrically connected to one of the plurality of first bonding pads, and a plurality of second terminals of the group of a plurality of decoupling capacitors are connected to one of the plurality of second bonding pads; as well as Multiple bonding metals are disposed on multiple first bonding pads and multiple second bonding pads, wherein multiple decoupling capacitors overlap multiple first bonding pads and multiple second bonding pads, and laterally surround multiple dielectric layers overlapping multiple portions of multiple bonding metals.

11. The semiconductor die with decoupling capacitors as claimed in claim 10, wherein the plurality of decoupling capacitors each comprise: A first electrode has a columnar portion and a groove portion located on the columnar portion, and serves as the second terminal of each of the decoupling capacitors; A capacitor dielectric layer conformally covers an inner surface of the groove portion of the first electrode; as well as A second electrode covers the dielectric layer of the capacitor and fills a recess defined by the groove portion of the first electrode, wherein the second electrode serves as the first terminal of each of the decoupling capacitors.

12. The semiconductor die with decoupling capacitors as claimed in claim 11, further comprising a plurality of winding units formed in a plurality of dielectric layers, wherein a plurality of first electrodes and a plurality of second electrodes of the plurality of decoupling capacitors are connected to a plurality of second bonding pads and a plurality of first bonding pads via the plurality of winding units.

13. The semiconductor die with decoupling capacitors as claimed in claim 12, wherein the plurality of winding units include a first winding extending over the group of the plurality of decoupling capacitors, and the plurality of second electrodes of the group of the plurality of decoupling capacitors are electrically connected to each other through the first winding.

14. The semiconductor die with decoupling capacitors as claimed in claim 12, further comprising a second winding embedded in the substrate, wherein a plurality of the first electrodes of the group of the plurality of decoupling capacitors are electrically connected to the second winding.

15. The semiconductor die with decoupling capacitor as claimed in claim 14, wherein the plurality of winding units further includes a conductive plug positioned on the second winding, wherein the second winding is connected to one of the plurality of second bonding pads via the conductive plug.

16. The semiconductor die with decoupling capacitor as claimed in claim 10, further comprising a polymer pattern covering a plurality of the first bonding pads and a plurality of the second bonding pads, and having a plurality of openings respectively exposing one of the plurality of the first bonding pads and the plurality of the second bonding pads.

17. A semiconductor die with a decoupling capacitor, comprising: A plurality of first bonding pads and a plurality of second bonding pads, wherein the plurality of first bonding pads are coupled to a power supply voltage and the plurality of second bonding pads are coupled to a reference voltage; Multiple bonding metals are disposed on multiple central regions of multiple first bonding pads and multiple second bonding pads; as well as Multiple decoupling capacitors are disposed below multiple first bonding pads and multiple second bonding pads, and overlap multiple peripheral regions of multiple first bonding pads and multiple second bonding pads, wherein the multiple decoupling capacitors are connected in parallel with each other, multiple first terminals of the multiple decoupling capacitors are electrically connected to multiple first bonding pads, and multiple second terminals of the multiple decoupling capacitors are electrically connected to multiple second bonding pads. More than one of the decoupling capacitors, which overlap one of the first bonding pads and one of the second bonding pads, is arranged along a ring pattern.

18. The semiconductor die with decoupling capacitors as claimed in claim 17, further comprising a memory array connected in parallel to a plurality of the decoupling capacitors.

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