Back Plate

Abstract

The present invention provides a backplane. The backplane includes a substrate, a gate line, a data line and a power line staggered in rows and columns, and a pixel structure distributed in an array; the pixel structure includes a driving transistor, a switching transistor connected to the driving transistor, and a pixel electrode connected to the driving transistor, the gate line and the data line are respectively connected to the switching transistor, and the power line is connected to the driving transistor; in the same row of pixel structures or the same column of pixel structures, a power line is arranged between the 2n-1 pixel structure and the 2n-th pixel structure, the power line is connected to the source of the driving transistor in the 2n-1 pixel structure, and the power line is connected to the source of the driving transistor in the 2n-th pixel structure; n is a positive integer greater than or equal to 1. The present invention can save pixel area, and then can reasonably layout the driving transistor in the pixel structure through the saved pixel area.

Description

Technical Field

[0001] The present invention relates to the field of display technology or 3D printing technology, and in particular to a backplane. Background Art

[0002] In the prior art, when manufacturing a backplane in the field of display technology or 3D printing technology, when the size of the pixel area occupied by the pixel structure in the backplane is small, the pixel area cannot be saved, and thus the driving transistors in the pixel structure cannot be reasonably arranged through the saved pixel area. Summary of the invention

[0003] One of the purposes of the present invention is to provide a backplane and a backplane pixel structure design to improve the driving ability of the pixel to the pixel electrode or the 3D printed anode and reduce the area occupied by the pixel structure to improve the pixel resolution.

[0004] The present invention provides a backplane, comprising a base substrate, gate lines, data lines and power lines arranged in rows and columns on the base substrate, and an array-distributed pixel structure arranged on the base substrate;

[0005] The pixel structure includes a driving transistor, a switching transistor connected to the driving transistor, and a pixel electrode connected to the driving transistor, the gate line and the data line are respectively connected to the switching transistor, and the power line is connected to the driving transistor;

[0006] In the same row of pixel structures or the same column of pixel structures, a power line is arranged between the 2n-1th pixel structure and the 2nth pixel structure, and the power line is connected to the source of the driving transistor in the 2n-1th pixel structure and the source of the driving transistor in the 2nth pixel structure; n is a positive integer.

[0007] Compared with the prior art, the backplane described in the embodiment of the present invention can save pixel area, and thus the driving transistors in the pixel structure can be reasonably arranged through the saved pixel area. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1a is a circuit diagram of an embodiment of a pixel structure in a backplane according to at least one embodiment of the present invention;

[0009] Figure 1b is a circuit diagram of a plurality of pixel structures in a backplane according to at least one embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a layout of a backplane according to at least one embodiment of the present invention;

[0011] Figure 3is another schematic diagram of the layout of the backplane according to at least one embodiment of the present invention;

[0012] Figure 4 and Figure 5 yes Figure 2 A top view of a gate metal layer in FIG.

[0013] Figure 6 yes Figure 2 A top view of the active layer in FIG.

[0014] Figure 7 yes Figure 2 A top view of the source and drain metal layers in FIG.

[0015] Figure 8 yes Figure 3 A top view of the conductive layer in FIG.

[0016] Fig. 9 is a top view of an embodiment of the conductive layer;

[0017] Fig.10 yes Figure 2 A top view of the capacitor electrode layer in FIG.

[0018] Fig.11 yes Figure 2 A top view of a pixel electrode layer in FIG.

[0019] Fig.12 is Figure 3 A schematic diagram showing the embodiment of the back plate shown in the figure with the labels of the via holes added;

[0020] Fig.13 is Figure 3 On the basis of the above, a schematic diagram of the A-A' section line is added;

[0021] Fig.14 yes Fig.13 A cross-sectional view of the back plate shown in the AA' direction;

[0022] Fig.15A is a schematic diagram of a layout of a backplane according to at least one embodiment of the present invention;

[0023] Fig. 15B yes Fig.15A A cross-sectional view of the back plate shown in the BB' direction;

[0024] Fig.16 yes Figure 3 A top view of an alternative conductive layer used in an embodiment of a backplane is shown. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The backplane provided in the present application can at least be used as a printing backplane in a 3D printing system, the backplane includes printing anodes distributed in an array, and the backplane drives the anodes to achieve 3D printing. Or the backplane provided in the present application can at least be used in the display field to drive pixel electrodes to achieve liquid crystal display or OLED display.

[0027] The backplane described in the embodiment of the present invention may include a pixel structure disposed on a substrate; Figure 1a The figure shows an equivalent circuit diagram of a pixel structure. Figure 1b Shown is an equivalent circuit diagram of a pixel structure distributed in multiple arrays.

[0028] Figure 1a The equivalent circuit diagram of the pixel structure shown includes a driving transistor T1, a switching transistor T2, a storage capacitor C1 and a pixel electrode 10;

[0029] The gate electrode G1 of the driving transistor T1 is electrically connected to the first electrode plate C1a of the storage capacitor C1, the source electrode S1 of the driving transistor T1 is electrically connected to the power line V1, and the drain electrode D1 of the driving transistor T1 is electrically connected to the pixel electrode 10;

[0030] The gate G2 of the switch transistor T2 is electrically connected to the gate line G0, the source S2 of the switch transistor T2 is electrically connected to the data line D0, and the drain D2 of the switch transistor T2 is electrically connected to the first electrode plate C1a of the storage capacitor C1;

[0031] The second electrode plate C1 b of the storage capacitor C1 is electrically connected to the pixel electrode 10 .

[0032] like Figure 1a When the embodiment of the pixel structure shown is in operation, under the control of the gate driving signal provided by the gate line G0, T2 is turned on to provide the data voltage on the data line D0 to the gate of T1, and T1 controls the connection or disconnection between the power line V1 and the pixel electrode 10 under the control of the potential of its gate; C1 is used to maintain the potential of the gate of T1.

[0033] Figure 1bAmong them, TFT1 is a switching transistor, TFT2 is a driving transistor, Gate is a gate line, VDD is a power line, Data is a data line, and C is a storage capacitor.

[0034] The backplane described in the embodiment of the present invention comprises a base substrate, gate lines, data lines and power lines arranged in rows and columns on the base substrate, and a pixel structure arranged in an array on the base substrate;

[0035] The pixel structure includes a driving transistor, a switch transistor connected to the driving transistor, and a pixel electrode connected to the driving transistor; the gate line and the data line are respectively connected to the switch transistor, and the power line is connected to the driving transistor;

[0036] In the same row of pixel structures or the same column of pixel structures, a power line is arranged between the 2n-1th pixel structure and the 2nth pixel structure, and the power line is connected to the source of the driving transistor in the 2n-1th pixel structure and the source of the driving transistor in the 2nth pixel structure; n is a positive integer greater than or equal to 1.

[0037] In a specific implementation, the 2n-1th pixel structure and the 2nth pixel structure share one power line, which can save pixel area, and further, the driving transistors in the pixel structure can be reasonably arranged through the saved pixel area.

[0038] In a specific implementation, in the same row of pixel structures, the 2n-1th pixel structure may be a pixel structure located at the 2n-1th column of the row, and the 2nth pixel structure may be a pixel structure located at the 2nth column of the row, but the present invention is not limited thereto.

[0039] In the same column of pixel structures, the 2n-1th pixel structure may be a pixel structure located in the 2n-1th row of the column, and the 2nth pixel structure may be a pixel structure located in the 2nth row of the column, but the present invention is not limited thereto.

[0040] Optionally, the 2n-1th pixel structure and the 2nth pixel structure are two adjacent pixel structures located in the same row or in the same column; the driving transistor in the 2n-1th pixel structure is a first driving transistor, and the driving transistor in the 2nth pixel structure is a second driving transistor;

[0041] The power line and the source of the first driving transistor are located in different layers, the power line and the source of the second driving transistor are located in different layers, and the power line is connected to the source of the first driving transistor and the source of the second driving transistor through a via.

[0042] In a specific implementation, the driving transistor in a first pixel structure of two adjacent pixel structures is a first driving transistor, the driving transistor in a second pixel structure of two adjacent pixel structures is a second driving transistor, and the power line is electrically connected to the sources of the above two driving transistors.

[0043] Optionally, the source of the first driving transistor and the source of the second driving transistor are located in the same layer, the source of the first driving transistor is connected to the source of the second driving transistor, and the position where the power line is connected to the source through a via is the position where the source of the first driving transistor and the source of the second driving transistor are connected.

[0044] In actual operation, the source of the first driving transistor and the source of the second driving transistor can both be located in the source-drain metal layer, and the power line is electrically connected to the first conductive connection part; the source of the first driving transistor and the source of the second driving transistor are electrically connected through the second conductive connection part, and the first conductive connection part and the second conductive connection part are connected through a via, and the orthographic projection of the first conductive connection part on the substrate substrate at least partially overlaps with the orthographic projection of the second conductive connection part on the substrate substrate.

[0045] In an embodiment of the present invention, the gate line extends along the row direction of the array, and the data line and the power line extend along the column direction of the array; two data lines respectively connected to the switching transistors in the 2nth pixel structure and the 2n+1th pixel structure are arranged between the 2nth pixel structure and the 2n+1th pixel structure; two data lines respectively connected to the switching transistors in the 2n-1th pixel structure and the 2n-2th pixel structure are arranged between the 2n-1th pixel structure and the 2n-2th pixel structure.

[0046] exist Figure 2 and Figure 3 In the embodiment of the substrate shown, the first pixel structure 21 and the second pixel structure 22 are the 2n-1 pixel structure and the 2n pixel structure, respectively, and a power line is provided between the two. Furthermore, the power line is a common power line for the two pixel structures. The switch transistor in the first pixel structure 21 is connected to the first data line D01, and the switch transistor in the second pixel structure 22 is connected to the second data line D02. The two pixel structures and the power line as well as the data line D01 and the data line D02 together constitute a repeating unit and are repeatedly arranged in sequence in the row or column direction.

[0047] In one case, a repeating unit including a 2n-1th pixel structure and a 2nth pixel structure located in the same row may be continuously repeated along the row direction, and the 2n-1th pixel structure and the 2nth pixel structure are symmetrically arranged about a power line in the middle thereof;

[0048] In another case, the repeating unit including the 2n-1th pixel structure and the 2nth pixel structure located in the same column may be continuously repeated along the column direction, and the 2n-1th pixel structure and the 2nth pixel structure are symmetrically arranged about a power line in the middle.

[0049] One implementation manner is that, in the pixel region where the pixel structure is located, the driving transistor and the switching transistor are sequentially arranged along a row or column direction, and the arrangement in a column direction is taken as an example for explanation;

[0050] The gate of the driving transistor extends from the data line to the power line in the row direction, and the gate of the driving transistor extends from the gate line of the pixel structure in the previous row to the switch transistor in the column direction;

[0051] The width direction of the channel in the active layer pattern of the driving transistor is consistent with the row direction, and the channel extends from the data line located on one side of the pixel structure to the power line located on the other side of the pixel structure in the row direction;

[0052] The source electrode of the driving transistor and the drain electrode of the driving transistor extend in a row direction respectively, and the source electrode of the driving transistor and the drain electrode of the driving transistor are arranged in sequence in a column direction;

[0053] The gate of the driving transistor is connected to the drain of the switching transistor, the source of the driving transistor is electrically connected to the power line, and the drain of the driving transistor is electrically connected to the pixel electrode;

[0054] The source of the switch transistor is electrically connected to the data line, and the gate of the switch transistor is electrically connected to the gate line.

[0055] In the backplane described in the embodiment of the present invention, in the pixel area where the pixel structure is located, the driving transistor and the switching transistor are arranged in sequence along the column direction, and the gate of the driving transistor is extended from the data line on one side of the pixel structure to the power line on the other side of the pixel structure in the row direction, so as to occupy most of the area in the row direction of the pixel area, and the gate of the driving transistor is extended from the gate line of the pixel structure in the previous row in the column direction to the direction of the switching transistor, so that the gate of the driving transistor occupies most of the area in the column direction of the pixel area, and the layout of the driving transistor and the switching transistor is compact, and the channel in the active layer pattern of the driving transistor is extended from the data line on one side of the pixel structure to the power line on the other side of the pixel structure in the row direction, so that the width-to-length ratio of the driving transistor is large, so as to improve the driving ability of the driving transistor.

[0056] In an embodiment of the present invention, the source of the driving transistor and the drain of the driving transistor can be arranged in a source-drain metal layer, and the source-drain metal layer can be arranged between the active layer of the driving transistor and the substrate, or the source-drain metal layer can be arranged on a side of the active layer away from the substrate.

[0057] In a specific implementation, the data line and the power line extending along the column direction are located on opposite sides of the pixel structure. The data line can be located on the first side of the pixel structure, and the power line extending along the column direction can be located on the second side of the pixel structure. The first side and the second side are opposite sides.

[0058] In an embodiment of the present invention, the gate of the driving transistor extends in the row direction from the data line to the power line, which means that in the row direction, the gate of the driving transistor extends in the direction from the data line to the power line, wherein the data line may be a data line located on a first side of a pixel structure where the driving transistor is located, and the power line may be a power line located on a second side of the pixel structure where the driving transistor is located and extends in a column direction, but is not limited thereto.

[0059] In the embodiment of the present invention, the gate of the driving transistor extends in the column direction from the gate line of the pixel structure in the previous row to the direction of the switch transistor, which means that in the column direction, the gate of the driving transistor extends in the direction from the gate line of the pixel structure in the previous row to the direction of the switch transistor;

[0060] In an embodiment of the present invention, the channel extends in the row direction from the data line located on one side of the pixel structure to the power line located on the other side of the pixel structure, which means that in the row direction, the extension direction of the channel is: from the data line located on one side of the pixel structure to the power line located on the other side of the pixel structure.

[0061] In a specific implementation, the gate line has a first protrusion, the data line has a second protrusion, the gate of the switch transistor is the first protrusion, and the source of the switch transistor is the second protrusion;

[0062] The width direction of the channel of the active layer pattern of the switch transistor is perpendicular to the width direction of the channel of the drive transistor;

[0063] The drain of the switching transistor also includes an extension portion connected to the drain, the extension portion extends from the direction of the switching transistor to the direction of the power line, and the drain of the switching transistor is connected to the gate of the driving transistor through the extension portion.

[0064] In actual operation, the gate of the switching transistor is the first protrusion of the gate line, the source of the switching transistor is the second protrusion of the data line, the drain of the switching transistor is electrically connected to the gate of the driving transistor through an extension portion, and the extension portion extends toward the power line to make the layout of the switching transistor and the driving transistor compact.

[0065] In a preferred case, the driving transistor in the 2n-1 pixel structure and the driving transistor in the 2n pixel structure are located symmetrically in the pixel region with respect to a power line between the 2n-1 pixel structure and the 2n pixel structure; the use of a symmetrical pixel structure can save pixel area and improve the aspect ratio of the driving transistor;

[0066] Positions of the switch transistor in the 2n-1th pixel structure and the switch transistor in the 2nth pixel structure in the pixel region are symmetrical about a power line between the 2n-1th pixel structure and the 2nth pixel structure.

[0067] like Figure 2 As shown, the backplane described in the embodiment of the present invention includes a base substrate, gate lines, data lines and power lines arranged in rows and columns staggered on the base substrate, and an array-distributed pixel structure arranged on the base substrate;

[0068] exist Figure 2 , the first gate line is labeled G01, the first data line is labeled D01, the second gate line is labeled G02, the second data line is labeled D02, and the power line is labeled V1 extending along the column direction;

[0069] The left pixel structure (the left pixel structure is Figure 2 The first pixel structure 21 located on the left side in the figure includes a driving transistor, a switching transistor connected to the driving transistor, and a pixel electrode connected to the driving transistor;

[0070] The first gate line G01 extends along the row direction of the array and is located at a side of the pixel structure close to the pixel structure of the next row; the first data line D01 and the power line V1 extending along the column direction are located at opposite sides of the first pixel structure 21; D01 is located on the left side of the first pixel structure 21, and V1 is located on the right side of the first pixel structure 21;

[0071] In the pixel area where the first pixel structure 21 is located, the driving transistor and the switching transistor are sequentially arranged along a column direction;

[0072] like Figure 2 and Figure 4As shown, the gate G1 of the driving transistor in the first pixel structure 21 extends from the first data line D01 to the power line V1 in the row direction, and the gate G1 of the driving transistor extends from the gate line connected to the pixel structure of the previous row (in the column direction) to the power line V1. Figure 2 In the embodiment, the gate line connected to the pixel structure in the previous row is a second gate line (G02) extending in the direction of the switch transistor;

[0073] like Figure 2 and Figure 6 As shown, the width direction of the channel 511 in the active layer pattern of the driving transistor is the row direction, and the channel 511 extends from the first data line D01 to the power line V1 in the row direction;

[0074] like Figure 2 and Figure 7 As shown, the source S1 of the driving transistor and the drain D1 of the driving transistor extend in the row direction respectively, and the source S1 of the driving transistor and the drain D1 of the driving transistor are arranged in sequence in the column direction; the source S1 of the driving transistor and the drain D1 of the driving transistor are both located in the source-drain metal layer, and the source-drain metal layer is arranged on the side of the active layer away from the substrate.

[0075] like Figure 2 and Figure 4 As shown, the first gate line G01 has a first protrusion, the main body of the first gate line G01 extends along the row direction, the first protrusion protrudes from the main body of G01, and the gate G2 of the switch transistor is the first protrusion;

[0076] like Figure 2 and Figure 7 As shown, the first data line D01 has a second protrusion, the main body of the first data line D01 extends along the column direction, the second protrusion protrudes from the main body of D01, and the source S2 of the switch transistor is the second protrusion;

[0077] like Figure 2 , Figure 4 and Figure 7 As shown, the gate G2 of the switch transistor is the first protrusion, and the source S2 of the switch transistor is the second protrusion, so that the space occupied by the switch transistor is small.

[0078] In a preferred embodiment, two adjacent columns of pixel structures in the same row of pixel structures are mirror-imaged, and a symmetrical pixel structure is adopted to save pixel area and improve the width-to-length ratio of the driving transistor.

[0079] like Figure 2As shown, the first pixel structure 21 and the second pixel structure 22 are mirror-imaged on both sides of the power line V1; the first pixel structure 21 and the second pixel structure 22 share the power line V1; the power line is located between the driving transistor included in the first pixel structure 21 and the driving transistor included in the second pixel structure 22; the first pixel structure 21 includes a first data line D01, and the second pixel structure 22 includes a second data line D02, the first data line D01 is located on the side of the first pixel structure 21 away from the power line V1, and the second data line D02 is located on the side of the second pixel structure 22 away from the power line V1.

[0080] like Figure 2 and Figure 7 As shown, the source S1 of the driving transistor in the first pixel structure 21 is connected to the source of the driving transistor in the second pixel structure 22 .

[0081] Optionally, the length of the gate of the driving transistor in the column direction is greater than the length of the active layer pattern of the driving transistor in the column direction, so that the gate of the driving transistor extends in the direction of the switching transistor relative to the active layer, and the extended part of the gate of the driving transistor has no overlapping area with the projection of the active layer pattern of the driving transistor on the substrate; the drain of the driving transistor is electrically connected to the pixel electrode through the capacitor electrode layer; the capacitor electrode layer and the extended part of the gate have an overlapping area on the substrate, and the capacitor electrode layer at least forms a capacitor with the extended part of the gate.

[0082] In a specific implementation, the capacitor electrode layer serves as both a connection layer and an electrode of a storage capacitor.

[0083] like Figure 2 , Figure 4 , Figure 5 , Figure 6 and Fig.10 As shown, the length of the gate G1 of the driving transistor in the column direction is greater than the length of the active layer pattern 51 of the driving transistor in the column direction, so that the gate G1 of the driving transistor extends in the direction of the switch transistor relative to the active layer, and the extended portion 40 of the gate G1 and the projection of the active layer pattern 51 of the driving transistor on the substrate have no overlapping area; the drain D1 of the driving transistor is electrically connected to the pixel electrode 10 through the capacitor electrode layer;

[0084] like Figure 2 , Figure 4 , Figure 5 and Fig.10 As shown, the capacitor electrode layer and the extension portion 40 of the gate G1 have an overlapping area on the substrate, and the capacitor electrode layer at least forms a capacitor with the extension portion 40 of the gate.

[0085] Optionally, the capacitor electrode layer is located between the drain of the driving transistor and the pixel electrode, a first insulating layer is provided between the capacitor electrode layer and the drain of the driving transistor, and a second insulating layer is provided between the capacitor electrode layer and the pixel electrode;

[0086] The capacitor electrode layer is electrically connected to the drain electrode of the driving transistor through a via hole provided in the first insulating layer, and the capacitor electrode layer is electrically connected to the pixel electrode through a via hole provided in the second insulating layer;

[0087] The orthographic projection of the capacitor electrode layer on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate have an overlapping area to form a capacitor.

[0088] Optionally, the drain of the driving transistor is located in the source-drain metal layer, the pixel electrode is located in the pixel electrode layer, the capacitor electrode layer A9 is located between the source-drain metal layer A4 and the pixel electrode layer A11, a first insulating layer A5 is provided between the capacitor electrode layer A9 and the source-drain metal layer A4, a second insulating layer A10 is provided between the capacitor electrode layer A9 and the pixel electrode layer A11, the capacitor electrode layer A9 is electrically connected to the drain of the driving transistor through a via hole, the capacitor electrode layer A9 is electrically connected to the pixel electrode through a via hole, and the orthographic projection of the capacitor electrode layer A9 on the substrate has an overlapping area with the orthographic projection of the gate of the driving transistor on the substrate to form a capacitor.

[0089] In an embodiment of the present invention, the power line is in the same layer and is formed of the same material as the capacitor electrode layer, so that there is enough space in the source-drain metal layer to set the source and drain of the driving transistor, thereby being able to set the width-to-length ratio of the driving transistor to be larger to enhance the driving capability of the driving transistor.

[0090] In an embodiment of the present invention, the backplane further comprises the first insulating layer, the organic resin layer, the conductive layer and the third insulating layer which are sequentially arranged between the drain electrode of the driving transistor and the capacitor electrode layer;

[0091] The orthographic projection of the organic resin layer on the base substrate covers the orthographic projection of the active layer pattern on the base substrate, and the orthographic projection of the conductive layer on the base substrate covers the orthographic projection of the active layer pattern on the base substrate; the organic resin layer and the conductive layer prevent the active layer pattern from being damaged;

[0092] The drain electrode of the driving transistor is electrically connected to the conductive layer through a via hole penetrating the first insulating layer and the organic resin layer, and the conductive layer is electrically connected to the capacitor electrode layer through a via hole penetrating the third insulating layer.

[0093] In actual operation, the organic resin layer can be used to enhance the ability to block hydrogen and improve the stability of the backplane; the conductive layer covers the organic resin layer, which can enhance the ability to block hydrogen and prevent the stacking of the capacitor electrode layer from affecting the organic resin layer.

[0094] Optionally, the conductive layer may be made of ITO (indium tin oxide), and the organic resin layer may be made of an organic insulating material, but the present invention is not limited thereto.

[0095] like Figure 3 and Fig.14 As shown, the drain electrode D1 of the driving transistor is located at the source-drain metal layer A4, and the backplane according to the embodiment of the present invention further includes the first insulating layer A5, the organic resin layer A6, the conductive layer A7 and the third insulating layer A8 which are sequentially arranged between the source-drain metal layer A4 and the capacitor electrode layer A9;

[0096] The organic resin layer A6 and the conductive layer A7 are used to block hydrogen; the orthographic projection of the organic resin layer A6 on the base substrate covers the orthographic projection of the active layer pattern on the base substrate, and the orthographic projection of the conductive layer A7 on the base substrate covers the orthographic projection of the active layer pattern on the base substrate;

[0097] The drain electrode of the driving transistor is electrically connected to the conductive layer A7 through a via hole penetrating the first insulating layer A5 and the organic resin layer A6, and the conductive layer A7 is electrically connected to the capacitor electrode layer A9 through a via hole penetrating the third insulating layer A8.

[0098] In a specific implementation, the gate of the driving transistor, the gate of the switching transistor and the gate line can be arranged on the same layer on the substrate and made of the same material; the active layer pattern of the driving transistor and the active layer pattern of the switching transistor can be arranged above the film layer where the gate is located; the source of the driving transistor, the drain of the driving transistor, the source of the switching transistor and the drain of the switching transistor are all arranged on the same layer; the power line and the capacitor electrode layer are located on the same layer and made of the same material, the power line is located above the source of the driving transistor and is connected to the source of the driving transistor through a via, and the pixel electrode is arranged above the power line and the capacitor electrode layer;

[0099] The drain of the driving transistor is electrically connected to the pixel electrode through the capacitor electrode layer, and the orthographic projection of the capacitor electrode layer on the substrate and the orthographic projection of the gate of the driving transistor relative to the extension of the active layer on the substrate have an overlapping area to form a capacitor;

[0100] The drain of the switch transistor is electrically connected to the gate of the drive transistor through an extension portion extending toward the power line.

[0101] In the embodiment of the present invention, Figure 2 , Figure 3 , Figure 4 and Fig.14 As shown, the gate G1 of the driving transistor, the gate G2 of the switching transistor, the first gate line G01 and the second gate line G02 may be disposed on the gate metal layer A1; Figure 2 , Figure 3 , Figure 6 and Fig.14 As shown, the active layer pattern 51 of the driving transistor and the active layer pattern of the switching transistor are arranged on the active layer A3; Figure 2 , Figure 3 , Figure 7 and Fig.14 As shown, the source S1 of the driving transistor, the drain D1 of the driving transistor, the source S2 of the switching transistor and the drain D2 of the switching transistor are all arranged on the source-drain metal layer A4; Figure 2 , Figure 3 , Fig.10 and Fig.14 As shown, the power line V1 and the capacitor electrode layer A9 are provided in the same layer and with the same material; Figure 2 , Figure 3 , Fig.11 and Fig.14 As shown, the pixel electrode is located in the pixel electrode layer A11;

[0102] The gate metal layer A1, the active layer A3, the source-drain metal layer A4, the capacitor electrode layer A9 and the pixel electrode layer A11 may be sequentially arranged on the base substrate.

[0103] The drain electrode of the driving transistor located in the source-drain metal layer A4 is electrically connected to the pixel electrode located in the pixel electrode layer A11 through the capacitor electrode layer A9. Figure 2 , Figure 4 , Figure 5 and Fig.10 As shown, the orthographic projection of the capacitor electrode layer on the base substrate and the orthographic projection of the gate G1 of the driving transistor relative to the extension portion 40 of the active layer on the base substrate have an overlapping area, forming a capacitor.

[0104] In a specific implementation, two adjacent columns of pixel structures in the same row are mirror-imaged and arranged on both sides of the power line;

[0105] Two pixel structures mirror-set on both sides of the power line share one power line, and the power line is located between two driving transistors mirror-set; sources of the two driving transistors mirror-set extend from one pixel structure to another pixel structure along a row direction, and the sources of the two driving transistors are an integrated structure;

[0106] The power line further includes a first conductive connection portion, and a source electrode of a first driving transistor of the two driving transistors in the mirror-image arrangement is electrically connected to a source electrode of a second driving transistor of the two driving transistors in the mirror-image arrangement via a second conductive connection portion;

[0107] The orthographic projection of the first conductive connection portion on the base substrate at least partially overlaps with the orthographic projection of the second conductive connection portion on the base substrate, and the first conductive connection portion is electrically connected to the second conductive connection portion through a via hole so that the source of the driving transistor is electrically connected to the power line.

[0108] like Figure 2 and Figure 3 As shown, the first pixel structure 21 and the second pixel structure 22 are mirror-imaged and arranged on both sides of the power line V1;

[0109] The first pixel structure 21 and the second pixel structure 22 share a power line V1, and the power line V1 is located between the driving transistor of the first pixel structure 21 and the driving transistor of the second pixel structure 22; the source S1 of the driving transistor of the first pixel structure 21 extends from the first pixel structure 21 to the second pixel structure 22 along the row direction, and the driving transistor of the first pixel structure 21 and the driving transistor of the second pixel structure 22 are integrated with the power line V1;

[0110] like Figure 7 As shown, the source electrode S1 of the driving transistor of the first pixel structure 21 and the source electrode of the driving transistor of the second pixel structure 22 are electrically connected via the second conductive connection portion L2;

[0111] The power line also includes a first conductive connection part L1, the orthographic projection of the first conductive connection part L1 on the base substrate at least partially overlaps with the orthographic projection of the second conductive connection part L2 on the base substrate, and the first conductive connection part L1 is electrically connected to the second conductive connection part L2 through a via, so that the source S1 of the driving transistor is electrically connected to the power line V1.

[0112] In an embodiment of the present invention, the backplane may further include: an isolation layer arranged above the active layer pattern of the driving transistor, the isolation layer being used to isolate the influence of impurities on the active layer pattern of the driving transistor; the isolation layer is a single-layer isolation layer or a multi-layer isolation layer, and the single-layer isolation layer or the multi-layer isolation layer includes at least one of an organic resin layer, a metal layer or a metal oxide active layer.

[0113] In a specific implementation, an isolation layer is disposed above the active layer of the driving transistor, and the isolation layer can isolate the influence of impurities (such as hydrogen, oxygen and other impurities) on the active layer pattern of the driving transistor.

[0114] Optionally, the isolation layer may be a single-layer isolation layer, or the isolation layer may be a multi-layer isolation layer, and the isolation layer may include at least one of an organic resin layer, a metal layer, or a metal oxide active layer. Optionally, the multi-layer isolation layer is a double-layer isolation layer, and the double-layer isolation layer includes an organic resin layer and a metal oxide active layer sequentially arranged above the active layer.

[0115] In a specific implementation, the metal oxide active layer or metal layer in the isolation layer includes an isolation portion arranged above the active layer pattern of the driving transistor of each pixel structure; the isolation portions are independent of each other, or the isolation portions are arranged in an integrated manner.

[0116] When the isolation layer adopts a metal oxide active layer or a metal layer, the isolation layer includes an isolation part, and the isolation part is arranged above the active layer pattern of the driving transistor. The multiple isolation parts included in the isolation layer can be independent of each other or arranged in an integrated manner, and the structure of the isolation part is not limited to this.

[0117] In the embodiment of the present invention, the backplane may further include the first insulating layer, the organic resin layer, the conductive layer containing metal and the third insulating layer which are sequentially arranged between the drain electrode of the driving transistor and the capacitor electrode layer; a second insulating layer is arranged between the capacitor electrode layer and the pixel electrode;

[0118] The organic resin layer and the conductive layer serve as protective layers for the active layer pattern of the driving transistor, and are used to block hydrogen; the orthographic projection of the organic resin layer on the base substrate covers the orthographic projection of the active layer pattern of the driving transistor on the base substrate, and the orthographic projection of the conductive layer on the base substrate covers the orthographic projection of the active layer pattern of the driving transistor on the base substrate;

[0119] The vias between the first conductive connection portion and the second conductive connection portion include a first via, a second via and a third via; the first via is a via that passes through the first insulating layer, the second via is a via that passes through the organic resin layer, and the third via is a via that passes through the third insulating layer;

[0120] The orthographic projection of the first via hole on the base substrate, the orthographic projection of the second via hole on the base substrate, and the orthographic projection of the third via hole on the base substrate at least partially overlap, so that the first conductive connection portion is electrically connected to the second conductive connection portion.

[0121] exist Fig.12 In the figure, the ones marked with numbers H01, H02, and H03 are the first via hole, the second via hole, and the third via hole, respectively.

[0122] like Fig.14 As shown, the orthographic projection of the first via hole H01 on the base substrate and the orthographic projection of the third via hole on the base substrate are within the orthographic projection of the second via hole H02 on the base substrate.

[0123] like Fig.14 As shown, the backplane may include a conductive layer A7 and an organic resin layer A6; the conductive layer A7 is arranged on a side of the capacitor electrode layer A9 away from the base substrate 20; the organic resin layer A6 is arranged between the conductive layer A7 and the source-drain metal layer A4; the backplane also includes a first insulating layer A5 arranged between the source-drain metal layer A4 and the organic resin layer A6 and a third insulating layer A8 arranged between the conductive layer A7 and the capacitor electrode layer A9; the vias include a first via H01, a second via H02 and a third via H03.

[0124] exist Fig.14 In the figure, A1 is a gate metal layer, A2 is a gate insulating layer, A3 is an active layer, A10 is a second insulating layer, and A11 is a pixel electrode layer.

[0125] Optionally, both the first insulating layer and the third insulating layer may be passivation layers, but the present invention is not limited thereto.

[0126] like Fig.12 and Fig.14 As shown, the orthographic projection of the first via hole H01 on the base substrate 20 is within the orthographic projection of the second via hole H02 on the base substrate 20 , and the orthographic projection of the third via hole H03 on the base substrate 20 is within the orthographic projection of the second via hole H02 on the base substrate 20 .

[0127] In the embodiment of the present invention, due to process limitations, the area of ​​the orthographic projection of H02 on the substrate is set to be larger than the area of ​​the orthographic projection of H01 on the substrate, and the area of ​​the orthographic projection of H02 on the substrate is set to be larger than the area of ​​the orthographic projection of H03 on the substrate, so as to ensure that H01 can be fully presented and can be completely etched.

[0128] In specific implementation, Figure 8 As shown, the conductive layer may include a plurality of mutually independent conductive patterns 30; the orthographic projection of the conductive patterns 30 on the substrate covers the pixel region where the pixel structure is arranged. In addition, the openings between the conductive patterns 30 may expose the first conductive connection portion L1 and the second conductive connection portion L2 to avoid short circuit.

[0129] In a specific implementation, the active layer may be a metal oxide active layer, but is not limited thereto.

[0130] In a specific implementation, the active layer can be made of IGZXO, which is a metal added to IGZO (indium gallium zinc oxide) to enhance the acid corrosion resistance of the transistor source and drain during etching, reduce back channel damage, and improve the stability of TFT (thin film transistor).

[0131] In an embodiment of the present invention, the backplane may include a gate metal layer, an active layer, a source-drain metal layer, a capacitor electrode layer and a pixel electrode layer which are sequentially arranged on the base substrate, the gate metal layer includes a gate line, a gate of the driving transistor and a gate of the switching transistor, the gate of the driving transistor is reused as a first plate of a storage capacitor, the active layer includes an active layer pattern of the driving transistor and an active layer pattern of the switching transistor, the capacitor electrode layer includes a power line and a first plate portion of a second plate of the storage capacitor; the source-drain metal layer includes a source of the driving transistor, a drain of the driving transistor, a source of the switching transistor, a drain of the switching transistor, and a second plate portion of a second plate of the storage capacitor; the pixel electrode layer includes a plurality of independent pixel electrodes.

[0132] The embodiment of the present invention adopts a stacked structure of a gate metal layer, a capacitor electrode layer and a source-drain metal layer to form a capacitor, so as to simplify the process flow, simplify the pixel structure, reduce the pixel structure area and ensure a higher driving capability.

[0133] like Figure 2 and Figure 3As shown, the first pixel structure 21 and the second pixel structure 22 are mirror-imaged and arranged on both sides of the power line V1 extending along the column direction; the first pixel structure 21 and the second pixel structure 22 are arranged in the same row; the first pixel structure 21 includes a driving transistor, a switching transistor and a first data line D01; the second pixel structure 22 includes a driving transistor, a switching transistor and a second data line D02;

[0134] The first pixel structure 21 and the second pixel structure 22 share the first gate line G01 and the power line V1; pixel structures in the same column may share the same data line.

[0135] like Figure 2 As shown, the backplane includes a gate metal layer A1, an active layer A3, a source-drain metal layer A4, a capacitor electrode layer A9 and a pixel electrode layer A11 which are sequentially arranged on the base substrate 20;

[0136] Figure 4 and Figure 5 yes Figure 2 A top view of the gate metal layer in FIG. Figure 6 yes Figure 2 Top view of the active layer in Figure 7 yes Figure 2 A top view of the source and drain metal layers in FIG. Fig.10 yes Figure 2 A top view of the capacitor electrode layer in FIG. Fig.11 yes Figure 2 A top view of the pixel electrode layer in FIG.

[0137] Figure 3 The embodiment of the back plate shown is similar to Figure 2 The difference of the embodiment of the backplane shown is that a conductive layer and an organic resin layer are added, and a second via hole and a second connecting via hole are added.

[0138] exist Figure 4 and Figure 5 In the figure, the first gate line is labeled G01, the second gate line is labeled G02, and the gate of the driving transistor in the first pixel structure 21 is labeled G1. The gate G1 of the driving transistor in the first pixel structure 21 is multiplexed as the first plate of the storage capacitor; Figure 4 and Figure 5 In the figure, the gate of the switch transistor in the first pixel structure 21 is marked with G2, and the gate G2 of the switch transistor in the first pixel structure 21 is the protrusion of G01; Figure 6 In the figure, the active layer pattern of the driving transistor in the first pixel structure 21 is marked with 51; the active layer pattern of the switching transistor in the first pixel structure 21 is marked with 52; Figure 7In the figure, the source of the driving transistor in the first pixel structure 21 is marked with S1, the drain of the driving transistor in the first pixel structure 21 is marked with D1, the source of the switching transistor in the first pixel structure 21 is marked with S2, the drain of the switching transistor in the first pixel structure 21 is marked with D2, and the extension portion is marked with L3, and the extension portion L3 is electrically connected to D2; Figure 7 In the figure, S2 is the protrusion of D01. Figure 8 In the figure, the reference numeral 30 indicates a conductive pattern included in the conductive layer. Fig.10 In FIG. 1 , the first conductive connection portion is labeled L1, and the power line is labeled V1 and arranged along the column direction. Fig.11 In the figure, the element marked with 10 is a pixel electrode.

[0139] like Figure 4 and Figure 5 As shown in FIG. 1 , the main part of G01 is a linear part extending along the row direction, and G2 is an integral structure with the main part of G01 and protrudes from the main part of G01. Figure 7 As shown, the main body of D01 is a linear portion extending along the column direction, and S2 is an integral structure with the main body of D01 and protrudes from the main body of D01.

[0140] In the embodiment of the present invention, the column direction may be a vertical direction, the row direction may be a horizontal direction, the first side may be a left side, and the second side may be a right side, but the present invention is not limited thereto.

[0141] like Figure 2 and Figure 3 As shown, the first pixel structure 21 and the second pixel structure are mirror-imaged on opposite sides of the power line V1, and a symmetrical pixel structure is used to save pixel area. In the embodiment of the present invention, the power line is arranged in the capacitor electrode layer to further save pixel area and achieve better resolution. In addition, the embodiment of the present invention uses low-resistance metal to make the power line and expands the line width of the power line as much as possible to reduce the IR voltage drop under large current (IR voltage drop refers to a phenomenon in which the voltage drops or increases on the power supply and ground networks in an integrated circuit) and improve the uniformity of the large-size backplane.

[0142] like Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, the active layer pattern of the driving transistor includes a first channel portion 511, a first electrode contact portion 512 and a second electrode contact portion 513;

[0143] The orthographic projection of the source S1 of the driving transistor on the substrate at least partially overlaps with the orthographic projection of the first electrode contact portion 512 on the substrate, and the orthographic projection of the drain D1 of the driving transistor on the substrate at least partially overlaps with the orthographic projection of the second electrode contact portion 513 on the substrate;

[0144] The source electrode S1 of the driving transistor is in direct contact with the first electrode contact portion 512 , and the drain electrode D1 of the driving transistor is in direct contact with the second electrode contact portion 513 ;

[0145] The first channel portion 511 is disposed between the first electrode contact portion 512 and the second electrode contact portion 513;

[0146] The first channel portion 511 extends along a row direction.

[0147] like Figure 6 As shown, a ratio between a width of the first channel portion 511 in the row direction and a length of the first channel portion 511 in the column direction (the ratio is also the width-to-length ratio of the driving transistor) is greater than a predetermined ratio.

[0148] In an embodiment of the present invention, the power line and the capacitor electrode layer are arranged in the same layer and with the same material, so that there is enough space in the source-drain metal layer to arrange the source and drain of the driving transistor, thereby being able to set the width-to-length ratio of the driving transistor to be larger to improve the driving capability.

[0149] exist Figure 2 and Figure 3 In the illustrated embodiment, the width-to-length ratio of the driving transistor may be greater than or equal to 4 and less than or equal to 8. For example, the width-to-length ratio of the driving transistor may be equal to 5, but is not limited thereto.

[0150] In the embodiment of the present invention, the predetermined ratio may be greater than or equal to 1 and less than or equal to 12.5, but is not limited thereto.

[0151] like Figure 7 As shown, the drain electrode D1 of the driving transistor and the second electrode plate portion C1b2 are an integrated structure;

[0152] like Figure 2 , Figure 3 , Figure 7 and Fig.10 As shown, there is a first overlapping area between the orthographic projection of the first electrode portion C1b1 on the substrate and the orthographic projection of the second electrode portion C1b2 on the substrate; the first electrode portion C1b1 and the power line V1 are independent of each other;

[0153] The first electrode portion C1b1 is electrically connected to the second electrode portion C1b2 through a connecting via; the connecting via is provided in the first overlapping region;

[0154] like Figure 2 , Figure 3 , Fig.10 , Fig.11 and Fig.12 As shown, there is a second overlapping area between the orthographic projection of the first electrode portion C1b1 on the base substrate and the orthographic projection of the pixel electrode 10 on the base substrate;

[0155] The first electrode portion C1b1 is electrically connected to the pixel electrode 10 through a fourth via hole H04 disposed in the second overlapping area.

[0156] exist Fig.14 Among them, the via hole labeled H04 is a fourth via hole, and the fourth via hole H04 is a via hole penetrating the second insulating layer A10.

[0157] like Figure 3 , Figure 7 , Figure 8 and Fig.10 As shown, the second electrode portion C1b2 is electrically connected to the conductive pattern 30 through the first connection via H1 and the second connection via H2; the conductive pattern 30 is electrically connected to the first electrode portion C1a through the third connection via H3.

[0158] like Fig.12 As shown, the connecting vias may include a first connecting via H1, a second connecting via H2 and a third connecting via; the orthographic projection of the first connecting via H1 on the base substrate is within the orthographic projection of the second connecting via H2 on the base substrate, and the orthographic projection of the third connecting via on the base substrate is within the orthographic projection of the second connecting via H2 on the base substrate.

[0159] exist Fig.12 In the corresponding embodiment, the orthographic projection of the first connecting via H1 on the base substrate overlaps with the orthographic projection of the third connecting via on the base substrate, but the invention is not limited thereto. In actual operation, the orthographic projection of the first connecting via on the base substrate may also at least partially overlap with the orthographic projection of the third connecting via on the base substrate.

[0160] like Fig.14 As shown, the first connection via hole H1 is a via hole penetrating the first insulating layer A5, the second connection via hole H2 is a via hole penetrating the organic resin layer A6, and the third connection via hole H3 is a via hole penetrating the third insulating layer A8;

[0161] The orthographic projection of the first connecting via H1 on the base substrate is within the orthographic projection of the second connecting via H2 on the base substrate, and the orthographic projection of the third connecting via H3 on the base substrate is within the orthographic projection of the second connecting via H2 on the base substrate.

[0162] In an embodiment of the present invention, due to process limitations, the area of ​​the orthographic projection of H2 on the substrate is set to be larger than the area of ​​the orthographic projection of H1 on the substrate, and the area of ​​the orthographic projection of H2 on the substrate is set to be larger than the area of ​​the orthographic projection of H3 on the substrate, so as to ensure that H1 can be fully presented and can be completely etched.

[0163] like Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 7 As shown, the gate G1 of the driving transistor is reused as the first plate of the storage capacitor; the second plate portion C1b2 and the second electrode D1 of the driving transistor are an integrated structure;

[0164] exist Fig.10 Among them, the portion labeled C1b1 is the first electrode portion;

[0165] like Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 7 and Fig.10 As shown, the orthographic projection of the first electrode plate C1a on the base substrate, the orthographic projection of the first electrode plate portion C1b1 on the base substrate, and the orthographic projection of the second electrode plate portion C1b2 on the base substrate at least partially overlap to form a storage capacitor.

[0166] like Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, the active layer pattern of the switch transistor includes a second channel portion 521 (i.e., a channel of the active layer pattern of the switch transistor), a third electrode contact portion 522 and a fourth electrode contact portion 523;

[0167] The orthographic projection of the source S2 of the switch transistor on the substrate at least partially overlaps with the orthographic projection of the third electrode contact portion 522 on the substrate, and the orthographic projection of the drain D2 of the switch transistor on the substrate at least partially overlaps with the orthographic projection of the fourth electrode contact portion 523 on the substrate;

[0168] The source S2 of the switch transistor is in direct contact with the third electrode contact portion 522, and the drain D2 of the switch transistor is in direct contact with the fourth electrode contact portion 523;

[0169] The second channel portion 521 is disposed between the third electrode contact portion 522 and the fourth electrode contact portion 523 .

[0170] In a specific implementation, the second electrode of the switch transistor is electrically connected to the extension portion, a third overlapping region exists between the orthographic projection of the extension portion on the substrate and the orthographic projection of the first electrode plate of the storage capacitor on the substrate, and the first electrode plate of the storage capacitor is electrically connected to the extension portion through a fourth connecting via hole provided in the third overlapping region, so that the first electrode plate of the storage capacitor is electrically connected to the second electrode of the switch transistor;

[0171] The backplane further comprises a gate insulating layer disposed between the gate metal layer and the active layer;

[0172] The fourth connection via hole is a via hole penetrating the gate insulation layer.

[0173] like Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 7 As shown, the drain D2 of the switching transistor is electrically connected to the extension portion L3, and there is a third overlapping area between the orthographic projection of the extension portion L3 on the substrate and the orthographic projection of the first electrode plate of the storage capacitor (that is, the gate G1 of the driving transistor) on the substrate, and the first electrode plate of the storage capacitor is electrically connected to the extension portion L3 through a fourth connecting via H4 arranged in the third overlapping area, so that the first electrode plate of the storage capacitor is electrically connected to the second electrode D2 of the switching transistor.

[0174] exist Fig.14 Among them, the one labeled H4 is a fourth connection via hole, and the fourth connection via hole H4 is a via hole penetrating the gate insulating layer A2.

[0175] In the embodiment of the present invention, Fig. 9 As shown, the conductive layer includes a plurality of independent conductive patterns 30, and the orthographic projection of the conductive patterns 30 on the base substrate covers the pixel area where the pixel structure is arranged; and as shown Fig. 9 As shown, the conductive layer has openings between the plurality of independent conductive patterns 30 to expose the first conductive connection portion and the second conductive connection portion to prevent short circuit.

[0176] Optionally, the backplane described in the embodiment of the present invention may include a gate metal layer, an active layer, an etching barrier layer, a source-drain metal layer, a capacitor electrode layer and a pixel electrode layer sequentially arranged on the substrate; the etching barrier layer is used to protect the active layer from being etched;

[0177] The active layer is electrically connected to the source-drain metal layer through a via hole penetrating the etching stop layer; the gate of the driving transistor and the gate of the switching transistor are arranged on the gate metal layer; the active layer pattern of the driving transistor and the active layer pattern of the switching transistor are arranged on the active layer; the source of the driving transistor, the drain of the driving transistor, the source of the switching transistor and the drain of the driving transistor are all arranged on the source-drain metal layer; the power line is arranged on the capacitor electrode layer, and the pixel electrode is arranged on the pixel electrode layer; the pixel electrodes included in different pixel structures are independent of each other;

[0178] The drain of the driving transistor is electrically connected to the pixel electrode through the capacitor electrode layer, and the orthographic projection of the capacitor electrode layer on the base substrate has an overlapping area with the orthographic projection of the gate of the driving transistor on the base substrate; the drain of the switching transistor is electrically connected to the gate of the driving transistor through an extension portion extending in the direction of the power line.

[0179] In a specific implementation, an etch barrier layer may be provided between the active layer and the source / drain metal layer, and the active layer is electrically connected to the source / drain metal layer through a via hole penetrating the etch barrier layer; the etch barrier layer is used to protect the active layer from being etched, and the etch barrier layer can protect the back channel and prevent the back channel from being damaged by the etching process when forming the source / drain.

[0180] like Fig.15A and Fig. 15B As shown, the backplane described in the embodiment of the present invention includes a gate metal layer A1, a gate insulating layer A2, an active layer A3, an etching barrier layer A4, a source-drain metal layer A5, a first insulating layer A6, a capacitor electrode layer A7, a second insulating layer A8 and a pixel electrode layer A9, which are sequentially arranged above the base substrate 20.

[0181] exist Fig.15A In the figure, the number 10 is a pixel electrode, the number V1 is a power line extending along the column direction, the number G01 is a first gate line, the number G02 is a second gate line, the number D01 is a first data line, and the number D02 is a second data line.

[0182] Fig.15A The backplane layout shown is similar to Figure 2The difference in the layout of the backplane is that: an etching blocking layer A4 is provided, and the source of the driving transistor is electrically connected to the active layer pattern of the driving transistor through a first electrode via, the drain of the driving transistor is electrically connected to the active layer pattern of the driving transistor through at least one second electrode via, the source of the switching transistor is electrically connected to the active layer pattern of the switching transistor through a third electrode via, and the drain of the switching transistor is electrically connected to the active layer pattern of the switching transistor through a second electrode via; the size and position of each via; and the shape of the power line.

[0183] like Fig.15A and Fig. 15B As shown, the first electrode via hole H11, the second electrode via hole H12, the third electrode via hole H13 and the fourth electrode via hole H14 are via holes penetrating the etching stop layer.

[0184] like Fig.15A In the figure, L1 is a first conductive connection portion included in the power line, such as Fig.15A and Fig. 15B As shown, L1 is electrically connected to the second conductive connection portion (the second conductive connection portion is provided in the source-drain metal layer) through a first via hole H01 penetrating the first insulating layer A6;

[0185] exist Fig.15A and Fig. 15B In the embodiment shown, the gate of the driving transistor is reused as the first plate of the storage capacitor; the drain of the driving transistor and the second plate portion are an integrated structure; the second plate portion is electrically connected to the first plate portion through a second via H02; the first plate portion is electrically connected to the pixel electrode 10 through a third via H03.

[0186] like Fig.15A and Fig. 15B As shown, the orthographic projection of the second via hole H02 on the base substrate does not overlap with the orthographic projection of the third via hole H03 on the base substrate, so as to avoid line breakage, but the present invention is not limited thereto.

[0187] When manufacturing the backplane described in the embodiment of the present invention, when depositing the capacitor electrode layer, it will sink at the position of the second via hole H02. If the orthographic projection of H03 on the base substrate overlaps with the orthographic projection of H02 on the base substrate, the first electrode portion C1b1 may not be electrically connected to the pixel electrode 10 through the third via hole H03 set in the third overlapping area. Therefore, in actual operation, the orthographic projection of the second via hole H02 on the base substrate and the orthographic projection of the third via hole H03 on the base substrate are set to not overlap.

[0188] exist Fig.15A and Fig. 15BIn the embodiment shown, the drain of the switching transistor is electrically connected to the extension portion, and the gate of the driving transistor (i.e., the first plate of the storage capacitor) is electrically connected to the extension portion through a fourth via H04 (H04 is a via that passes through the gate insulation layer and the etching barrier layer), so that the first plate of the storage capacitor is electrically connected to the drain of the switching transistor.

[0189] exist Figure 3 In the embodiment of the backplane shown in FIG. 1 , the structure of the conductive layer can be replaced by Fig.16 The structure shown.

[0190] like Fig.16 As shown, the conductive layer may include a plurality of first openings K1 and a plurality of second openings K2 , and the third connection vias H3 pass through the first openings K1 ; the first openings K1 expose the first conductive connection portions L1 and the second conductive connection portions L2 to avoid short circuit.

[0191] use Fig.16 According to the structure of the conductive layer shown, the second electrode portion can be directly electrically connected to the first electrode portion through the first connecting via, the second connecting via and the third connecting via, without the need for switching through the conductive layer. Therefore, when manufacturing the substrate described in the embodiment of the present invention, the first insulating layer and the organic resin layer can be manufactured in sequence on the side of the source and drain metal layer away from the base substrate, and then the second connecting via is manufactured through the organic resin layer, and then the third insulating layer is manufactured on the side of the organic resin layer away from the first insulating layer. Then, the same dry etching process is used to manufacture the first connecting via that penetrates the first insulating layer and the third connecting via that penetrates the third insulating layer. In this way, one mask can be saved, thereby saving production costs.

[0192] like Fig.16 As shown, the conductive patterns 30 included in the conductive layer can be connected to each other, which can improve pixel uniformity.

[0193] In actual operation, in order to avoid ESD (Electro-Static discharge) problems, the conductive pattern may be connected to a suitable potential. For example, the conductive pattern may be grounded, but the present invention is not limited thereto.

[0194] In the embodiment of the present invention, under the premise of not affecting the characteristics of TFT (Thin Film Transistor), the conductive pattern may also be electrically connected to other voltage signal lines in the display panel.

[0195] In the embodiment of the present invention, the conductive layer does not serve as a transfer layer between metal layers, and the capacitor electrode layer is directly electrically connected to the pixel electrode layer through a via hole, which can reduce the contact resistance.

[0196] In the embodiment of the present invention, Figure 2 , Figure 3 and Fig.15A As shown, the power line labeled V21 is the first power line extending in the row direction, and the power line labeled V22 is the second power line extending in the row direction. The power lines in the embodiment of the present invention can be arranged in a grid shape, the first conductive connection part L1 is arranged between V21 and V22, and the length of L1 in the row direction is greater than the length of V1 in the row direction, the length of L1 in the column direction is greater than the length of V21 in the column direction, and the length of L1 in the column direction is greater than the length of V22 in the column direction, but not limited to this. Among them, L1, V21, V22 and V1 are electrically connected.

[0197] In an embodiment of the present invention, the power lines are arranged in a grid shape to maximize the line width, and low-resistance metal can be used to make the power lines to reduce IR voltage drop under large current (IR voltage drop refers to a phenomenon in which the voltage drops or increases on the power and ground networks in an integrated circuit) and improve the uniformity of a large-size backplane.

[0198] The 3D printing system described in the embodiment of the present invention includes a printing box and the above-mentioned back plate; the printing box contains an electrolyte; the printing box includes a first cover plate and a second cover plate arranged opposite to each other; the back plate is arranged on the side of the first cover plate facing the second cover plate, so that each pixel electrode of the back plate faces the electrolyte; and a cathode for printing is arranged on the side of the second cover plate facing the first cover plate.

[0199] In a specific implementation, the backplane includes a pixel structure and a pixel electrode arranged on a base substrate; the pixel structure is used to control the data voltage on the corresponding column data line under the control of the gate drive signal on the corresponding row gate line, and control the connection or disconnection between the power line and the pixel electrode, so as to control the position of the metal ions to be printed in the electrolyte to be deposited on the second cover plate, and finally form a 3D pattern to achieve high-precision printing.

[0200] In an embodiment of the present invention, when the backplane is an anode backplane for 3D printing, the pixel electrode is an electrochemical anode, and the electrochemical anode and cathode can be arranged in the same closed cavity structure, and the closed cavity structure contains an electrolyte, and the electrolyte is a metal salt solution to be printed. For example, when the printed metal is copper, the electrolyte can be a copper sulfate solution, or other copper metal salt solution; and, in the closed cavity structure, the backplane and the cathode backplane (the cathode backplane is provided with a cathode) are arranged opposite to each other, and the electrolyte, the electrochemical anode and the cathode constitute an electrochemical circuit; a voltage is applied between the electrochemical anode and the cathode, and the copper ions move to the vicinity of the cathode and are deposited on the cathode backplane to form a 3D stereoscopic figure.

[0201] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0202] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0203] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0204] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A backplane, characterized in that: It includes a base substrate, gate lines, data lines and power lines arranged in rows and columns on the base substrate, and a pixel structure arranged in an array on the base substrate; The pixel structure includes a driving transistor, a switching transistor connected to the driving transistor, and a pixel electrode connected to the driving transistor, the gate line and the data line are respectively connected to the switching transistor, and the power line is connected to the driving transistor; In the same row of pixel structures or the same column of pixel structures, a power line is provided between the 2n-1th pixel structure and the 2nth pixel structure, and the power line is connected to the source of the driving transistor in the 2n-1th pixel structure and the source of the driving transistor in the 2nth pixel structure; n is a positive integer greater than or equal to 1; The gate lines extend along the row direction of the array, and the data lines and the power lines extend along the column direction of the array; two data lines connected to the switch transistors in the 2nth pixel structure and the 2n+1th pixel structure are respectively arranged between the 2nth pixel structure and the 2n+1th pixel structure; two data lines connected to the switch transistors in the 2n-1th pixel structure and the 2n-2th pixel structure are respectively arranged between the 2n-1th pixel structure and the 2n-2th pixel structure; In a pixel region where the pixel structure is located, the driving transistor and the switching transistor are sequentially arranged along a column direction; The gate of the driving transistor extends from the data line to the power line in the row direction, and the gate of the driving transistor extends from the gate line of the pixel structure in the previous row to the switch transistor in the column direction; The width direction of the channel in the active layer pattern of the driving transistor is consistent with the row direction, and the channel extends from the data line located on one side of the pixel structure to the power line located on the other side of the pixel structure in the row direction; The source electrode of the driving transistor and the drain electrode of the driving transistor extend in a row direction respectively, and the source electrode of the driving transistor and the drain electrode of the driving transistor are arranged in sequence in a column direction; The gate of the driving transistor is connected to the drain of the switching transistor, the source of the driving transistor is electrically connected to the power line, and the drain of the driving transistor is electrically connected to the pixel electrode; The source of the switch transistor is electrically connected to the data line, and the gate of the switch transistor is electrically connected to the gate line.

2. The back plate according to claim 1, characterized in that: The driving transistor in the 2n-1th pixel structure is a first driving transistor, and the driving transistor in the 2nth pixel structure is a second driving transistor. The power line and the source of the first driving transistor are located in different layers, the power line and the source of the second driving transistor are located in different layers, and the power line is connected to the source of the first driving transistor and the source of the second driving transistor through a via.

3. The back plate according to claim 2, characterized in that: The source of the first driving transistor and the source of the second driving transistor are located in the same layer, the source of the first driving transistor is connected to the source of the second driving transistor, and the position where the power line is connected to the source through a via is the position where the source of the first driving transistor and the source of the second driving transistor are connected.

4. The back plate according to claim 1, characterized in that: The gate line has a first protrusion, the data line has a second protrusion, the gate of the switch transistor is the first protrusion, and the source of the switch transistor is the second protrusion; the width direction of the channel of the active layer pattern of the switch transistor is perpendicular to the width direction of the channel of the drive transistor; The drain of the switch transistor also includes an extension portion connected to the drain, the extension portion extends from the direction of the switch transistor to the direction of the power line, and the drain of the switch transistor is connected to the gate of the driving transistor through the extension portion.

5. The back plate according to claim 1, characterized in that: The driving transistor in the 2n-1th pixel structure and the driving transistor in the 2nth pixel structure are located symmetrically in the pixel region with respect to a power supply line between the 2n-1th pixel structure and the 2nth pixel structure; Positions of the switch transistor in the 2n-1th pixel structure and the switch transistor in the 2nth pixel structure in the pixel region are symmetrical about a power line between the 2n-1th pixel structure and the 2nth pixel structure.

6. The back plate according to claim 1, characterized in that: The length of the gate of the driving transistor in the column direction is greater than the length of the active layer pattern of the driving transistor in the column direction, so that the gate of the driving transistor extends in the direction of the switching transistor relative to the active layer, and the extended portion of the gate has no overlapping area with the projection of the active layer pattern of the driving transistor on the substrate; The drain electrode of the driving transistor is electrically connected to the pixel electrode through the capacitor electrode layer; The capacitor electrode layer and the extended portion of the gate have an overlapping area on the base substrate, and the capacitor electrode layer at least forms a capacitor with the extended portion of the gate.

7. The back plate according to claim 6, characterized in that: The capacitor electrode layer is located between the drain electrode of the driving transistor and the pixel electrode, a first insulating layer is provided between the capacitor electrode layer and the drain electrode of the driving transistor, and a second insulating layer is provided between the capacitor electrode layer and the pixel electrode; The capacitor electrode layer is electrically connected to the drain electrode of the driving transistor through a via hole provided in the first insulating layer, and the capacitor electrode layer is electrically connected to the pixel electrode through a via hole provided in the second insulating layer; The orthographic projection of the capacitor electrode layer on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate have an overlapping area.

8. The back plate according to claim 7, characterized in that: The power line and the capacitor electrode layer are located in the same layer and are made of the same material.

9. The back plate according to claim 6 or 7, characterized in that: It also includes a first insulating layer, an organic resin layer, a conductive layer and a third insulating layer which are sequentially arranged between the drain electrode of the driving transistor and the capacitor electrode layer; The orthographic projection of the organic resin layer on the base substrate covers the orthographic projection of the active layer pattern on the base substrate, and the orthographic projection of the conductive layer on the base substrate covers the orthographic projection of the active layer pattern on the base substrate; The drain electrode of the driving transistor is electrically connected to the conductive layer through a via hole penetrating the first insulating layer and the organic resin layer, and the conductive layer is electrically connected to the capacitor electrode layer through a via hole penetrating the third insulating layer.

10. The back plate according to claim 1, wherein: The gate of the driving transistor, the gate of the switching transistor and the gate line are arranged on the same layer on the substrate and are made of the same material; the active layer pattern of the driving transistor and the active layer pattern of the switching transistor are arranged above the film layer where the gate is located; the source and drain of the driving transistor, and the source and drain of the switching transistor are arranged on the same layer; the power line and the capacitor electrode layer are arranged on the same layer, the power line is located above the source of the driving transistor and is connected to the source of the driving transistor through a via hole, and the pixel electrode is arranged above the power line and the capacitor electrode layer; The drain electrode of the driving transistor is electrically connected to the pixel electrode through the capacitor electrode layer; The orthographic projection of the capacitor electrode layer on the substrate and the orthographic projection of the extended portion of the gate of the driving transistor relative to the active layer on the substrate have an overlapping area to form a capacitor; The drain of the switch transistor is electrically connected to the gate of the drive transistor through an extension portion extending toward the power line.

11. The back plate according to claim 10, characterized in that: Two adjacent columns of pixel structures in the same row are mirror-imaged and arranged on both sides of the power line; Two pixel structures mirror-set on both sides of the power line share one power line, and the power line is located between two mirror-set driving transistors; sources of the two mirror-set driving transistors extend from one pixel structure to another pixel structure along a row direction; The power line further includes a first conductive connection portion, and a source electrode of a first driving transistor of the two driving transistors in the mirror-image arrangement is electrically connected to a source electrode of a second driving transistor of the two driving transistors in the mirror-image arrangement via a second conductive connection portion; The orthographic projection of the first conductive connection portion on the base substrate at least partially overlaps with the orthographic projection of the second conductive connection portion on the base substrate, and the first conductive connection portion is electrically connected to the second conductive connection portion through a via hole so that the source of the driving transistor is electrically connected to the power line.

12. The back plate according to claim 1, 10 or 11, characterized in that: Also includes: An isolation layer disposed above the active layer pattern of the driving transistor, the isolation layer being used to isolate the influence of impurities on the active layer pattern of the driving transistor; The isolation layer is a single-layer isolation layer or a multi-layer isolation layer, and the single-layer isolation layer or the multi-layer isolation layer includes at least one of an organic resin layer, a metal layer or a metal oxide active layer; the multi-layer isolation layer is a double-layer isolation layer, and the double-layer isolation layer includes an organic resin layer and a metal oxide active layer sequentially arranged above the active layer; The metal oxide active layer or metal layer in the isolation layer includes an isolation portion disposed above the active layer pattern of the driving transistor of each pixel structure; The isolation parts are independent of each other, or the isolation parts are arranged in one piece.

13. The back plate according to claim 11, characterized in that It also includes a first insulating layer, an organic resin layer, a conductive layer containing metal and a third insulating layer which are sequentially arranged between the drain electrode of the driving transistor and the capacitor electrode layer; a second insulating layer is arranged between the capacitor electrode layer and the pixel electrode; The organic resin layer and the conductive layer serve as protective layers for the active layer pattern of the driving transistor, and are used to block hydrogen; the orthographic projection of the organic resin layer on the base substrate covers the orthographic projection of the active layer pattern of the driving transistor on the base substrate, and the orthographic projection of the conductive layer on the base substrate covers the orthographic projection of the active layer pattern of the driving transistor on the base substrate; The vias between the first conductive connection portion and the second conductive connection portion include a first via, a second via, and a third via; The first via hole is a via hole penetrating the first insulating layer, the second via hole is a via hole penetrating the organic resin layer, and the third via hole is a via hole penetrating the third insulating layer; An orthographic projection of the first via hole on the base substrate, an orthographic projection of the second via hole on the base substrate, and an orthographic projection of the third via hole on the base substrate at least partially overlap.

14. The back plate according to claim 13, characterized in that: The orthographic projection of the first via hole on the base substrate is within the orthographic projection of the second via hole on the base substrate, and the orthographic projection of the third via hole on the base substrate is within the orthographic projection of the second via hole on the base substrate.

15. The back plate according to claim 14, characterized in that: The conductive layer includes a plurality of mutually independent conductive patterns; the orthographic projections of the conductive patterns on the base substrate cover a pixel region where a pixel structure is arranged.

16. The back plate according to claim 1, characterized in that: It comprises a gate metal layer, an active layer, an etching stop layer, a source-drain metal layer, a capacitor electrode layer and a pixel electrode layer which are sequentially arranged on the substrate; the etching stop layer is used to protect the active layer from being etched; The active layer is electrically connected to the source-drain metal layer through a via hole penetrating the etch stop layer; The gate of the driving transistor and the gate of the switching transistor are arranged on the gate metal layer; the active layer pattern of the driving transistor and the active layer pattern of the switching transistor are arranged on the active layer; The source of the driving transistor, the drain of the driving transistor, the source of the switch transistor and the drain of the driving transistor are all arranged on the source-drain metal layer; the power line is arranged on the capacitor electrode layer, and the pixel electrode is arranged on the pixel electrode layer; The pixel electrodes included in different pixel structures are independent of each other; The drain of the driving transistor is electrically connected to the pixel electrode through the capacitor electrode layer, and the orthographic projection of the capacitor electrode layer on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate have an overlapping area; The drain of the switch transistor is electrically connected to the gate of the drive transistor through an extension portion extending toward the power line.

17. The back plate according to claim 1, characterized in that: The back plate is a back plate of a 3D printing system, and the pixel electrode is an anode in the 3D printing system.

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