Packaging method of cis chip

Abstract

This invention provides a packaging method for a CIS chip, including mounting the CIS chip onto a substrate; attaching a cover plate to the photosensitive area of ​​the CIS chip; connecting the pads and pins using bonding wires; placing a mold on the substrate, with the CIS chip and pins positioned within the mold; injecting adhesive or molding compound into the mold to cover the exposed chip surface, bonding wires, and exposed CIS chip surface within the mold; removing the mold, followed by delamination and die picking to complete the packaging of the CIS chip. The substrate is flat, eliminating the support structure. The method of placing the mold on the substrate and positioning the CIS chip and pins within the mold, and injecting adhesive or molding compound into the mold to cover the exposed chip surface, bonding wires, and exposed CIS chip surface within the mold, eliminates cavities, improves overall bonding strength, and creates thinning marks at the chip surface boundaries, eliminating the need for thick-cutting and thus improving warpage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to a packaging method for a CIS chip. Background Technology

[0002] Figure 1 This is a schematic diagram of the packaging structure in the prior art. Figure 2 This is a flowchart illustrating the packaging process of existing technologies. (Example:) Figure 1 As shown, the casing 100 is generally frame-shaped. During packaging, the chip can be connected to the bottom surface inside the casing 100 using silver paste. Multiple pads are provided around the edges of the chip 102 surface, and multiple pins 101 are correspondingly arranged around the edges of the bottom surface inside the casing 100. Bonding wires 103 connect the pads and corresponding pins 101, and a glass cover 104 is placed over the casing 100.

[0003] like Figure 2 As shown, the existing packaging process includes chip thinning, dicing, die mounting, bonding, and glass encapsulation, and its applications are as follows: Figure 1 The aforementioned shell 100, and ultimately formed as shown Figure 1 The packaging structure is shown.

[0004] In the aforementioned packaging technologies, the frame contains supports, cavities, etc., resulting in poor overall bonding strength. The bonding wires are prone to breakage when suspended. Furthermore, if a separate shell is used, the unit price is high, and the mold opening cost is relatively large. If a long strip substrate is used, the cutting stress is large, which can easily cause warping and affect the subsequent surface mount technology (SMT) process.

[0005] Therefore, it is necessary to provide a novel packaging method for CIS chips to solve the aforementioned problems existing in the prior art. Summary of the Invention

[0006] The purpose of this invention is to provide a packaging method for CIS chips that reduces cavities, improves overall bonding strength, and eliminates the need for thick-cutting, thereby improving warpage.

[0007] To achieve the above objectives, the packaging method for the CIS chip of the present invention includes:

[0008] The system provides a CIS chip, a cover plate, a substrate, and a mold. The CIS chip has multiple pads formed on it. The substrate is flat and has at least one chip bit that matches the CIS chip. Thinning marks are formed at the boundaries of the chip bit. Pins corresponding to the pads are formed on the chip bit. The mold is flat and has a through-hole forming on it. The shape of the through-hole matches the chip bit. The thickness of the mold is greater than the thickness of the CIS chip.

[0009] The CIS chip is mounted on the substrate;

[0010] The cover plate is attached to the photosensitive area of ​​the CIS chip;

[0011] The connection between the pad and the pin is achieved by bonding wire;

[0012] The mold is placed on the substrate, and the CIS chip and its pins are placed within the mold.

[0013] Inject adhesive or molding compound into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface located within the mold.

[0014] The mold is removed, and then the film is peeled off and the wafer is picked up to complete the packaging of the CIS chip.

[0015] The beneficial effects of the packaging method are as follows: the substrate is flat, eliminating the support structure, and the mold is placed on the substrate, with the CIS chip and pins placed within the mold. Glue or molding compound is injected into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface within the mold, eliminating cavities and improving overall bonding strength. Thinning marks are formed at the boundaries of the chip, eliminating the need for thick-cutting, thereby improving warpage.

[0016] Optionally, the chip location has a chip bonding position adapted to the CIS chip, and the pins are located outside the chip bonding position. The step of attaching the CIS chip to the substrate includes: applying adhesive to the chip bonding position, and then covering the CIS chip onto the chip bonding position. Its advantage is that it facilitates precise positioning of the CIS chip.

[0017] Optionally, the connection between the pad and the pin via bonding wire includes: using a wire bonding process to connect the pad and the pin via bonding wire.

[0018] Optionally, the packaging method of the CIS chip further includes: forming a plurality of the CIS chips on a semiconductor substrate, and forming a plurality of independent CIS chips by dicing.

[0019] Optionally, the packaging method of the CIS chip further includes: forming a plurality of the CIS chips on a semiconductor substrate, then thinning the substrate of the CIS chips, and then dicing to form a plurality of independent CIS chips.

[0020] Optionally, injecting adhesive or molding compound into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface within the mold includes: injecting adhesive or molding compound into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface within the mold, until only the upper surface of the cover plate is exposed.

[0021] Optionally, the packaging method for the CIS chip further includes forming the thinning marks at the boundaries of the chip bits by etching or stamping.

[0022] Optionally, the packaging method for the CIS chip further includes: forming a mold position penetrating the mold by etching on the mold.

[0023] Optionally, the cover plate is made of glass.

[0024] Optionally, the substrate is made of ceramic. Attached Figure Description

[0025] Figure 1 A diagram of the packaging structure in the prior art;

[0026] Figure 2 This is a schematic diagram of the packaging process in existing technologies;

[0027] Figure 3 This is a schematic diagram of the substrate structure in some embodiments of the present invention;

[0028] Figure 4 This is a schematic diagram of the mold structure in some embodiments of the present invention;

[0029] Figure 5 This is a flowchart of the CIS chip packaging method of the present invention;

[0030] Figure 6 This is a cross-sectional view of the structure formed after step S1 of the present invention;

[0031] Figure 7 This is a cross-sectional view of the structure formed after step S2 of the present invention;

[0032] Figure 8This is a cross-sectional view of the structure formed after step S3 of the present invention;

[0033] Figure 9 This is a cross-sectional view of the structure formed after step S4 of the present invention;

[0034] Figure 10 This is a cross-sectional view of the structure formed after step S5 of the present invention;

[0035] Figure 11 This is a cross-sectional view of the structure formed after removing the mold in step S6 of the present invention;

[0036] Figure 12 This is a cross-sectional view of the CIS chip packaging structure of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0038] To address the problems existing in the prior art, embodiments of the present invention provide a substrate, the substrate being flat and including at least one chip bit, the chip bit having pins, and a thinning mark being provided at the boundary of the chip bit. The thinning mark is formed by etching or stamping the substrate to facilitate the removal of the chip bit from the substrate.

[0039] In some embodiments, the chip location has a chip bonding area, and the pin is located outside the chip bonding area.

[0040] In some embodiments, the substrate has a separate trace that connects to the outside of the substrate to enable external pin routing.

[0041] Figure 3 This is a schematic diagram of the substrate structure in some embodiments of the present invention. (Refer to...) Figure 3 The substrate 200 is flat and has 6 chip positions 201 adapted to the CIS chip. Each chip position 201 has pins 202 that correspond one-to-one with the pads of the CIS chip, and thinning marks 203 are provided at the boundary of the chip position.

[0042] Reference Figure 3 The chip position 201 is provided with a chip bonding position 204 adapted to the CIS chip. The pin 202 is located outside the chip bonding position 204 and is arranged around the chip bonding position 204.

[0043] The present invention also provides a mold, the mold being flat, and having through-hole mold positions formed on the mold, the shape of which is adapted to the chip position. The mold positions are formed by etching on the mold.

[0044] Figure 4 This is a schematic diagram of the mold structure in some embodiments of the present invention. (Refer to...) Figure 4 The mold 300 is flat, and a mold position 301 is formed on the mold 300 that penetrates the mold. The shape of the mold position 301 is adapted to the chip position, and the thickness of the mold 300 is greater than the thickness of the CIS chip.

[0045] In some embodiments, the shape formed by the die on one side of the die is exactly the same size and shape as the shape formed by the thinning mark of one of the chip bits.

[0046] Figure 5 This invention relates to a packaging method for a CIS chip. (See reference...) Figure 5 The packaging method for the CIS chip includes the following steps:

[0047] S0: Provides a CIS chip, a cover plate, a substrate, and a mold. The CIS chip has multiple pads formed on it. The substrate is flat and has at least one chip bit that matches the CIS chip. Thinning marks are formed at the boundaries of the chip bit. Pins corresponding to the pads are formed on the chip bit. The mold is flat and has a through-hole forming on it. The shape of the through-hole matches the chip bit. The thickness of the mold is greater than the thickness of the CIS chip.

[0048] S1: The CIS chip is mounted on the substrate;

[0049] S2: Attach the cover plate to the photosensitive area of ​​the CIS chip;

[0050] S3: The connection between the pad and the pin is achieved by bonding wire;

[0051] S4: Cover the substrate with the mold, and place the CIS chip and pins within the mold position;

[0052] S5: Inject adhesive or molding compound into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface located within the mold.

[0053] S6: Remove the mold, then peel off the film and pick up the wafer to complete the packaging of the CIS chip.

[0054] In some embodiments, the peeling process includes peeling off a back film that serves as a support, and the chip picking process includes placing the packaged CIS chip into a corresponding container. The back film is the substrate.

[0055] In some embodiments, a semiconductor substrate is used, such as a silicon substrate, but the invention is not limited thereto. Multiple CIS chips are formed on the silicon substrate.

[0056] In some embodiments, the packaging method of the CIS chip further includes: forming a plurality of the CIS chips on a semiconductor substrate, and forming a plurality of independent CIS chips by dicing.

[0057] In some embodiments, the packaging method of the CIS chip further includes: forming a plurality of the CIS chips on a semiconductor substrate, then thinning the substrate of the CIS chips, and then dicing to form a plurality of independent CIS chips.

[0058] In some embodiments, the chip position is provided with a chip bonding position adapted to the CIS chip, and the pin is located outside the chip bonding position. The step of attaching the CIS chip to the substrate includes: applying adhesive to the chip bonding position, and then covering the chip bonding position with the CIS chip.

[0059] Figure 6 This is a cross-sectional view of the structure formed after step S1 of the present invention. (Refer to...) Figure 6 The CIS chip 400 is attached to the substrate 200 by dispensing and die bonding processes.

[0060] Figure 7 This is a cross-sectional view of the structure formed after step S2 of the present invention. (Refer to...) Figure 7 The cover plate 401 is attached to the photosensitive area on the upper side of the CIS chip 400, wherein the material of the cover plate 401 is glass.

[0061] In some embodiments, the connection between the pad and the pin via bonding wire includes: using a wire bonding process to connect the pad and the pin via bonding wire. Specifically, the wire bonding process includes: heating one end of the bonding wire to melt it into a spherical shape, then attaching the spherical end of the bonding wire to the pad and applying pressure and ultrasound to form a first solder joint, thus connecting the bonding wire to the pad; pulling the bonding wire, then attaching the middle portion of the bonding wire to the pin and applying pressure and ultrasound to form a second solder joint, thus connecting the bonding wire to the pin; and cutting the remaining bonding wire to complete the connection between the pad and the pin via the bonding wire.

[0062] In some embodiments, the bonding wire is a gold wire or an aluminum wire.

[0063] Figure 8 This is a cross-sectional view of the structure formed after step S3 of the present invention. (Refer to...) Figure 8 The pad 402 and the pin 202 are connected by the bonding wire 403.

[0064] Figure 9 This is a cross-sectional view of the structure formed after step S4 of the present invention. (Refer to...) Figure 9 The mold 300 covers the upper side of the substrate 200, and the sidewall of the mold position 301 is aligned with the thinning mark 203.

[0065] In some embodiments, the process specifically includes injecting adhesive or molding compound into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface located within the mold, until only the upper surface of the cover plate is exposed.

[0066] Figure 10 This is a cross-sectional view of the structure formed after step S5 of the present invention. (Refer to...) Figure 10 The molding compound 302 in the mold 301 covers the surface of the exposed chip position (not shown in the figure), the bonding wire 403 and the surface of the exposed CIS chip 400, and the uppermost side of the molding compound 302 is flush with the upper surface of the cover plate 401.

[0067] Figure 11 This is a cross-sectional view of the structure formed after removing the mold in step S6 of the present invention. Figure 11 and Figure 10 The difference is that, Figure 11 The mold 300 is removed, thereby forming a CIS chip packaging structure that is integrally connected with the substrate.

[0068] Figure 12This is a cross-sectional view of the CIS chip packaging structure of the present invention. Forces of opposite directions and perpendicular to the surface of the substrate 200 are applied to the CIS chip packaging structure and the substrate 200 outside the thinning mark 203. Because the substrate 200 at the thinning mark 203 is very thin, the substrate 200 will break and separate at the thinning mark 203, thereby causing the CIS chip packaging structure to separate entirely from the substrate 200, forming an independent CIS chip packaging structure, such as... Figure 12 As shown.

[0069] In some embodiments, the cover plate is made of glass, and the substrate is made of ceramic.

[0070] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A packaging method of a CIS chip, characterized by, include: We provide CIS chips, cover plates, substrates, and molds; The CIS chip has multiple pads formed on it; the substrate is flat and has at least one chip bit that matches the CIS chip, the chip bit has a thinning mark at its boundary, and the chip bit has pins that correspond one-to-one with the pads; the mold is flat and has a mold part that penetrates through it, the shape of the mold part on one side of the mold is exactly the same as the shape and size formed by the thinning mark of the chip bit, and the thickness of the mold is greater than the thickness of the CIS chip; The CIS chip is mounted on the substrate; The cover plate is attached to the photosensitive area of ​​the CIS chip; The connection between the pad and the pin is achieved by bonding wire; The mold is placed on the substrate, and the CIS chip and its pins are placed within the mold. Inject adhesive or molding compound into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface located within the mold. Remove the mold to form a CIS chip package structure that is integrally connected with the substrate; Forces in opposite directions and perpendicular to the substrate surface are applied to the CIS chip packaging structure and the substrate outside the thinning mark, respectively, so that the substrate breaks and separates at the thinning mark, thereby separating the CIS chip packaging structure from the substrate as a whole to form an independent CIS chip packaging structure.

2. The CIS chip packaging method according to claim 1, wherein, The chip has a chip mounting position adapted to the CIS chip, and the pin is located outside the chip mounting position. The step of mounting the CIS chip onto the substrate includes: Apply adhesive to the chip mounting position, and then cover the CIS chip onto the chip mounting position.

3. The packaging method for a CIS chip according to claim 1, characterized in that, The connection between the pad and the pin via bonding wire includes: The connection between the pads and the pins is achieved by using a wire bonding process, with bonding wires.

4. The packaging method for a CIS chip according to claim 1, characterized in that, Also includes: Multiple CIS chips are formed on a semiconductor substrate, and then diced to form multiple independent CIS chips.

5. The packaging method for a CIS chip according to claim 1, characterized in that, Also includes: Multiple CIS chips are formed on a semiconductor substrate, then the substrate of the CIS chips is thinned, and then dicing is performed to form multiple independent CIS chips.

6. The packaging method for a CIS chip according to claim 1, characterized in that, The process of injecting adhesive or molding compound into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface located within the mold includes: Inject adhesive or molding compound into the mold to cover the exposed chip surface, the bonding wire, and the exposed CIS chip surface located within the mold, until only the upper surface of the cover plate is exposed.

7. The packaging method for a CIS chip according to claim 1, characterized in that, Also includes: The thinning marks are formed by etching or stamping at the boundaries of the chip bits.

8. The packaging method for a CIS chip according to claim 1, characterized in that, Also includes: A mold position is formed through the mold by etching.

9. The packaging method for a CIS chip according to claim 1, characterized in that, The cover plate is made of glass.

10. The packaging method for a CIS chip according to claim 1, characterized in that, The substrate is made of ceramic.

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