Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of reducing the possibility of occurrence of a failure. The semiconductor device of the embodiments includes a first metal member, a semiconductor element, and a second metal member. The first metal member is electrically connected to a first terminal. The semiconductor element includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, and a second electrode. The second metal member is provided on the second electrode, is electrically connected to the second electrode, and is electrically connected to a second terminal. The semiconductor element includes a first portion overlapping the second metal member in a first direction and a second portion not overlapping the second metal member in the first direction. The length of the first semiconductor region between adjacent gate electrodes in a second direction in the second portion is longer than the length of the first semiconductor region between adjacent gate electrodes in the second direction in the first portion.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2020-153274 (Filing Date: September 11, 2020). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0004] A semiconductor device such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) is used for power conversion and the like. For a semiconductor device, it is preferable that a breakdown does not occur. SUMMARY

[0005] Embodiments of the present application provide a semiconductor device in which a possibility of a breakdown occurring can be reduced.

[0006] A semiconductor device according to an embodiment includes a first metal component, a semiconductor element, and a second metal component. The first metal component is electrically connected to a first terminal. The semiconductor element includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, and a second electrode. The first electrode is disposed on the first metal component and is electrically connected to the first metal component. The first semiconductor region is disposed on the first electrode. The second semiconductor region is disposed on the first semiconductor region. The third semiconductor region is disposed on the second semiconductor region. The gate electrode is positioned opposite a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first metal component toward the first electrode. The second electrode is disposed on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region and the third semiconductor region. Multiple second semiconductor regions, third semiconductor regions, and gate electrodes are disposed in the second direction. The second metal component is disposed on the second electrode, electrically connected to the second electrode, and electrically connected to a second terminal. The semiconductor element includes: a first portion for which the second electrode is disposed, overlapping the second metal component in the first direction; and a second portion for which the second electrode is disposed, not overlapping the second metal component in the first direction. The length of the first semiconductor region between adjacent gate electrodes in the second portion in the second direction is longer than the length of the first semiconductor region between adjacent gate electrodes in the first portion in the second direction. Attached Figure Description

[0007] Figure 1 This is a top view showing the semiconductor device according to the first embodiment.

[0008] Figure 2 yes Figure 1 Sectional view II-II.

[0009] Figure 3 yes Figure 1 Sectional view III-III.

[0010] Figure 4 This is a top view showing the semiconductor device according to the first embodiment.

[0011] Figure 5 yes Figure 4 VV sectional view.

[0012] Figure 6 It means Figure 4a plan view of a portion VI of FIG. 1.

[0013] Figure 7 is a sectional view of a portion of a semiconductor device of a modification example of the first embodiment.

[0014] Figure 8 is a sectional view of a portion of a semiconductor device of a modification example of the first embodiment.

[0015] Figure 9 is a sectional view of a portion of a semiconductor device of a modification example of the first embodiment.

[0016] Figure 10 is a sectional view of a portion of a semiconductor device of the second embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, each embodiment of the present application will be described with reference to the drawings.

[0018] The drawings are schematic or conceptual, and the relationship between the thickness and width of each portion, the ratio of sizes among the portions, and the like, are not necessarily the same as that of the actual one. Even in cases where the same portion is shown in different drawings, the dimensions, the ratios, and the like, are not necessarily the same.

[0019] In the present application specification and each drawing, the same element is marked by the same reference sign and detailed description is appropriately omitted.

[0020] In the following description and drawings, n + , n, n - and p + , p marks indicate the relative levels of impurity concentrations. That is, the mark annotated with "+" indicates that the impurity concentration is relatively high compared to the mark not annotated with either of "+" and "-", and the mark annotated with "-" indicates that the impurity concentration is relatively low compared to the mark not annotated with either. In the case where each region includes both p-type impurities and n-type impurities, these marks indicate the relative levels of net impurity concentrations after these impurities compensate for each other.

[0021] As for each embodiment described below, each semiconductor region can be implemented by reversing the p-type and the n-type.

[0022] (First Embodiment)

[0023] Figure 1 is a plan view of a semiconductor device of the first embodiment.

[0024] Figure 2 is a II-II sectional view of FIG. 1. Figure 1 Figure 3 is a II-II sectional view of FIG. 1. Figure 1 ​a III-III sectional view.

[0025] As shown in Figures 1-3 , the semiconductor device 100 includes a first metal member 1, a second metal member 2, a third metal member 3, a sealing portion 5, and a semiconductor element 10. In Figure 1 , the sealing portion 5 is omitted.

[0026] As shown in Figure 2 and Figure 3 , the semiconductor element 10 includes a first electrode 11, a second electrode 12, a third electrode 13, and a semiconductor layer 20.

[0027] In the description of the embodiments, an XYZ orthogonal coordinate system is used. A direction from the first metal member 1 toward the first electrode 11 is set as a Z direction (a first direction). Two directions perpendicular to the Z direction and orthogonal to each other are set as an X direction (a second direction) and a Y direction (a third direction). In addition, for convenience of description, the direction from the first metal member 1 toward the first electrode 11 is referred to as "up", and the opposite direction thereof is referred to as "down". These directions are based on the relative positional relationship of the first metal member 1 and the first electrode 11, and are independent of the direction of gravity.

[0028] The first metal member 1 is provided on a lower surface of the semiconductor device 100. The first metal member 1 is electrically connected to a first terminal la. For example, the first terminal la is formed integrally with the first metal member 1. The first metal member 1 and the first terminal la can be constituted by different members. For example, as shown in Figure 1 , a plurality of the first terminals la are provided in the X direction, and each of the first terminals la extends in the Y direction.

[0029] The semiconductor element 10 is, for example, a MOSFET. The first electrode 11 is provided on the first metal member 1 and is electrically connected to the first metal member 1. The semiconductor layer 20 is provided on the first electrode 11. The second electrode 12 and the third electrode 13 are provided on the semiconductor layer 20. The third electrode 13 is separated from and electrically separated from the second electrode 12.

[0030] The second metal member 2 is provided on the second electrode 12 and is electrically connected to the second electrode 12. The second metal member 2 is electrically connected to a second terminal 2a. For example, as shown in Figure 1 , a plurality of the second terminals 2a are provided in the X direction, and each of the second terminals 2a extends in the Y direction.

[0031] The third metal member 3 is provided on the third electrode 13 and is electrically connected to the third electrode 13. The third metal member 3 is electrically connected to a third terminal 3a.

[0032] In Figure 2 and Figure 3In the illustrated example, the first electrode 11 to the third electrode 13 are electrically connected to the first metal member 1 to the third metal member 3 via the bonding portions 51 to 53, respectively. The second metal member 2 and the third metal member 3 are electrically connected to the second terminal 2a and the third terminal 3a via the bonding portions 54 and 55, respectively. The example is not limited to this, and one member can be crimped to the other member without the intervening of the connecting portion. The second metal member 2 can be formed integrally with the second terminal 2a. The third metal member 3 can be formed integrally with the third terminal 3a.

[0033] The shapes of the first metal member 1, the second metal member 2, and the third metal member 3 are not limited to the illustrated example, and can be appropriately changed according to the use of the semiconductor device 100. In addition, the number or the shape of each of the first terminal 1a, the second terminal 2a, and the third terminal 3a can be appropriately changed.

[0034] The sealing portion 5 covers the upper surface and the side surface of the first metal member 1, the lower surface and the side surface of the second metal member 2, the third metal member 3, and the semiconductor element 10, and seals the semiconductor element 10. A part of each of the first terminal 1a, the second terminal 2a, and the third terminal 3a is not covered by the sealing portion 5, and is exposed to the outside.

[0035] Figure 4 is a plan view of the semiconductor device according to the first embodiment.

[0036] Figure 5 is a V-V cross-sectional view of Figure 4

[0037] In Figure 4 , the second metal member 2 and the sealing portion 5 are omitted. As Figure 4 indicated, the semiconductor element 10 includes a first portion Po1 and a second portion Po2. The second electrode 12 is provided in the first portion Po1 and the second portion Po2. The first portion Po1 overlaps the second metal member 2 in the Z direction. The first portion Po1 is in contact with the second metal member 2 via the bonding portion 52. The second portion Po2 does not overlap the second metal member 2 in the Z direction. For example, the second portion Po2 is located around the first portion Po1 along the X-Y plane.

[0038] As Figure 5 indicated, the semiconductor layer 20 includes an n - type (first conductive type) semiconductor region 21 (first semiconductor region), a p-type (second conductive type) semiconductor region 22 (second semiconductor region), an n + type semiconductor region 23 (third semiconductor region), an n + type semiconductor region 24, a p + type semiconductor region 25, and a gate electrode 30. ​

[0039] n + An n-type semiconductor region 24 is provided on the first electrode 11 and is electrically connected to the first electrode 11. - An n-type semiconductor region 21 is provided on the n + Type semiconductor region 24. The n - Type semiconductor region 21 is electrically connected to the first electrode 11 via the n + Type semiconductor region 24. The n - The n-type impurity concentration in the n + Type semiconductor region 24 is lower than the n-type impurity concentration in the n

[0040] A p-type semiconductor region 22 is provided on the n - Type semiconductor region 21. The p + Type semiconductor region 23 and a p + Type semiconductor region 25 is provided on the p-type semiconductor region 22. The p + Type semiconductor region 25 has a higher p-type impurity concentration than the p-type impurity concentration in the p-type semiconductor region 22.

[0041] The gate electrode 30 opposes a part of the n - Type semiconductor region 21, the p-type semiconductor region 22, and the n + Type semiconductor region 23 via the gate insulating layer 31 in the X direction. The gate electrode 30 is electrically connected to the third electrode 13.

[0042] The p-type semiconductor region 22, the n + Type semiconductor region 23, the n + Type semiconductor region 24, the p + Type semiconductor region 25, and the gate electrode 30 are each provided with a plurality in the X direction. The first portion Po1 and the second portion Po2 are each provided with a plurality of the p-type semiconductor regions 22, a plurality of the n + Type semiconductor regions 23, a plurality of the n + Type semiconductor regions 24, a plurality of the p + Type semiconductor regions 25, and a plurality of the gate electrodes 30. Each of the p-type semiconductor regions 22, each of the n + Type semiconductor regions 23, each of the n + Type semiconductor regions 24, each of the p + Type semiconductor regions 25, and each of the gate electrodes 30 extend in the Y direction.

[0043] The second electrode 12 is electrically connected to the plurality of p-type semiconductor regions 22 and the plurality of n + Type semiconductor regions 23 in the first portion Po1 and the second portion Po2.

[0044] Figure 5The length L1 shown is the n between adjacent gate electrodes 30 in the X direction in the first part Po1. - The length of the semiconductor region 21 in the X direction. The length L2 is the distance between adjacent gate electrodes 30 in the X direction within the second part Po2. - The length of the semiconductor region 21 in the X direction is L2, which is longer than L1. For example, the spacing P2 of the plurality of gate electrodes 30 in the second portion Po2 in the X direction is longer than the spacing P1 of the plurality of gate electrodes 30 in the X direction in the first portion Po1. The spacing corresponds to the distance between the centers of adjacent gate electrodes 30 in the X direction.

[0045] Figure 6 It means Figure 4 Top view of part VI.

[0046] exist Figure 6 The second metal component 2, sealing part 5, second electrode 12, p-type semiconductor region 22, and n-type semiconductor region 22 are omitted. + Type semiconductor region 23 and p + Type semiconductor region 25.

[0047] The gate electrode 30, located in the second portion Po2, is electrically connected to the third electrode 13 via a gate wiring (not shown) disposed on the outer periphery of the semiconductor element 10. For example, as... Figure 6 As shown, a connection portion 30c extending in the X direction is provided in the semiconductor layer 20. The gate electrode 30 provided in the first portion Po1 is electrically connected to the gate electrode 30 provided in the second portion Po2 via the connection portion 30c.

[0048] The operation of the semiconductor device 100 will be explained.

[0049] With a positive voltage applied to the first electrode 11 relative to the second electrode 12, a voltage exceeding a threshold is applied to the gate electrode 30 via the third electrode 13. This forms a channel (inversion layer) in the p-type semiconductor region 22, and the semiconductor element 10 becomes conductive. Electrons flow from the second electrode 12 to the first electrode 11 through the channel. That is, current flows from the first electrode 11 to the second electrode 12. Subsequently, if the voltage applied to the gate electrode 30 falls below the threshold, the channel in the p-type semiconductor region 22 disappears, and the semiconductor element 10 becomes cut off.

[0050] An example of the materials used in each component of the semiconductor device 100 will be described.

[0051] The first metal member 1, the second metal member 2, the third metal member 3, the first terminal la, the second terminal 2a, and the third terminal 3a include a metal such as copper. The first electrode 11, the second electrode 12, and the third electrode 13 include a metal such as aluminum. n - The p-type semiconductor region 22, the n + The p-type semiconductor region 23, the n + The p-type semiconductor region 24, and the p + The p-type semiconductor region 25 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. In the case where silicon is used as a semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The gate electrode 30 includes a conductive material such as polysilicon. An impurity can be added to the conductive material. The gate insulating layer 31 includes an insulating material such as silicon oxide. The bonding portions 51 to 55 include a metal such as tin, antimony, silver, or copper.

[0052] Effects of the embodiments are described.

[0053] When the semiconductor element 10 becomes an on state, current flows through the semiconductor layer 20. When current flows through the semiconductor layer 20, heat is generated. The heat generated in the semiconductor layer 20 is mainly transferred to the first metal member 1 and the second metal member 2 via the first electrode 11 and the second electrode 12, and is discharged from the semiconductor device 100.

[0054] As Figure 4 shown, the semiconductor element 10 includes a first portion Po1 and a second portion Po2. The first portion Po1 overlaps the second metal member 2 in the Z direction. Therefore, heat generated in the first portion Po1 is easily discharged to the second metal member 2. The second portion Po2 does not overlap the second metal member 2 in the Z direction. Therefore, heat generated in the second portion Po2 is difficult to be discharged to the second metal member 2 as compared with heat generated in the first portion Po1. When the semiconductor element 10 is operated, the temperature of the second portion Po2 becomes higher than the temperature of the first portion Po1.

[0055] When the semiconductor element 10 is in an on state, if current is excessively concentrated in a part of the channel, the semiconductor element 10 can be destroyed. When the temperature of the second portion Po2 is higher than the temperature of the first portion Po1, the resistance of the semiconductor region in the second portion Po2 is lower than the resistance of the semiconductor region in the first portion Po1. Due to the difference in resistance, the current density flowing in the second portion Po2 is larger than the current density flowing in the first portion Po1. In particular, when viewed in the Z direction, the area of the second portion Po2 is smaller than the area of the first portion Po1. Therefore, current is easily concentrated to flow to the second portion Po2. Due to the concentration of current to the second portion Po2, the temperature of the second portion Po2 rises, and the semiconductor element 10 can be destroyed.

[0056] In the semiconductor device 100 of the embodiment, such as Figure 5 As shown, the gate electrodes 30 in the second part Po2 are n apart from each other. - The length L2 of the semiconductor region 21 is greater than the n-th distance between the gate electrodes 30 in the first portion Po1. - The length L1 of the semiconductor region 21 is longer. For example, the spacing P2 of the gate electrodes 30 in the second part Po2 is longer than the spacing P1 of the gate electrodes 30 in the first part Po1. Therefore, the number of gate electrodes 30 per unit area in the second part Po2 is less than the number of gate electrodes 30 per unit area in the first part Po1.

[0057] Therefore, when the semiconductor element 10 is in the ON state, the resistance per unit area in the second portion Po2 is higher than the resistance per unit area in the first portion Po1. Due to the increased resistance of the second portion Po2, current is less likely to concentrate in the second portion Po2 when the semiconductor element 10 is in the ON state. For example, the current flows dispersedly to both the first portion Po1 and the second portion Po2. Alternatively, the current mainly flows to the first portion Po1. According to the embodiment, the possibility of damage to the semiconductor element 10 due to current concentration in the second portion Po2 can be reduced. The safe operating area (SOA) of the semiconductor element 10 can be improved.

[0058] In particular, the area of ​​the first part Po1 in the XY plane is larger than the area of ​​the second part Po2 in the XY plane. Therefore, even if the current mainly flows to the first part Po1, the current concentration can be suppressed compared to the case where the current mainly flows to the second part Po2.

[0059] Here, two reference examples can be given as semiconductor devices capable of suppressing current concentration in the second part Po2. In the semiconductor device of the first reference example, n is not provided in the second part Po2. + The semiconductor region 23 or gate electrode 30. In the semiconductor device of the second reference example, a plurality of gate electrodes 30 are provided at the same spacing in both the first portion Po1 and the second portion Po2, and in the second portion Po2, a portion of the gate electrodes 30 are electrically connected to the second electrode 12.

[0060] In the semiconductor device of the first reference example, no current flows in the second portion Po2 when the semiconductor element 10 is in the on state. Therefore, the on-resistance of the semiconductor element 10 increases. According to the first embodiment, the possibility of damage to the semiconductor element 10 can be reduced, and the on-resistance of the semiconductor device can be reduced compared to the first reference example.

[0061] According to the semiconductor device of the second reference example, current flows through the second portion Po2, thus reducing the on-resistance of the semiconductor element 10 compared to the first reference example. However, if a gate electrode 30 electrically connected to the second electrode 12 is provided, the n-value between the gate electrodes 30 and each other... - The width (length in the X direction) of the semiconductor region 21 is narrower compared to the first embodiment. When n - When the width of the semiconductor region 21 narrows, the width of the current path also narrows, thus increasing the on-resistance of the semiconductor device. According to the first embodiment, n in the second part Po2... - The length L2 of the semiconductor region 21 is greater than that of n in the first part Po1. - The length L1 of the semiconductor region 21 is longer. If the length L2 is longer than the length L1, the width of the current path between the gate electrodes 30 becomes wider. Therefore, according to the first embodiment, the possibility of damage to the semiconductor element 10 can be reduced, and the on-resistance of the semiconductor device can be reduced compared to the second reference example.

[0062] Figures 7-9 This is a cross-sectional view of a portion of a semiconductor device representing a modified embodiment.

[0063] In semiconductor device 110, such as Figure 7 As shown, the semiconductor layer 20 includes a conductive portion 35. The conductive portion 35 is disposed on n through an insulating layer 35a. - In the semiconductor region 21, the gate electrode 30 is disposed on the conductive portion 35 through an insulating layer 35b.

[0064] An electrical connection EC exists between the second electrode 12 and the conductive portion 35. The potential of the conductive portion 35 is the same as the potential of the second electrode 12. Multiple conductive portions 35 are provided in the X direction. Each conductive portion 35 extends in the Y direction. For example, the Y-direction end of the conductive portion 35 is pulled upwards and contacts the second electrode 12.

[0065] Alternatively, the conductive portion 35 can be electrically connected to the gate electrode 30, and the potential of the conductive portion 35 is the same as the potential of the gate electrode 30. In this case, the insulating layer 35b is not provided, and the conductive portion 35 is in contact with the gate electrode 30.

[0066] When the semiconductor device 110 switches to the off state, the positive voltage applied to the first electrode 11 relative to the second electrode 12 increases. Due to this increase in positive voltage, the depletion layer... - The depletion layer extends from the interface between the n-type semiconductor region 21 and the p-type semiconductor region 22. Additionally, the depletion layer extends from the n-type semiconductor region 22. - The interface between the semiconductor region 21 and the insulating layer 35a is oriented towards n -The semiconductor region 21 is extended. By extending the depletion layer of the latter, the breakdown voltage of the semiconductor device 110 can be improved. Alternatively, while maintaining the breakdown voltage of the semiconductor device 110, the n-type voltage can be increased. - The concentration of n-type impurities in the semiconductor region 21 reduces the on-resistance of the semiconductor device 110.

[0067] Length L2 is longer than length L1. Therefore, the conductive parts 35 in the second part Po2 are n apart from each other. - Type semiconductor region 21, n compared to the conductive portion 35 in the first portion Po1 - The semiconductor region 21 is difficult to deplete. To promote the n in the second part Po2 - Depletion of semiconductor region 21, n in the second part Po2 - The n-type impurity concentration in semiconductor region 21 can also be higher than that in the first part Po1. - The n-type impurity concentration in semiconductor region 21 is low.

[0068] Furthermore, as described above, by providing the conductive portion 35, it is possible to increase n while maintaining the withstand voltage of the semiconductor device 110. - The concentration of n-type impurities in the semiconductor region 21 is reduced. This reduces the on-resistance of the semiconductor element 10a. When the on-resistance of the semiconductor element 10a decreases, heat generation also decreases. Therefore, the current flowing to the semiconductor device 110 can be increased. If the current increases, when a temperature difference arises between the first portion Po1 and the second portion Po2, the current is more likely to concentrate in the second portion Po2. According to the embodiment, even when the conductive portion 35 is provided, the concentration of current in the second portion Po2 can be effectively suppressed, reducing the possibility of damage to the semiconductor element 10a.

[0069] exist Figure 8 In the semiconductor device 120 shown, compared to the semiconductor device 110, the second electrode 12 includes a contact portion 12a. The contact portion 12a protrudes toward the p-type semiconductor region 22. For example, a pair of n-type semiconductor regions 22 are disposed on one p-type semiconductor region 22. + Type semiconductor region 23. Contact portion 12a is located in a pair of n in the X direction. + Between type semiconductor regions 23. p + The p-type semiconductor region 25 is disposed between the p-type semiconductor region 22 and the bottom of the contact portion 12a.

[0070] According to the semiconductor device 120, the second electrode 12 and p + The contact area between the p-type semiconductor regions 25 is increased. This allows for a more stable potential in the p-type semiconductor region 22. For example, in the n-type region... -When avalanche breakdown occurs in the p-type semiconductor region 21, it can suppress potential fluctuations in the p-type semiconductor region 22. This can suppress the operation of parasitic transistors and further reduce the possibility of damage to the semiconductor device 10b.

[0071] Figure 9 The semiconductor device 130 shown includes p + To replace n-type semiconductor region 26 and n-type semiconductor region 27 + Type semiconductor region 24. p + Type semiconductor region 26 is disposed at the first electrode 11 and n - The n-type semiconductor regions 21 are electrically connected to the first electrode 11. The n-type semiconductor region 27 is disposed between the p-type semiconductor regions 21. + Type semiconductor region 26 and n - Between the n-type semiconductor regions 21 and 27. The n-type impurity concentration in the n-type semiconductor region 27 is higher than that in the n-type semiconductor region 28. - The concentration of n-type impurities in the n-type semiconductor region 21.

[0072] The operation of the semiconductor device 130 will be explained.

[0073] In semiconductor device 130, semiconductor element 10c is an IGBT. With a positive voltage applied to the first electrode 11 relative to the second electrode 12, a voltage exceeding a threshold value is applied to the gate electrode 30. This forms a channel (inversion layer) in the p-type semiconductor region 22. Electrons are injected from the second electrode 12 into the n-type semiconductor region 22 via the channel. - Type semiconductor region 21. Holes from p + Type 25 semiconductor region implanted into n - Type semiconductor region 21. Therefore, semiconductor device 130 becomes conductive. In n - In semiconductor region 21, conductivity modulation is generated by the injection of electrons and holes, n - The resistance of the semiconductor region 21 is reduced.

[0074] In the modified semiconductor devices 110-130, similarly to semiconductor device 100, n in the second part Po2 - The length L2 of the type semiconductor region 21 is greater than that of n in the first part Po1. - The length L1 of the semiconductor region 21 is longer. The spacing P2 of the gate electrodes 30 in the second part Po2 is longer than the spacing P1 of the gate electrodes 30 in the first part Po1. Therefore, the possibility of damage to semiconductor devices 10a to 10c due to current concentration can be reduced.

[0075] (Second Implementation)

[0076] Figure 10This is a cross-sectional view showing a portion of the semiconductor device according to the second embodiment.

[0077] The semiconductor device 200 of the second embodiment differs from the semiconductor device 100 in that it includes a semiconductor element 10d instead of a semiconductor element 10a. The semiconductor element 10d is a MOSFET. In the semiconductor element 10d, n in the second portion Po2... + The number of semiconductor regions 23 per unit area is less than n in the first part Po1. + The number of semiconductor regions 23 per unit area.

[0078] For example, such as Figure 10 As shown, in the first part Po1, a pair of n-type semiconductor regions are disposed above a p-type semiconductor region 22. + p-type semiconductor region 23. In the second part Po2, an n-type semiconductor region 22 is disposed above a p-type semiconductor region 22. + Type semiconductor region 23.

[0079] When n is not set + In the region of the semiconductor region 23, no current flows even when a voltage is applied to the gate electrode 30. + The fewer the number of semiconductor regions 23, the less current flows when the semiconductor element 10d is in the ON state. That is, the resistance increases. According to the second embodiment, similarly to the first embodiment, the resistance of the semiconductor regions in the second portion Po2 is higher than the resistance of the semiconductor regions in the first portion Po1. Therefore, when the semiconductor element 10d is in the ON state, current concentration in the second portion Po2 can be suppressed. As a result, the possibility of damage to the semiconductor element 10d due to current concentration in the second portion Po2 can be reduced.

[0080] For example, n in the second part Po2 - The length L2 of the semiconductor region 21 and the n in the first part Po1 - The length L1 of the semiconductor region 21 is the same. The spacing P2 of the gate electrodes 30 in the second part Po2 is the same as the spacing P1 of the gate electrodes 30 in the first part Po1.

[0081] Alternatively, similar to the first embodiment, the length L2 can be longer than the length L1. The spacing P2 can also be longer than the spacing P1. This further suppresses current concentration in the second portion Po2.

[0082] like Figure 10 As shown, p is set in the second part Po2. + The width of the semiconductor region 25 can also be greater than that of the p-type semiconductor region 25 located in the first part Po1. +The width of the p-type semiconductor region 25 is wide. In the second portion Po2, the potential of the p-type semiconductor region 22 is likely to fluctuate. + One side surface of the p-type semiconductor region 25 can also be in contact with the gate insulating layer 31. Thereby, the fluctuation of the potential of the p-type semiconductor region 22 in the second portion Po2 can be further suppressed.

[0083] In the semiconductor device 200 of the second embodiment, the configuration of the semiconductor device of each modification example of the first embodiment can also be applied. For example, in the semiconductor device 200, the conductive portion 35 can also be provided in the semiconductor layer 20. The second electrode 12 can also include the contact portion 12a. It can also be that the semiconductor element 10d is an IGBT, and includes a p-type semiconductor region 26 and an n-type semiconductor region 27 instead of the n-type semiconductor region 24. + + The p-type semiconductor region 26 and the n-type semiconductor region 27 instead of the n-type semiconductor region 24.

[0084] The above illustrates several embodiments of the present application, but these embodiments are suggested as examples, and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, changes, etc. can be made within the scope of the gist of the application. These embodiments and their modifications are included in the scope and gist of the application, and are included in the scope of the application and its equivalents described in the claims. In addition, the above-described embodiments can be implemented in combination with each other.​

Claims

1. A semiconductor device comprising: a first metal member electrically connected to a first terminal; a semiconductor element including: a first electrode provided over the first metal member and electrically connected to the first metal member; a first semiconductor region of a first conductivity type provided over the first electrode; a second semiconductor region of a second conductivity type provided over the first semiconductor region; a third semiconductor region of the first conductivity type provided over the second semiconductor region; a gate electrode facing the first semiconductor region, the second semiconductor region, and the third semiconductor region with a gate insulating layer interposed therebetween in a second direction perpendicular to a first direction from the first metal member toward the first electrode; and a second electrode provided over the second semiconductor region and over the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region, the semiconductor element including a plurality of the second semiconductor regions, the third semiconductor regions, and the gate electrodes provided in the second direction; and a second metal member provided over the second electrode, electrically connected to the second electrode, and electrically connected to a second terminal, wherein the semiconductor element includes: a first portion in which the second electrode is provided and overlaps with the second metal member in the first direction; and a second portion in which the second electrode is provided and does not overlap with the second metal member in the first direction, wherein a length of the first semiconductor region between the gate electrodes adjacent to each other in the second portion in the second direction is longer than a length of the first semiconductor region between the gate electrodes adjacent to each other in the first portion in the second direction.

2. The semiconductor device according to claim 1, wherein a pitch of the gate electrodes in the second portion in the second direction is longer than a pitch of the gate electrodes in the first portion in the second direction.

3. The semiconductor device according to claim 1, wherein a number of the gate electrodes per unit area in the second portion is smaller than a number of the gate electrodes per unit area in the first portion.

4. The semiconductor device according to claim 1, wherein a number of the third semiconductor regions per unit area in the second portion is smaller than a number of the third semiconductor regions per unit area in the first portion. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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