Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a substrate, a gate structure discretely disposed on the substrate, source / drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located between the gate structures; the substrate including a device region and a dummy device region, the extension direction of the dummy device region being perpendicular to the extension direction of the gate structure; removing a portion of the thickness of the gate structure and the interlayer dielectric layer in the dummy device region to form a first opening; removing the gate structure exposed by the first opening to form a second opening; and forming a first blocking layer in the second opening. In this embodiment, the first blocking layer is formed in the second opening. Correspondingly, the first blocking layer is less likely to be formed on the interlayer dielectric layer. Consequently, during the etching of the interlayer dielectric layer to form the source / drain opening exposing the source / drain doped layers, the first blocking layer is less likely to act as a temporary etching stop during the formation of the source / drain opening, which is beneficial for improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction of feature size, semiconductor technology has gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has a stronger control over the channel and can effectively suppress short-channel effects.

[0004] In semiconductor fabrication, it is necessary to form source and drain plugs that connect the source and drain doped layers of the fin field-effect transistor to the subsequent metal interconnect structure. The quality of the formation of the source and drain plugs has a significant impact on the performance of the semiconductor structure. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, a gate structure discretely disposed on the substrate, source / drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located between the gate structures, the substrate including a device region and a dummy device region, the extension direction of the dummy device region being perpendicular to the extension of the gate structure; removing a portion of the thickness of the gate structure and the interlayer dielectric layer in the dummy device region to form a first opening; removing the gate structure exposed by the first opening to form a second opening; forming a first blocking layer in the second opening; etching the interlayer dielectric layer to form a source / drain opening exposing the source / drain doped layers, the extension direction of the source / drain opening being the same as the extension direction of the gate structure.

[0007] Optionally, the step of forming a first blocking layer in the second opening includes: forming a dielectric material layer in the first opening and the second opening; removing the dielectric material layer in the first opening, and leaving the dielectric material layer in the second opening as the first blocking layer.

[0008] Optionally, a dry etching process can be used to remove the dielectric material layer in the first opening.

[0009] Optionally, the step of forming the dielectric material layer includes: conformally covering a silicon nitride material layer in the first opening and the second opening; forming a silicon oxide material layer on the silicon nitride material layer; or, the step of forming the dielectric material layer includes: forming a silicon nitride layer in the first opening and the second opening.

[0010] Optionally, the method for forming the semiconductor structure further includes: after forming the first blocking layer, forming a second blocking layer in the first opening; and during the process of etching the interlayer dielectric layer to form a source / drain opening exposing the source / drain doped layer, also etching the second blocking layer.

[0011] Optionally, in the step of forming a second blocking layer in the first opening, the material of the second blocking layer is the same as the material of the interlayer dielectric layer.

[0012] Optionally, the material of the second blocking layer includes silicon oxide.

[0013] Optionally, in the step of forming the first opening, the distance from the top surface of the interlayer dielectric layer to the top surface of the source / drain doped layer is greater than...

[0014] Optionally, in the step of providing the substrate, a sidewall layer is formed between the gate structure and the interlayer dielectric layer; the method of forming the semiconductor structure includes: after providing the substrate, but before forming the first opening, removing part of the thickness or completely removing the sidewall layer.

[0015] Optionally, in the step of providing the substrate, a sidewall layer is formed between the gate structure and the interlayer dielectric layer; the method of forming the semiconductor structure includes: after forming the first opening and before forming the second opening, removing part of the thickness or completely removing the sidewall layer.

[0016] Optionally, a dry etching process can be used to remove part of the thickness or completely remove the sidewall layer.

[0017] Optionally, a dry etching process can be used to remove the gate structure exposed by the first opening to form a second opening.

[0018] Optionally, the step of removing a portion of the thickness of the gate structure and interlayer dielectric layer in the dummy device region to form the first opening includes: forming a mask layer with grooves on the substrate, the grooves exposing the dummy device region; the method of forming the semiconductor structure further includes: removing the mask layer after forming the second opening.

[0019] Optionally, in the step of providing the substrate, the substrate includes: a channel structure discretely disposed on the substrate, the gate structure spanning the channel structure and covering a portion of the top wall and a portion of the sidewalls of the channel structure; the source / drain doped layer located in the channel structure on both sides of the gate structure; and the dummy device region located between the channel structures.

[0020] This invention also provides a semiconductor structure, comprising: a substrate including a device region and a dummy device region; a gate structure disposed on the substrate, the extension direction of the gate structure being perpendicular to the extension direction of the dummy device region; source / drain doped layers located on both sides of the gate structure; an interlayer dielectric layer located on the source / drain doped layers and covering the sidewalls of the gate structure; a first blocking layer located on the side of the interlayer dielectric layer of the dummy device region for disconnecting the gate structure; and a source / drain opening penetrating the interlayer dielectric layer to expose the source / drain doped layers, the extension direction of the source / drain opening being the same as the extension direction of the gate structure.

[0021] Optionally, the semiconductor structure further includes: a second blocking layer located on the interlayer dielectric layer and the first blocking layer of the dummy device region; the source / drain opening also penetrates the second blocking layer.

[0022] Optionally, the material of the second blocking layer is the same as the material of the interlayer dielectric layer.

[0023] Optionally, the material of the second blocking layer includes silicon oxide.

[0024] Optionally, the semiconductor structure further includes: a channel structure, discretely disposed on the substrate, the gate structure spanning the channel structure and covering a portion of the top wall and a portion of the sidewalls of the channel structure; the source / drain doped layer, located in the channel structure on both sides of the gate structure; and the dummy device region, located between the channel structures.

[0025] Optionally, the distance from the top surface of the interlayer dielectric layer to the top surface of the source / drain doped layer is greater than...

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0027] In the formation method provided by this embodiment of the invention, a portion of the thickness of the gate structure and interlayer dielectric layer in the dummy device region is removed to form a first opening. The gate structure exposed by the first opening is removed to form a second opening. A first blocking layer is formed in the second opening. The first blocking layer is not easily formed on the interlayer dielectric layer. Correspondingly, during the process of etching the interlayer dielectric layer to form the source / drain opening that exposes the source / drain doped layer, the first blocking layer is not etched. That is, during the process of forming the source / drain opening, the first blocking layer is not easily used to temporarily stop the etching, resulting in better formation quality of the source / drain opening. The source / drain opening can expose the source / drain doped layer, resulting in lower contact resistance between the subsequently formed source / drain plug and the source / drain doped layer, which is beneficial to improving the electrical performance of the semiconductor structure. Attached Figure Description

[0028] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0029] Figures 7 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0030] Figure 17 and Figure 18 This is a schematic diagram of the semiconductor structure of the present invention. Detailed Implementation

[0031] The semiconductor structures currently being formed still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure formation method.

[0032] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0033] like Figure 1As shown, a substrate is provided, the substrate including a substrate 1, a channel structure (not shown) discrete on the substrate 1, a gate structure 2 spanning the channel structure, source / drain doped layers 3 located on both sides of the gate structure 2 in the channel structure, and an interlayer dielectric layer 4 located on the side of the gate structure 2. The substrate includes a device region I and a dummy device region II, the dummy device region II being located between the channel structures, and the extension direction of the dummy device region II being perpendicular to the extension of the gate structure 2. A mask layer 5 is formed on the substrate, the mask layer 5 exposing the dummy device region II.

[0034] like Figure 2 As shown, the gate structure 2 and the interlayer dielectric layer 4, with a portion of the thickness of the pseudo-device region I, are etched using the mask layer 5 as a mask to form the first opening 6.

[0035] like Figure 3 As shown, the gate structure 2 exposed by the first opening 6 is removed to form a second opening 7.

[0036] like Figure 4 As shown, a dielectric layer 8 is formed in the first opening 6 and the second opening 7.

[0037] like Figure 5 and Figure 6 As shown, Figure 6 for Figure 5 In the cross-sectional view at AA, the dielectric layer 8 and the interlayer dielectric layer 4 are etched to form a source / drain opening 9 that exposes the source / drain doped layer 3. The extension direction of the source / drain opening 9 is the same as the extension direction of the gate structure 2.

[0038] The source / drain opening 9 is used to form source / drain plugs, which are used to connect multiple source / drain doped layers 3. Typically, the material of the interlayer dielectric layer 4 is silicon oxide, and the material of the dielectric layer 8 is silicon nitride. During the formation of the source / drain opening 9, the etching rate of the dielectric layer 8 in the dummy device region II is lower than that of the interlayer dielectric layer 4. Therefore, the dielectric layer 8 in the dummy device region II is not easy to remove, and the depth of the source / drain opening 9 at the top of the dielectric layer 8 is relatively small. Consequently, the thickness of the source / drain plug formed at the top of the dielectric layer 8 is relatively small, resulting in severe heating of the source / drain plugs formed in the source / drain opening 9. Furthermore, the contact resistance between the source / drain plugs and the source / drain doped layer 3 is relatively large, leading to poor electrical performance of the semiconductor structure.

[0039] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. The method includes providing a substrate, the substrate comprising a base, a gate structure discretely disposed on the substrate, source / drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located between the gate structures. The substrate includes a device region and a dummy device region, the extension direction of the dummy device region being perpendicular to the extension direction of the gate structure. A portion of the thickness of the gate structure and the interlayer dielectric layer in the dummy device region is removed to form a first opening. The gate structure exposed by the first opening is removed to form a second opening. A first blocking layer is formed in the second opening. The interlayer dielectric layer is etched to form a source / drain opening exposing the source / drain doped layers, the extension direction of the source / drain opening being the same as the extension direction of the gate structure.

[0040] In the formation method provided by the technical solution of this invention, a portion of the thickness of the gate structure and interlayer dielectric layer in the dummy device region is removed to form a first opening. The gate structure exposed by the first opening is removed to form a second opening. A first blocking layer is formed in the second opening. Correspondingly, the first blocking layer is not easily formed on the interlayer dielectric layer. Correspondingly, during the process of etching the interlayer dielectric layer to form the source / drain opening that exposes the source / drain doped layer, the first blocking layer is not etched. That is to say, during the process of forming the source / drain opening, the first blocking layer is not easily used to temporarily stop the etching, so that the source / drain opening can expose the source / drain doped layer. This results in a smaller contact resistance between the subsequently formed source / drain plug and the source / drain doped layer, which is beneficial to improving the electrical performance of the semiconductor structure.

[0041] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Figures 7 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0043] refer to Figure 7 A substrate is provided, the substrate including a substrate 100, a gate structure 101 discrete on the substrate 100, source and drain doped layers 102 located on both sides of the gate structure 101, and an interlayer dielectric layer 106 covering the source and drain doped layers 102. The substrate includes a device region I and a dummy device region II, the extension direction of the dummy device region II being perpendicular to the extension of the gate structure 101.

[0044] In the method of forming a semiconductor structure, device region I is used to form a semiconductor device, and the gate structure 101 is subsequently replaced with a metal gate structure. The pseudo-device region II is used to electrically isolate the metal gate structure.

[0045] The substrate 100 provides a process platform for the subsequent formation of semiconductors.

[0046] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0047] The gate structure 101 occupies space for the metal gate structure that will be formed later.

[0048] In this embodiment, the gate structure 101 is a stacked structure. Specifically, the gate structure 101 includes a gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) located on the gate oxide layer.

[0049] In this embodiment, the gate oxide layer is made of silicon oxide, and the pseudo gate layer is made of polysilicon.

[0050] When the semiconductor structure is in operation, the source and drain doped layers 102 provide stress to the channel, thereby increasing the carrier migration rate.

[0051] In this embodiment, the semiconductor structure is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), and the source and drain doped layers 102 serve as the source and drain of the NMOS. When the semiconductor structure is in operation, the source and drain doped layers 102 apply tensile stress to the channel, which can increase the electron migration rate.

[0052] In other embodiments, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor), and the source and drain doped layers serve as the source and drain of the PMOS. When the semiconductor structure is in operation, the source and drain doped layers apply compression stress to the channel, which can improve the hole mobility.

[0053] It should be noted that an anti-etching layer 104 is formed on the surface of the source / drain doped layer 102.

[0054] During the subsequent etching of the interlayer dielectric layer 106 to form source / drain openings that expose the source / drain doped layer 102, the etch-resistant layer 104 serves to temporarily stop the etching process.

[0055] The etching resistance of the etching-resistant layer 104 is greater than that of the interlayer dielectric layer 106.

[0056] In this embodiment, the material of the anti-etching layer 104 includes silicon nitride. Silicon nitride is a commonly used material in semiconductor processes, and it has high hardness and density, which enables it to effectively stop etching.

[0057] In the step of providing a substrate, the substrate further includes: a channel structure 201, which is disposed on the substrate 100; a gate structure 101 that spans the channel structure 201 and covers part of the top wall and part of the sidewall of the channel structure 201; and a source / drain doped layer 102 located in the channel structure 201 on both sides of the gate structure 101.

[0058] In this embodiment, the semiconductor structure is a FinFET (Fin Field-Effect Transistor). Correspondingly, the channel structure 201 is a fin. In other embodiments, the semiconductor structure may also be a Global Alloy Transistor (GAA), and the corresponding channel structure includes a channel stack.

[0059] In this embodiment, the channel structure 201 is made of silicon. In other embodiments, the channel structure may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0060] It should be noted that the pseudo-device region II is located between the channel structures 201, and the pseudo-device region II is used to electrically isolate the subsequently formed metal gate structure.

[0061] In this embodiment, during the step of providing the substrate, a sidewall layer 103 is formed between the gate structure 101 and the interlayer dielectric layer 106.

[0062] During the subsequent removal of the gate structure 101, the sidewall layer 103 protects the source and drain doped layer 102 from damage.

[0063] The material of the sidewall layer 103 includes one or more of SiCO, SiCN, SiN, and SiON. In this embodiment, the material of the sidewall layer 103 includes SiN.

[0064] The substrate further includes an isolation layer (not shown) located on the substrate 100 between the channel structures 201, the isolation layer covering a portion of the sidewalls of the channel structures 201.

[0065] The isolation layer is used to achieve electrical isolation between the various channel structures 201, and also to electrically isolate the substrate 100 and the subsequently formed metal gate structure.

[0066] In this embodiment, the material of the isolation layer is a dielectric material. Specifically, the material of the isolation layer includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer.

[0067] Interlayer dielectric layer 106 is used for electrical isolation of adjacent devices.

[0068] In this embodiment, the material of the interlayer dielectric layer 106 is an insulating material. Specifically, the material of the interlayer dielectric layer 106 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 106.

[0069] refer to Figure 8 and Figure 9 The gate structure 101 and interlayer dielectric layer 106 of a certain thickness in the pseudo-device region II are removed to form a first opening 105.

[0070] In the formation method provided in this embodiment of the invention, a portion of the thickness of the gate structure 101 and the interlayer dielectric layer 106 in the dummy device region II is removed to form a first opening 105 (e.g., Figure 9 As shown, the gate structure 101 exposed by the first opening 105 is subsequently removed to form a second opening. A first blocking layer is formed in the second opening. The first blocking layer is not easily formed on the interlayer dielectric layer 106. Correspondingly, during the process of etching the interlayer dielectric layer 106 to form the source / drain opening that exposes the source / drain doped layer 102, the first blocking layer will not be etched. That is to say, during the process of forming the source / drain opening, the first blocking layer is not likely to play a temporary etching stop role, so that the formation quality of the source / drain opening is better. The source / drain opening can expose the source / drain doped layer 102, so that the contact resistance between the subsequently formed source / drain plug and the source / drain doped layer 102 is smaller, which is beneficial to improving the electrical performance of the semiconductor structure.

[0071] In addition, a portion of the thickness of the gate structure 101 and the interlayer dielectric layer 106 is removed to form a first opening 105, in preparation for the subsequent complete removal of the gate structure 101 of the pseudo-device region II.

[0072] In this embodiment, a dry etching process is used to remove a portion of the gate structure 101 and interlayer dielectric layer 106 in the dummy device region II, forming a first opening 105. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps ensure that the morphology of the first opening 105 meets process requirements and also improves the removal efficiency of the interlayer dielectric layer 106 and gate structure 101. Using a dry etching process allows for precise control of the removal thickness of the interlayer dielectric layer 106 and gate structure 101, reducing damage to other film structures.

[0073] The step of removing a portion of the thickness of the gate structure 101 and interlayer dielectric layer 106 in the dummy device region II to form the first opening 105 includes: forming a mask layer 108 with a groove 107 on the substrate, the groove 107 exposing the dummy device region II.

[0074] The mask layer 108 is made of a material that is easy to remove, which reduces damage to the formed film layer when the mask layer 108 is removed in the future.

[0075] In this embodiment, the material of the mask layer 108 is an organic material. Specifically, the material of the mask layer 108 includes one or more of the following: BARC (bottom anti-reflective coating), SOC (spin on carbon), ODL (organic dielectric layer), photoresist, DARC (dielectric anti-reflective coating), DUO, or APF (Advanced Patterning Film).

[0076] The step of forming the mask layer 108 includes: forming a mask material layer (not shown) covering the substrate; patterning the mask material layer, with the remaining mask material layer serving as the mask layer 108.

[0077] In this embodiment, the mask material layer is formed using a spin coating process. Spin coating offers advantages such as mild process conditions and simple operation, and significantly reduces pollution, saves energy, and improves cost-effectiveness.

[0078] It should be noted that in the step of forming the first opening 105, the distance from the top surface of the interlayer dielectric layer 106 to the top surface of the source / drain doped layer 102 should not be too small. Subsequently, the gate structure 101 exposed by the first opening 105 is removed to form the second opening, and a dielectric material layer is formed in both the first and second openings. The dielectric material layer in the first opening 105 is then removed, leaving the dielectric material layer in the second opening as the first blocking layer. If the distance is too small, meaning the depth of the first opening 105 is too large, the thickness of the dielectric material layer removed during the formation of the first blocking layer in the second opening will be too large, requiring excessive processing time, resulting in poor process control and low formation efficiency of the first blocking layer. Furthermore, if the distance is too small, the source / drain doped layer 102 is easily etched incorrectly during the formation of the first opening 105. In this embodiment, the distance from the top surface of the interlayer dielectric layer 106 to the top surface of the source / drain doped layer 102 is greater than [missing information].

[0079] In this embodiment, the method for forming the semiconductor structure includes: after providing the substrate, before forming the first opening 105, removing part of the thickness or completely removing the sidewall layer 103.

[0080] Specifically, after the mask layer 108 is formed but before the first opening 105 is formed, a portion or all of the thickness of the sidewall layer 103 is removed.

[0081] Removing part or all of the thickness of the sidewall layer 103 helps reduce the difficulty of the subsequent removal of the gate structure 101.

[0082] In this embodiment, a dry etching process is used to remove part or all of the sidewall layer 103. During the dry etching process to remove part or all of the sidewall layer 103, the etching rate of the sidewall layer 103 is greater than the etching rate of the gate structure 101, and the etching rate of the sidewall layer 103 is greater than the etching rate of the interlayer dielectric layer 106. This is beneficial for ensuring that the morphology of the first opening 105 meets the process requirements. In addition, the dry etching process allows for precise control of the removal thickness of the sidewall layer 103, or, during the complete removal of the sidewall layer 103, the top of the channel structure 201 can be used as the etching stop position, and damage to other film structures can be reduced.

[0083] Specifically, using the mask layer 108 as a mask, a dry etching process is used to remove part of the thickness of the sidewall layer 103 or to completely remove the sidewall layer 103.

[0084] Specifically, in the process of removing part of the thickness of the sidewall layer 103 using a dry etching process, the etching gas used includes one or both of CHF3 and CH2F2.

[0085] In other embodiments, the method for forming the semiconductor structure further includes: after forming the first opening and before forming the second opening, removing a portion of the thickness or completely removing the sidewall layer.

[0086] After forming the first opening, a portion of the thickness or the sidewall layer is removed, resulting in a larger removal window for the gate structure and reducing the difficulty of subsequent gate structure removal processes.

[0087] refer to Figure 10 Remove the gate structure 101 exposed by the first opening 105 to form a second opening 109.

[0088] The second opening 109 prepares for the subsequent formation of the first blocking layer.

[0089] In this embodiment, a dry etching process is used to remove the gate structure 101 exposed by the first opening 105, forming a second opening 109. During the process of removing the gate structure 101 exposed by the first opening 105 using the dry etching process, the etching rate of the gate structure 101 is greater than the etching rate of the interlayer dielectric layer 106. While forming the second opening 109, damage to the interlayer dielectric layer 106 of the dummy device region II is reduced, which helps to ensure that the morphology of the second opening 109 meets the process requirements.

[0090] Specifically, using the mask layer 108 as a mask, a dry etching process is employed to remove the gate structure 101 exposed by the first opening 105, forming a second opening 109.

[0091] The method for forming the semiconductor structure further includes: after forming the second opening 109, removing the mask layer 108.

[0092] After forming the second opening 109, removing the mask layer 108 can prevent organic materials in the mask layer 108 from contaminating the machine. Furthermore, it provides process space for the subsequent formation of the first barrier layer.

[0093] In this embodiment, the mask layer 108 is removed using an ashing process.

[0094] refer to Figure 11 and Figure 12 A first blocking layer 111 is formed in the second opening 109 (e.g., Figure 12 (As shown).

[0095] The first blocking layer 111 and the subsequently formed second blocking layer are used to disconnect the gate structure 101.

[0096] Specifically, the step of forming a first blocking layer 111 in the second openings 109 on both sides of the interlayer dielectric layer 106 includes:

[0097] like Figure 11 As shown, a dielectric material layer 110 is formed in the first opening 105 and the second opening 109.

[0098] Subsequently, the dielectric material layer 110 in the first opening 105 is removed, and the remaining dielectric material layer 110 in the second opening 109 serves as the first blocking layer.

[0099] In this embodiment, the step of forming the dielectric material layer 110 includes: conformally covering the silicon nitride material layer 1101 in the first opening 105 and the second opening 109; and forming a silicon oxide material layer 1102 on the silicon nitride material layer 1101.

[0100] In the method for forming the semiconductor structure, the gate structure 101 of the device region I is subsequently removed. During the removal of the gate structure 101 of the device region I, the gate oxide layer is removed. The material of the gate oxide layer includes silicon oxide. The etching resistance of the silicon nitride is greater than that of the silicon oxide. Therefore, during the removal of the gate oxide layer, the silicon nitride material layer 1101 is etched at a lower rate, and the first blocking layer 1101 and the subsequent second blocking layer can better block the subsequently formed metal gate structure.

[0101] In this embodiment, the silicon nitride material layer 1101 is formed using atomic layer deposition (ALD). ALD involves multiple deposition cycles, which improves the thickness uniformity of the silicon nitride material layer 1101, enabling it to conformally cover the sidewalls and bottom surface of the first opening 105 and the second opening 109. Furthermore, ALD offers good gap-filling performance and step coverage, correspondingly enhancing the conformal coverage capability of the silicon nitride material layer 1101. In other embodiments, the silicon nitride material layer can also be formed using chemical vapor deposition (CVD).

[0102] In this embodiment, the silicon oxide material layer 1102 is formed using a flowable chemical vapor deposition (FCVD) process. The FCVD process has excellent filling capabilities and is suitable for filling the first opening 105 and the second opening 109, which helps reduce the probability of voids and other defects forming within the silicon oxide material layer 1102, thereby improving the film quality of the silicon oxide material layer 1102.

[0103] In other embodiments, the step of forming the dielectric material layer includes forming a silicon nitride layer in the first opening and the second opening. That is, only silicon nitride exists in the first and second openings, resulting in a lower etching rate of the first blocking layer during the subsequent removal of the gate oxide layer.

[0104] like Figure 12 As shown, the dielectric material layer 110 in the first opening 105 is removed, and the remaining dielectric material layer 110 in the second opening 109 serves as the first blocking layer 111.

[0105] By removing the dielectric material layer 110 in the first opening 105, the first blocking layer 111 is formed only in the second opening 109. This makes it less likely that silicon nitride will be etched during the subsequent etching of the interlayer dielectric layer 106 to form the source and drain openings, and the etching will not stop.

[0106] In this embodiment, a dry etching process is used to remove the dielectric material layer 110 in the first opening 105. In the step of removing the dielectric material layer 110 in the first opening 105 using a dry etching process, the top of the interlayer dielectric layer 106 can be used as the etching stop position, making the semiconductor structure formation method more controllable.

[0107] It should be noted that during the process of removing the dielectric material layer 110 in the first opening 105, the silicon nitride material layer 1101 on the top of the interlayer dielectric layer 106 of the dummy device region II is exposed around its perimeter, and the removal process window for the silicon nitride material layer 1101 on the top of the interlayer dielectric layer 106 is relatively large, making it easy to remove. On the other hand, one side of the silicon nitride material layer 1101 on the sidewall of the first opening 105 is exposed, resulting in a smaller removal process window, making it easier to retain the silicon nitride material layer 1101 on the sidewall of the first opening 105.

[0108] Specifically, the remaining silicon oxide material layer 1102 serves as silicon oxide layer 1112, the remaining silicon nitride material layer 1101 serves as silicon nitride layer 1111, and the silicon oxide layer 1112 and silicon nitride layer 1111 serve as the first blocking layer 111.

[0109] Subsequently, a second blocking layer is formed in the first opening 105, and correspondingly, the sidewalls of the second blocking layer are surrounded by the silicon nitride material layer 1101. During the subsequent removal of the gate oxide layer, the silicon nitride material layer 1101 in the first blocking layer 111 is not easily removed, so that the first blocking layer 111 and the second blocking layer can be retained, and the first blocking layer 111 and the second blocking layer can better electrically isolate the subsequently formed metal gate structure.

[0110] refer to Figure 13 and Figure 14 , Figure 14 for Figure 13 A cross-sectional view at the BB layer shows a second blocking layer 112 formed in the first opening 105.

[0111] The second blocking layer 112 and the first blocking layer 111 are used together to block the subsequent formation of the metal gate structure 101.

[0112] In this embodiment, in the step of forming the second blocking layer 112 in the first opening 105, the material of the second blocking layer 112 is the same as the material of the interlayer dielectric layer 106. During the subsequent etching of the second blocking layer 112 and the interlayer dielectric layer 106, the formed source / drain opening can penetrate the second blocking layer 112 and the interlayer dielectric layer 106 to expose the source / drain doped layer 104.

[0113] In this embodiment, the material of the second blocking layer 112 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps reduce the process difficulty and cost of forming the second blocking layer 112. In addition, silicon oxide has a low dielectric constant, which also helps to improve the function of the subsequent second blocking layer 112 in isolating adjacent devices. The material of the second blocking layer 112, silicon oxide, can reduce the internal stress of the semiconductor structure, which is beneficial to improving the electrical performance of the semiconductor structure.

[0114] In this embodiment, the second blocking layer 112 is formed using a flowable chemical vapor deposition process. The flowable chemical vapor deposition process has good filling ability, which helps reduce the probability of voids and other defects forming within the second blocking layer 112, thereby improving the film quality of the second blocking layer 112.

[0115] refer to Figure 15 and Figure 16The method for forming the semiconductor structure further includes: etching the interlayer dielectric layer 106 to form source / drain openings 113 exposing the source / drain doped layer 102. The extension direction of the source / drain openings 113 is the same as the extension direction of the gate structure 101.

[0116] A portion of the gate structure 101 and interlayer dielectric layer 106 in the dummy device region II is removed to form a first opening 105. The gate structure 101 exposed by the first opening 105 is removed to form a second opening 109. A first blocking layer 111 is formed in the second opening 109. Correspondingly, the first blocking layer 111 is not easily formed on the interlayer dielectric layer 106. Correspondingly, during the etching of the interlayer dielectric layer 106 to form the source / drain opening 113 exposing the source / drain doped layer 102, the first blocking layer 111 is not etched. That is, during the formation of the source / drain opening 113, the first blocking layer 111 is not likely to temporarily stop the etching, resulting in better formation quality of the source / drain opening 113. The source / drain opening 113 can expose the source / drain doped layer 102, resulting in lower contact resistance between the subsequently formed source / drain plug and the source / drain doped layer 102, which is beneficial to improving the electrical performance of the semiconductor structure.

[0117] The source / drain opening 113 provides space for the subsequent formation of the source / drain plug.

[0118] Specifically, during the process of etching the interlayer dielectric layer 106 to form the source / drain opening 113 that exposes the source / drain doped layer 102, the second blocking layer 112 is also etched.

[0119] In this embodiment, a dry etching process is used to etch the second blocking layer 112 and the interlayer dielectric layer 106 to form source / drain openings 113 exposing the source / drain doped layer 102. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps ensure that the morphology of the source / drain openings 113 meets process requirements and also improves the removal efficiency of the second blocking layer 112 and the interlayer dielectric layer 106. Furthermore, during the dry etching process, the top of the etch-resistant layer 104 can be used as a temporary etching stop point, reducing damage to other film structures.

[0120] It should be noted that during the process of forming the source / drain opening 113 that exposes the source / drain doped layer 102, after temporarily stopping the etching on the resist layer 104, the dry etching process continues to etch the resist layer 104. The dry etching process can simultaneously etch the second blocking layer 112, the interlayer dielectric layer 106, and the resist layer 104 in the same machine by changing the gas.

[0121] It should be noted that, in other embodiments, the method for forming the semiconductor structure further includes: after forming the second blocking layer and before forming the source / drain opening, removing the dummy gate structure to form a gate opening; forming a work function layer and a metal gate layer on the bottom surface and sidewalls of the gate opening, wherein the work function layer and the metal gate layer serve as a metal gate structure.

[0122] Accordingly, during the formation of the source / drain opening, the gate structure is a metal gate structure, and the extension direction of the source / drain opening is the same as the extension direction of the gate structure, meaning that the extension direction of the source / drain opening is the same as the extension direction of the metal gate structure.

[0123] Accordingly, embodiments of the present invention also provide a semiconductor structure. (See reference...) Figure 17 and Figure 18 , Figure 18 for Figure 17 The cross-sectional view at DD shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0124] The semiconductor structure includes: a substrate 200, which includes a device region I and a dummy device region II; a gate structure 201, disposed on the substrate 200, the extension direction of the gate structure 201 being perpendicular to the extension direction of the dummy device region II; source / drain doped layers 202, located on both sides of the gate structure 201; an interlayer dielectric layer 206, located on the source / drain doped layers 202 and covering the sidewalls of the gate structure 201; a first blocking layer 211, located on the side of the interlayer dielectric layer 206 in the dummy device region II, for disconnecting the gate structure 201; and a source / drain opening 213, penetrating the interlayer dielectric layer 206 to expose the source / drain doped layers 202, the extension direction of the source / drain opening 213 being the same as the extension direction of the gate structure 201.

[0125] In the semiconductor structure provided by this embodiment of the invention, the first blocking layer 211 is located on the side of the interlayer dielectric layer 206 of the pseudo-device region II. Correspondingly, during the process of etching the interlayer dielectric layer 206 to form the source / drain opening 213 exposing the source / drain doped layer 202, the first blocking layer 211 is not etched. That is to say, during the process of forming the source / drain opening 213, the first blocking layer 211 does not easily play the role of temporarily stopping the etching, so that the source / drain opening 213 can expose the source / drain doped layer 202. This results in a smaller contact resistance between the subsequently formed source / drain plug and the source / drain doped layer 202, which is beneficial to improving the electrical performance of the semiconductor structure.

[0126] In the semiconductor structure, device region I is used to form a semiconductor device, and the pseudo-device region II is used for the electrically isolated gate structure 201.

[0127] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0128] In this embodiment, the gate structure 201 is a stacked structure. Specifically, the gate structure 201 includes a gate dielectric and a metal gate layer located on the gate dielectric layer.

[0129] In this embodiment, the material of the gate dielectric layer is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0130] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the gate structure may also be W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0131] When the semiconductor structure is in operation, the source and drain doped layers 202 provide stress to the channel, thereby increasing the carrier migration rate.

[0132] In this embodiment, the semiconductor structure is an NMOS, and the source and drain doped layers 202 serve as the source and drain of the NMOS. When the semiconductor structure is operating, the source and drain doped layers 202 apply tensile stress to the channel, which can increase the electron migration rate.

[0133] In other embodiments, the semiconductor structure is a PMOS, and the source and drain doped layers serve as the source and drain of the PMOS. When the semiconductor structure is operating, the source and drain doped layers apply compressive stress to the channel, which can improve the hole mobility.

[0134] It should be noted that an anti-etching layer 204 is formed on the surface of the source / drain doped layer 202.

[0135] During the etching of the interlayer dielectric layer 206 to form the source / drain openings 213 that expose the source / drain doped layer 202, the etching resist layer 204 serves to temporarily stop the etching process.

[0136] The etching resistance of the etching-resistant layer 204 is greater than that of the interlayer dielectric layer 206.

[0137] In this embodiment, the material of the anti-etching layer 204 includes silicon nitride. Silicon nitride is a commonly used material in semiconductor processes, and it has high hardness and density, which enables it to effectively stop etching.

[0138] The semiconductor structure further includes: a channel structure 401, which is disposed on the substrate 200; a gate structure 201 that spans the channel structure 401 and covers part of the top wall and part of the side wall of the channel structure 401; and a source / drain doped layer 202 located in the channel structure 401 on both sides of the gate structure 201.

[0139] In this embodiment, the semiconductor structure is a FinFET (Fin Field-Effect Transistor). Correspondingly, the channel structure 401 is a fin. In other embodiments, the semiconductor structure may also be a Global Alloy Transistor (GAA), and the corresponding channel structure includes a channel stack.

[0140] In this embodiment, the channel structure 401 is made of silicon. In other embodiments, the channel structure may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0141] It should be noted that the pseudo-device region II is located between the channel structures 401, and the pseudo-device region II is used to electrically isolate the gate structure 201.

[0142] It should be noted that the distance from the top surface of the interlayer dielectric layer 206 to the top surface of the source / drain doped layer 102 should not be too small. The steps for forming the first blocking layer 211 typically include: forming dielectric material layers on the top and sides of the interlayer dielectric layer 206 in the dummy device region II; removing the dielectric material layer above the interlayer dielectric layer 206; and using the remaining dielectric material layer as the first blocking layer 211. If the distance is too small, too much dielectric material layer needs to be removed, requiring excessive processing time, resulting in poor process control and low formation efficiency of the first blocking layer 211. In this embodiment, the distance from the top surface of the interlayer dielectric layer 206 to the top surface of the source / drain doped layer 102 is greater than...

[0143] The substrate further includes an isolation layer (not shown) located on the substrate 200 between the channel structures 401, the isolation layer covering a portion of the sidewalls of the channel structures 401.

[0144] The isolation layer is used to provide electrical isolation between the various channel structures 401, and also to electrically isolate the substrate 100 and the gate structure 201.

[0145] In this embodiment, the material of the isolation layer is a dielectric material. Specifically, the material of the isolation layer includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer.

[0146] Interlayer dielectric layer 206 is used for electrical isolation of adjacent devices.

[0147] In this embodiment, the material of the interlayer dielectric layer 206 is an insulating material. Specifically, the material of the interlayer dielectric layer 206 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 206.

[0148] The first blocking layer 211 and the second blocking layer 212 are used to disconnect the gate structure 101.

[0149] In this embodiment, the first blocking layer 211 includes a silicon nitride layer 2111 and a silicon oxide layer 2112 located on the silicon nitride layer 2111.

[0150] The semiconductor structure further includes a second blocking layer 212, located on the interlayer dielectric layer 206 and the first blocking layer 211 of the pseudo-device region II.

[0151] Furthermore, the silicon nitride layer 2111 is located between the second blocking layer 212 and the interlayer dielectric layer 206.

[0152] During the formation of the gate structure 201, the silicon nitride layer 2111 makes the first blocking layer 211 and the second blocking layer 212 less susceptible to etching.

[0153] In other embodiments, the first blocking layer may further include a silicon nitride layer. That is, the material of the first blocking layer is only silicon nitride.

[0154] Correspondingly, the source / drain opening 213 also penetrates the second blocking layer 212.

[0155] In this embodiment, the material of the second blocking layer 212 is the same as the material of the interlayer dielectric layer 206.

[0156] The material of the second blocking layer 212 is the same as that of the interlayer dielectric layer 206. During the process of etching the second blocking layer 212 and the interlayer dielectric layer 206 to form the source / drain opening 213, it is not easy for the etching to stop.

[0157] In this embodiment, the material of the second blocking layer 112 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the second blocking layer 112. In addition, the low dielectric constant of silicon oxide also helps to improve the function of the second blocking layer 112 in isolating adjacent devices.

[0158] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0159] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, the substrate comprising a substrate, a gate structure separated from the substrate, source-drain doped layers on both sides of the gate structure, and an interlayer dielectric layer covering the source-drain doped layers, the substrate comprising a device region and a dummy device region, the dummy device region extending perpendicularly to the extension of the gate structure; removing part of the thickness of the gate structure and the interlayer dielectric layer in the dummy device region to form a first opening; removing the gate structure exposed by the first opening to form a second opening; forming a first blocking layer in the second opening; forming a second blocking layer in the first opening; etching the interlayer dielectric layer to form a source-drain opening exposing the source-drain doped layer, the source-drain opening extending in the same direction as the gate structure; wherein, in the process of etching the interlayer dielectric layer to form the source-drain opening exposing the source-drain doped layer, the second blocking layer is also etched, the material of the second blocking layer being the same as that of the interlayer dielectric layer; the source-drain opening also penetrates the second blocking layer.

2. The method of forming a semiconductor structure of claim 1, wherein, The step of forming a first blocking layer in the second opening comprises: forming a dielectric material layer in the first opening and the second opening; removing the dielectric material layer in the first opening, and leaving the dielectric material layer in the second opening as the first blocking layer.

3. The method of forming a semiconductor structure of claim 2, wherein, The dielectric material layer in the first opening is removed by a dry etching process.

4. The method of forming a semiconductor structure of claim 2, wherein, The step of forming the dielectric material layer comprises: conformally covering a silicon nitride material layer in the first opening and the second opening; and forming a silicon oxide material layer on the silicon nitride material layer; Alternatively, The step of forming the dielectric material layer comprises: forming a silicon nitride layer in the first opening and the second opening.

5. The method of forming a semiconductor structure of claim 1, wherein, The material of the second blocking layer comprises silicon oxide.

6. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the first opening, the distance from the top surface of the interlayer dielectric layer to the top surface of the source-drain doped layer is greater than 300 Å.

7. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, a sidewall layer is formed between the gate structure and the interlayer dielectric layer; The method for forming the semiconductor structure comprises: after the substrate is provided, removing part of the thickness or completely removing the sidewall layer before the first opening is formed.

8. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, a sidewall layer is formed between the gate structure and the interlayer dielectric layer; The method for forming the semiconductor structure comprises: after the first opening is formed, removing part of the thickness or completely removing the sidewall layer before the second opening is formed.

9. The method of forming a semiconductor structure according to claim 7 or 8, wherein Part of the thickness or the entire sidewall layer is removed by a dry etching process.

10. The method of forming a semiconductor structure of claim 1, wherein, The gate structure exposed by the first opening is removed by a dry etching process to form the second opening.

11. The method of forming a semiconductor structure of claim 1, wherein, The step of removing part of the thickness of the gate structure and the interlayer dielectric layer in the dummy device region to form the first opening comprises: forming a mask layer with a groove on the substrate, the groove exposing the dummy device region; The method for forming the semiconductor structure further comprises: after the second opening is formed, removing the mask layer.

12. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the substrate comprises a channel structure separated from the substrate, the gate structure crossing the channel structure, and covering part of the top wall and part of the side wall of the channel structure; The source-drain doped layer is located in the channel structure on both sides of the gate structure. The dummy device region is located between the channel structures.

13. A semiconductor structure, characterized by The semiconductor structure comprises: a substrate comprising a device region and a dummy device region; a gate structure separated on the substrate, the extension direction of the gate structure being perpendicular to the extension direction of the dummy device region; a source-drain doped layer located on both sides of the gate structure; an interlayer dielectric layer located on the source-drain doped layer and covering the sidewall of the gate structure; a first blocking layer located on the side of the interlayer dielectric layer of the dummy device region for blocking the gate structure; a second blocking layer located on the interlayer dielectric layer and the first blocking layer of the dummy device region; the material of the second blocking layer is the same as that of the interlayer dielectric layer; a source-drain opening exposing the source-drain doped layer through the interlayer dielectric layer, the extension direction of the source-drain opening being the same as that of the gate structure; the source-drain opening also penetrates the second blocking layer.

14. The semiconductor structure of claim 13, wherein, The material of the second blocking layer comprises silicon oxide.

15. The semiconductor structure of claim 13, wherein, The semiconductor structure further comprises: a channel structure separated on the substrate, the gate structure crossing the channel structure and covering part of the top wall and part of the sidewall of the channel structure; The source-drain doped layer is located in the channel structure on both sides of the gate structure. The dummy device region is located between the channel structures.

16. The semiconductor structure of claim 13, wherein, The distance from the top surface of the interlayer dielectric layer to the top surface of the source-drain doped layer is greater than 300 Å.

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