Resistive random access memory device

Abstract

The present disclosure relates generally to memory devices and methods of forming the same. More specifically, the present disclosure relates to resistive random access (ReRAM) memory devices. The present disclosure provides a memory device comprising a dielectric layer having an opening, a sidewall along the opening, a first electrode located in the opening, a resistive layer disposed on the first electrode, an oxygen scavenging layer disposed on the resistive layer, and a second electrode in contact with the oxygen scavenging layer. The oxygen scavenging layer comprises a material that is different from the resistive layer and partially covers the resistive layer. The first electrode is electrically connected to the second electrode through the oxygen scavenging layer and the resistive layer.

Description

Technical Field

[0001] The disclosed subject matter generally relates to memory devices and methods of forming the same. More specifically, this disclosure relates to resistive random access (ReRAM) memory devices. Background Technology

[0002] Semiconductor devices and integrated circuit (IC) chips have found widespread application in the fields of physics, chemistry, biology, computing, and memory devices. An example of a memory device is a non-volatile (NV) memory device. NV memory devices are programmable and widely used in electronic products due to their ability to retain data for extended periods, even after power is turned off. Exemplary categories of NV memory can include resistive random access memory (ReRAM), erasable programmable read-only memory (EPROM), flash memory, ferroelectric random access memory (FeRAM), and magnetoresistive random access memory (MRAM).

[0003] Resistive memory devices operate by changing (or switching) between two different states: a high-resistance state (HRS), which can represent off or a 0 state; and a low-resistance state (LRS), which can represent on or a 1 state. However, these devices can experience large changes in their resistance switching characteristics, which can lead to large fluctuations in the current flow within the device, degrading its performance and increasing its power consumption.

[0004] Therefore, there is a need to provide improved memory devices that can overcome or at least improve one or more of the disadvantages mentioned above. Summary of the Invention

[0005] In one aspect of this disclosure, a memory device is provided, comprising: a dielectric layer having an opening; a first electrode located in the opening; a resistive layer disposed on the first electrode; a first oxygen scavenging layer disposed on the resistive layer; and a second electrode in contact with the first oxygen scavenging layer. The first oxygen scavenging layer comprises a material different from and partially covering the resistive layer.

[0006] In another aspect of this disclosure, a memory device is provided, comprising: a dielectric layer having an opening; a sidewall along the opening; a first electrode located in the opening; a resistive layer disposed on the first electrode and disposed along the sidewall; a first oxygen scavenging layer disposed on the resistive layer; and a second electrode in contact with the first oxygen scavenging layer and the resistive layer. The first oxygen scavenging layer comprises a material different from and partially covering the resistive layer.

[0007] In another aspect of this disclosure, a method is provided for forming a memory device by: forming an opening in a dielectric layer; forming a first electrode in the opening; forming a resistive layer on the first electrode; forming an oxygen scavenging layer on the resistive layer, wherein the oxygen scavenging layer comprises a material different from and partially covering the resistive layer; and forming a second electrode on the oxygen scavenging layer. Attached Figure Description

[0008] This disclosure can be understood by referring to the following description and the accompanying drawings.

[0009] For the sake of simplicity and clarity, the accompanying drawings illustrate a general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the embodiments described in this disclosure. Furthermore, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the embodiments of this disclosure. The same reference numerals in different drawings denote the same elements, and similar reference numerals may, but do not necessarily, denote similar elements.

[0010] Figure 1A This is a cross-sectional view of an embodiment of a memory device according to the present disclosure.

[0011] Figure 1B and Figure 1C Based on this disclosure Figure 1A The top view of the memory device shown.

[0012] Figures 2 to 6 This is a cross-sectional view of another embodiment of the memory device according to the present disclosure.

[0013] Figures 7 to 12 This is a cross-sectional view illustrating a set of exemplary steps for manufacturing a memory device according to embodiments of the present disclosure.

[0014] Figures 13 to 18 This is a cross-sectional view illustrating another set of exemplary steps for manufacturing a memory device according to embodiments of the present disclosure.

[0015] Figures 19 to 22 This is a cross-sectional view illustrating a set of alternative steps for forming an oxygen scavenging layer with different widths and materials, according to embodiments of the present disclosure.

[0016] Figures 23 to 27 This is a cross-sectional view illustrating an alternative set of steps for forming an oxygen scavenging layer with different widths and materials, according to embodiments of the present disclosure. Detailed Implementation

[0017] Various exemplary embodiments of this disclosure are described below. The embodiments disclosed herein are exemplary and are not intended to be exhaustive or limiting of this disclosure.

[0018] Figure 1A A cross-sectional view of an exemplary memory device according to the present disclosure is shown. The device includes a dielectric layer 122 having an opening 112 and a sidewall 130 along the opening 112. A first electrode 102 is disposed in the opening 112, and a resistive layer 108 is disposed on the first electrode 102. At least one oxygen scavenging layer may be disposed on the resistive layer 108. For example, in Figure 1A The device may include a first oxygen scavenging layer 110a and a second oxygen scavenging layer 110b, both disposed on the resistive layer 108. As used herein, the terms "oxygen scavenging" or "scavenger" may refer to a component, layer, film, or material that consumes or depletes oxygen ions from a given environment or reacts with such oxygen ions. In some embodiments, the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b may have substantially the same width and may comprise the same material. In other embodiments, the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b may have different widths. The first oxygen scavenging layer 110a may also comprise a different material than the second oxygen scavenging layer 110b.

[0019] The second electrode 106a can be disposed on the first oxygen removal layer 110a, and the third electrode 106b can be disposed on the second oxygen removal layer 110b. The second electrode 106a contacts the first oxygen removal layer 110a and is electrically connected to the first electrode 102 through the first oxygen removal layer 110a and the resistive layer 108. The third electrode 106b contacts the second oxygen removal layer 110b and is electrically connected to the first electrode 102 through the second oxygen removal layer 110b and the resistive layer 108.

[0020] The resistive layer 108 is partially covered by a first oxygen scavenging layer 110a and a second oxygen scavenging layer 110b. The first oxygen scavenging layer 110a may be spaced apart from the second oxygen scavenging layer 110b. In one embodiment, both the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b may have a width smaller than that of the resistive layer 108. Furthermore, the combined width of the oxygen scavenging layers 110a and 110b may be smaller than the width of the resistive layer 108.

[0021] A dielectric cap 128 may be disposed on the resistive layer and spaced apart from the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b. The dielectric cap 128 may have an upper surface that is substantially coplanar with the upper surfaces of the dielectric layer, the first oxygen scavenging layer 110a, and the second oxygen scavenging layer 110b. The dielectric cap 128 may comprise the same material as the dielectric layer 122.

[0022] The first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b may each have an upper surface that is substantially coplanar with the upper surface of the dielectric layer 122. In some embodiments, the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b may have a side surface 132 adjacent to the sidewall 130 of the opening 112. The side surface 132 of the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b may also be substantially aligned with the side edge 134 of the resistive layer 108.

[0023] The first electrode 102, the second electrode 106a, and the third electrode 106b can be connected to various interconnect structures 114a, 114b, 116, 118a, 18b, 120 to send or receive electrical signals between other circuitry and / or active components in the memory device. The interconnect structures may include interconnect vias 118a, 118b, 120 and conductors 114a, 114b, 116, and may include metals such as copper, cobalt, aluminum, or alloys thereof. Depending on the design requirements of the memory device, conductors 114a, 114b, 116 may be configured as source lines, bit lines, or word lines. As used herein, the terms "source line," "word line," and "bit line" refer to electrical terminal connections that connect elements in the memory device circuitry.

[0024] For example, in Figure 1A In the illustrated embodiment, a first bit line (e.g., wire 114a) may be positioned above the second electrode 106a and connected to the second electrode 106a via an interconnect via 118a. A second bit line (e.g., wire 114b) may be positioned above the third electrode 106b and connected to the third electrode 106b via an interconnect via 118b. A source bit line (e.g., wire 116) may be positioned below the first electrode 102 and connected to the first electrode 102 via an interconnect via 120.

[0025] Examples of active components (not shown) that can be connected to the first electrode 102, the second electrode 106a, and the third electrode 106b may include diodes (e.g., bidirectional diodes, single-photon avalanche diodes, etc.) or transistors, such as, but not limited to, planar field-effect transistors, fin field-effect transistors (FinFETs), ferroelectric field-effect transistors (FeFETs), complementary metal-oxide-semiconductor (CMOS) transistors, and bipolar junction transistors (BJTs).

[0026] Conductive paths can be configured to be formed in resistive layer 108, first oxygen scavenging layer 110a, and second oxygen scavenging layer 110b in response to electrical signals (e.g., setting voltage or current). Specifically, depending on the operation of the device, the conductive paths can electrically connect first electrode 102 to second electrode 106a and first electrode 102 to third electrode 106b.

[0027] exist Figure 1A In the illustrated embodiment, the first electrode 102 can be configured as an inert electrode, while the second electrode 106a and the third electrode 106b can be configured as active electrodes. As used herein, the term "active electrode" can refer to an electrode having a conductive material capable of being oxidized and / or reduced (i.e., a redox reaction) to generate a charge for forming a conductive path. Examples of conductive materials in an active electrode may include, but are not limited to, tantalum (Ta), hafnium (Hf), titanium (Ti), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), or alloys thereof. Conversely, the term "inert electrode" can refer to a conductive material resistant to redox reactions. Examples of conductive materials for inert electrodes may include, but are not limited to, ruthenium (Ru), platinum (Pt), titanium nitride (TiN), and tantalum nitride (TaN). Preferably, the active electrode can be configured to have a thickness much greater than that of an inert electrode. The greater thickness of the active electrode provides sufficient material for redox reactions between the active electrode and the resistive layer.

[0028] For example, a set voltage can be applied to the wire 114a to provide a potential difference between the first electrode 102 and the second electrode 106a. This potential difference can cause conductive paths (not shown) to form in the first oxygen scavenging layer 110a and the resistive layer 108 to allow electrical conduction between the first electrode 102 and the second electrode 106a. Specifically, the conductive path can be a filament formed by the diffusion or drift of charges (e.g., ions, electrons) caused by the potential difference.

[0029] The resistive layer 108 can also be configured to have a switchable resistor that responds to changes in an electrical signal. When an electrical signal is applied, forming a filament in the resistive layer 108 can decrease the resistance of the resistive layer 108. When the electrical signal flows in the reverse direction, the filament can be removed and the resistance of the resistive layer 108 can increase, thereby enabling the controllable resistance property of the resistive layer 108. The resistive layer 108 can exhibit varying characteristics characterized by different resistance states of the material forming the layer. These resistance states (e.g., a high resistance state (HRS) or a low resistance state (LRS)) can be used to represent one or more bits of information.

[0030] The first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b can be configured to cause ions to move from the resistive layer 108 toward the active electrode in response to an electrical signal. For example, when a potential difference is applied across the active electrode (e.g., the second electrode 106a) and the inert electrode (e.g., the first electrode 102), the first oxygen scavenging layer 110a can scavenge oxygen ions from the resistive layer 108 to increase the concentration or density of oxygen vacancies in the resistive layer 108. The oxygen ions scavenged by the first oxygen scavenging layer 110a can then drift to the active electrode to complete the conductive path between the first electrode 102 and the second electrode 106a.

[0031] During an operation switch for changing the stored data, when a switching electrical signal (e.g., a set voltage or a reset voltage) is applied to the resistive layer 108 and the oxygen removal layers 110a, 110b, the resistive layer 108 can change its resistance state. Including the oxygen removal layers 110a, 110b between the resistive layer 108 and the second and third electrodes 106a, 106b reduces resistance so that a conductive path connects the first electrode 102 to the second electrode 106a and the third electrode 106b.

[0032] Advantageously, by partially covering the resistive layer 108 with oxygen scavenging layers 110a and 110b, the contact area between the resistive layer 108 and the oxygen scavenging layers 110a and 110b can be reduced. For example, the widths of the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b can be smaller than the width of the resistive layer 108, thereby reducing the contact area. By using the reduced contact area and the smaller width of the oxygen scavenging layers 110a and 110b, the conductive paths formed between the active and inert electrodes can be limited, and the conductive paths will not be randomly formed along the length of the resistive layer 108. Limiting the conductive paths helps reduce the randomness of their formation, thereby reducing the cycle time and inter-device variability of the memory device in a high-resistance state. In other words, the variability of the resistance of the resistive layer 108 in a high-resistance state can be reduced. This enables stable switching of the resistance state in the resistive layer 108 during device operation and can reduce its total power consumption.

[0033] More advantageously, by configuring the side surfaces 132 of the oxygen scavenging layers 110a, 110b to abut the sidewalls 130 of the openings 112 in the dielectric layer 122, the side surfaces 132 of the oxygen scavenging layers 110a, 110b can be aligned with the side edges 134 of the resistive layer 108.

[0034] Advantageously, the dielectric cap 128 can prevent the formation of any conductive paths (or filaments) in the portions of the resistive layer 108 not covered by the oxygen removal layers 110a, 110b. Thus, the filaments can be confined within the oxygen removal layers 110a, 110b, thereby reducing the variability of the resistance of the resistive layer 108.

[0035] The thickness of the resistive layer 108 can be configured such that a relatively low voltage level is sufficient to switch the resistance of the resistive layer 108. In some embodiments, the resistive layer 108 may have a thickness in the range of about 1 nm to about 10 nm. Examples of materials used for the resistive layer 108 may include, but are not limited to, carbon polymers, perovskites, silicon dioxide, metal oxides, or nitrides. Some examples of metal oxides may include lanthanide oxides, tungsten oxide, zinc oxide, nickel oxide, niobium oxide, titanium oxide, hafnium oxide, aluminum oxide, tantalum oxide, zirconium oxide, yttrium oxide, scandium oxide, magnesium oxide, chromium oxide, and vanadium oxide. Examples of nitrides may include boron nitride and aluminum nitride. In some embodiments, metal oxides with a band gap greater than 3 eV may be used. Examples of such oxides may include titanium oxide, tungsten oxide, niobium oxide, nickel oxide, zinc oxide, lanthanide oxides, hafnium oxide, aluminum oxide, tantalum oxide, zirconium oxide, and yttrium oxide.

[0036] The oxygen scavenging layers 110a and 110b may comprise a material different from the resistive layer 108. In some embodiments, the oxygen scavenging layers 110a and 110b may comprise a metal, such as tantalum (Ta), titanium (Ti), tungsten (W), hafnium oxide (HfO2), or an oxide such as aluminum oxide (Al2O3).

[0037] exist Figure 1A In the illustrated embodiment, wires 116 and interconnect vias 120 may be formed in the first dielectric region 124. A dielectric layer 122 may be disposed on the first dielectric region 124. Examples of dielectric materials in the dielectric layer 122 may include, but are not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), nitrogen-doped silicon carbide (SiCN), and SiC. x H z (i.e., BLoK) TM ) or SiN w C x H z (i.e., NBLOK) TM ), where w, x, y, and z independently have values ​​greater than 0 and less than 0.75.

[0038] The second dielectric region 126 may be disposed on the dielectric layer 122. The second dielectric region 126 may include a second electrode 106a, a third electrode 106b, interconnect vias 118a and 118b, and conductors 114a and 114b. The first dielectric region 124 and the second dielectric region 126 may be part of a "metallization level" or an intermetallic dielectric (IMD) layer. Examples of dielectric materials in the first dielectric region 124 and the second dielectric region 126 may include, but are not limited to, silicon dioxide, tetraethyl orthosilicate (TEOS), or materials with SiC. x O y Hz The chemical composition of the material, where x, y, and z are stoichiometric ratios.

[0039] Figure 1B and Figure 1C Various examples of oxygen scavenging layers 110a, 110b configured on resistive layer 108 are shown. Section lines X-X' indicate sections taken from them. Figure 1A The cross-section of the view is shown. For simplicity, only the first electrode 102, the second electrode 106a, the third electrode 106b, the resistive layer 108, the oxygen scavenging layers 110a and 110b, and the third electrode 107 are shown. The first electrode 102 is represented by a rectangle with a dashed outline. The second electrode 106a and the third electrode 106b are represented by rectangles with solid outlines.

[0040] like Figure 1B As shown, the device may include an array of memory cells 100a, 100b, and 100c. Each memory cell 100a, 100b, and 100c may be configured to include a first oxygen scavenging layer 110a, a second oxygen scavenging layer 110b, and a first electrode 102. A resistive layer 108, a second electrode 106a, and a third electrode 106b may be configured to extend across each memory cell 100a, 100b, and 100c.

[0041] Figure 1C The embodiments in the example are similar to Figure 1B In the embodiments, except in Figure 1C In this embodiment, the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b can be configured to extend across each memory cell 100a, 100b, 100c. In this embodiment, the oxygen scavenging layers 110a and 110b may include the oxides described herein.

[0042] refer to Figure 2 The same reference numerals indicate Figure 1A The same features are shown, and another embodiment of the memory device is illustrated. Figure 2 The embodiments shown are similar to those shown in Figure 1, except that... Figure 2 In this configuration, there is no third electrode or its associated interconnection. For example... Figure 2 As shown, the second electrode 106 is disposed on the first oxygen scavenging layer 110a, while the second oxygen scavenging layer 110b does not contact the electrode. Therefore, the conductive path can be confined within the first oxygen scavenging layer 110a to connect the first electrode 102 to the second electrode 106. A bit line (e.g., wire 114) can be disposed above and connected to the second electrode 106. A source line (e.g., wire 116) can be disposed below and connected to the first electrode 102.

[0043] refer to Figure 3The same reference numerals indicate Figure 2 The same features are shown, and another embodiment of the memory device is illustrated. Figure 3 The illustrated embodiments are similar to Figure 2 The embodiments shown, except in Figure 3 In this configuration, the second electrode 106 extends laterally to contact the second oxygen scavenging layer 110b. Therefore, the conductive path can be confined within the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b to connect the first electrode 102 to the second electrode 106.

[0044] refer to Figure 4 The same reference numerals indicate Figure 1A The same features are shown, and another embodiment of the memory device is illustrated. For example... Figure 4 As shown, the resistive layer 108 can be modified to be disposed on the first electrode 102 and along the sidewall 130 of the opening 112 in the dielectric layer 122. For example, the resistive layer 108 can have a first segment 108a disposed on the first electrode 102 and a second segment 10ba disposed along the sidewall 130 of the opening 112.

[0045] Oxygen removal layers 110a and 110b may partially cover resistive layer 108. For example, oxygen removal layers 110a and 110b may be disposed on a first segment 108a of resistive layer 108. Side surfaces 132 of oxygen removal layers 110a and 110b may be adjacent to a second segment 108b of resistive layer 108. Dielectric cap 128 may be disposed on the first segment 108a of resistive layer 108 and electrically isolate the first oxygen removal layer 110a from the second oxygen removal layer 110b. The second segment 108b of resistive layer 108 may have an upper surface that is substantially coplanar with the upper surfaces of dielectric layer 122, dielectric cap 128, and oxygen removal layers 110a and 110b.

[0046] The second electrode 106a can be disposed on the second segment 108b of the first oxygen scavenging layer 110a and the resistive layer 108. The third electrode 106b can be disposed on the second segment 108b of the second oxygen scavenging layer 110b and the resistive layer 108. The second electrode 106a is electrically connected to the first electrode 102 by contacting the first oxygen scavenging layer 110a and the resistive layer 108. The third electrode 106b is electrically connected to the first electrode 102 by contacting the second oxygen scavenging layer 110b and the resistive layer 108.

[0047] exist Figure 4In the illustrated embodiment, the second electrode 106a and the third electrode 106b can be configured as active electrodes, while the first electrode 102 can be configured as an inert electrode. Due to the low resistance in the oxygen scavenging layers 110a and 110b, conductive paths can be formed in the first segment 108a of the resistive layer 108 and traverse through the oxygen scavenging layers 110a and 110b to connect the active electrode to the inert electrode. In other words, conductive paths cannot be formed in the region of the first segment 108a of the resistive layer 108 that is not covered by the oxygen scavenging layers 110a and 110b.

[0048] refer to Figure 5 The same reference numerals indicate Figure 4 The same features are shown, and another embodiment of the memory device is illustrated. Figure 5 The illustrated embodiments are similar to Figure 4 The embodiments shown, except in Figure 5 In this configuration, there is no third electrode or its associated interconnection. For example... Figure 5 As shown, the second electrode 106 is disposed on the second segment 108b of the first oxygen removal layer 110a and the resistive layer 108, while the second oxygen removal layer 110b does not contact the electrode.

[0049] refer to Figure 6 The same reference numerals indicate Figure 5 The same features are shown, and another embodiment of the memory device is illustrated. Figure 6 The illustrated embodiments are similar to Figure 5 The embodiments shown, except in Figure 6 In the middle, the second electrode 106 extends laterally to contact the second oxygen scavenging layer 110b.

[0050] The memory devices described herein may be resistive memory devices. Examples of resistive memory devices may include, but are not limited to, oxide random access memory (OxRAM). Figure 1A and Figure 4 The illustrated embodiment can be referred to as a "1 transistor 2 resistor (1T2R)" configuration, while Figure 2 , Figure 3 , Figure 5 and Figure 6 The embodiment shown can be referred to as a "1 transistor 1 resistor (1T1R)" configuration.

[0051] Figures 7 to 12 A set of steps is shown that can be used to create memory devices as provided in the embodiments of this disclosure.

[0052] As used herein, “deposition technique” refers to a process of applying material onto another material (or substrate). Exemplary techniques for deposition include, but are not limited to, spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source atomized chemical deposition (LSMCD), and atomic layer deposition (ALD).

[0053] Furthermore, "patterning techniques" include the deposition of materials or photoresists required to form the patterns, structures, or openings; patterning of materials or photoresists; exposure, development, etching, cleaning, and / or removal. Examples of patterning techniques include, but are not limited to, wet etching lithography, dry etching lithography, or direct patterning processes. These techniques may utilize mask sets and mask layers.

[0054] Figure 7 and Figure 8 A first electrode 102 and a resistive layer 108 are shown formed within an opening 112 defined in a dielectric layer 122. (Reference) Figure 7 This illustration shows a device structure used in manufacturing the memory device of this disclosure. The device structure may include a first dielectric region 124 having a conductor 116 and interconnect vias 120. A first electrode 102 may be formed on the first dielectric region 124 and contact the interconnect vias 120. A resistive layer 108 may be formed on the first electrode 102. In one embodiment, the first electrode 102 and the resistive layer 108 may be formed by depositing a material layer using the deposition techniques described herein, and subsequently patterning the deposited layer using the patterning techniques described herein. A mask element 104 may be used to form the first electrode 102 and the resistive layer 108 during the patterning step.

[0055] refer to Figure 8 A dielectric layer 122 can be formed on the first dielectric region 124 using the deposition techniques described herein. The deposited dielectric layer 122 can laterally surround the first electrode 102, the resistive layer 108, and the mask element 104, such that the first electrode 102, the resistive layer 108, and the mask element 104 are located within an opening 112 defined in the dielectric layer 122. A chemical mechanical planarization (CMP) process can be performed on the mask element 104 and the upper surface of the dielectric layer 122. Subsequently, an etching process or a stripping process can be used to remove the mask element 104 to expose the resistive layer 108.

[0056] In an alternative embodiment (not shown) for forming the first electrode 102 and the resistive layer 108 within the opening 112, a mask element 104 may be formed on a dielectric layer 122, and then the portion of the dielectric layer 122 not covered by the mask element 104 is etched (using the patterning techniques described herein) to define the opening 112 in the dielectric layer 122. Thereafter, material for forming the first electrode 102 and the resistive layer 108 may be deposited within the opening 112 and on the mask element 104. The mask element 104 and the material deposited thereon may then be removed using an etching or stripping process to obtain... Figure 8 The structure shown.

[0057] Figure 9 and Figure 10 This illustrates the formation of oxygen scavenging layers 110a and 110b on the resistive layer 108. For example... Figure 9 As shown, an oxygen-removing material layer 136 can be deposited on the dielectric layer 122 and within the opening 112 using the deposition techniques described herein. Preferably, a conformal deposition process such as an ALD process or a highly conformal CVD process can be used.

[0058] refer to Figure 10 The deposited layer 136 can be patterned using the patterning techniques described herein to form a first oxygen scavenging layer 110a and a second oxygen scavenging layer 110b. As shown, after the patterning step, the oxygen scavenging layers 110a and 110b partially cover the resistive layer 108. In this embodiment, the first oxygen scavenging layer 110a and the second oxygen scavenging layer 110b may have substantially the same width and comprise the same material.

[0059] refer to Figure 11 A dielectric cap 128 can be deposited on the portion of resistive layer 108 not covered by oxygen removal layers 110a and 110b. A CMP process can be performed to ensure that the upper surfaces of dielectric layer 122, oxygen removal layers 110a and 110b, and dielectric cap 128 are substantially coplanar with each other.

[0060] Figure 12 The formation of electrodes in contact with oxygen scavenging layers 110a and 110b is shown. For example... Figure 12 As shown, a second electrode 106a can be formed on the first oxygen scavenging layer 110a, and a third electrode 106b can be formed on the second oxygen scavenging layer 110b. For example, a second dielectric region 126 can be formed on the dielectric layer 122 by depositing a dielectric material using the deposition techniques described herein. The second dielectric region 126 can then be patterned using the patterning techniques described herein to define electrode openings (not shown).

[0061] The second electrode 106a and the third electrode 106b can be formed in the electrode openings by depositing conductive material using the deposition techniques described herein. Further processing steps can be performed, such as forming interconnect structures in the second dielectric region 126 to provide electrical connections to the second electrode 106a and the third electrode 106b. In other embodiments, the patterning of the second dielectric region 126 can be modified to form a single electrode opening above the oxygen scavenging layers 110a, 110b for subsequent metal deposition therein.

[0062] Figures 13 to 18 Another set of steps is shown that can be used to create the memory device provided in the embodiments of this disclosure.

[0063] Figure 13 and Figure 14 A first electrode 102 is shown formed within an opening 112 defined in a dielectric layer 122. (See diagram.) Figure 13 As shown, the first electrode 102 can be formed on the first dielectric region 124 and contact the interconnect via 120, for example, by depositing a conductive material layer using the deposition techniques described herein, and then patterning the deposited layer using the patterning techniques described herein. The first electrode 102 can be formed using a mask element 104 during the patterning step.

[0064] like Figure 14 As shown, a dielectric layer 122 can be formed on the first dielectric region 124 using the deposition techniques described herein. The deposited dielectric layer 122 can laterally surround the first electrode 102 and the mask element 104 such that the first electrode 102 and the mask element 104 are located within an opening 112 defined in the dielectric layer 122. A chemical mechanical planarization (CMP) process can be performed on the mask element 104 and the upper surface of the dielectric layer 122. Subsequently, an etching process or a stripping process can be used to remove the mask element 104 to expose the first electrode 102.

[0065] In an alternative embodiment (not shown) for forming the first electrode 102 in the opening 112, a mask element 104 may be formed on the dielectric layer 122, and then the portion of the dielectric layer 122 not covered by the mask element 104 may be etched (using the patterning techniques described herein) to define the opening 112 in the dielectric layer 122. Thereafter, conductive material for forming the first electrode 102 may be deposited in the opening 112 and on the mask element 104. The mask element 104 and the conductive material deposited thereon may then be removed using an etching or stripping process. The first electrode 102 formed by this alternative embodiment may have a trapezoidal shape (i.e., the upper surface is narrower than the lower surface), and... Figure 14 The rectangular shapes shown form a contrast.

[0066] refer to Figure 15A resistive layer 108 and an oxygen scavenging material layer 136 can be formed in the opening 112 using the deposition techniques described herein. For example, the resistive layer 108 can be deposited on the first electrode 102 and the dielectric layer 122. Preferably, the resistive layer 108 can be deposited using a conformal deposition process such as an ALD process or a highly conformal CVD process, such that the resistive layer 108 linees the sidewall 130 of the opening 112. Subsequently, the oxygen scavenging material layer 136 can be deposited conformally to the resistive layer 108.

[0067] refer to Figure 16 The oxygen scavenging material layer 136 can be patterned using the patterning techniques described herein. The oxygen scavenging material layer 136 can be patterned to form a first oxygen scavenging layer 110a and a second oxygen scavenging layer 110b. When patterning the oxygen scavenging material layer 136, an anisotropic etching technique (e.g., a "spacer etching" process) can be used.

[0068] refer to Figure 17 The resistive layer 108 can be patterned to have a first segment 108a disposed on the first electrode 102 and a second segment 108b disposed along the sidewall of the opening. As shown, after the resistive layer 108 is patterned, oxygen removal layers 110a, 110b partially cover the resistive layer 108. A dielectric cap 128 can be deposited on the portions of the resistive layer 108 not covered by the oxygen removal layers 110a, 110b. A chemical mechanical planarization (CMP) process can be performed to ensure that the upper surfaces of the dielectric layer 122, the oxygen removal layers 110a, 110b, the second segment 108b of the resistive layer 108, and the dielectric cap 128 are substantially coplanar with each other.

[0069] Figure 18 The formation of electrodes in contact with oxygen scavenging layers 110a and 110b is shown. For example... Figure 18 As shown, a second electrode 106a can be formed on the second segment 108b of the first oxygen scavenging layer 110a and the resistive layer 108. A third electrode 106b can be formed on the second oxygen scavenging layer 110b and the second segment 108b of the resistive layer 108. For example, a dielectric material can be deposited using the deposition techniques described herein to form a second dielectric region 126 on the dielectric layer 122. The second dielectric region 126 can then be patterned using the patterning techniques described herein to define an electrode opening (not shown).

[0070] The second electrode 106a and the third electrode 106b can be formed in the electrode openings by depositing conductive material using the deposition techniques described herein. Further processing steps can be performed, such as forming interconnect structures in the second dielectric region 126 to provide electrical connections to the second electrode 106a and the third electrode 106b. In other embodiments, the patterning of the second dielectric region 126 can be modified to form a single electrode opening above the oxygen scavenging layers 110a, 110b for subsequent metal deposition therein.

[0071] Figures 19 to 22 A set of alternative steps for forming oxygen scavenging layers 110a and 110b with different widths and materials is shown. Figure 19 middle( Figure 19 Continued Figure 8 In the illustrated embodiment, a barrier element 138 can be deposited to cover a portion of the structure, while a first oxygen-removing material layer 136a can be deposited on the uncovered portions of the structure. The barrier element 138 can be a photoresist layer or a hard mask layer. Figure 20 In this process, the first oxygen removal material layer 136a can be etched to form the first oxygen removal layer 110a, and the blocking element 138 can be removed.

[0072] Figure 20 The structure shown can be used to form embodiments with a single oxygen scavenging layer. For example, it can be used... Figure 20 A second electrode is formed on the first oxygen scavenging layer 110a shown, and then the interconnect structure described herein is formed.

[0073] refer to Figure 21 ( Figure 21 Continued Figure 20 In the illustrated embodiment, a blocking element 138 can be deposited to cover a portion of the resistive layer 108 and the first oxygen scavenging layer 110a, leaving the remaining portion of the resistive layer 108 uncovered. A second oxygen scavenging material layer 136b can be deposited on the portion of the resistive layer 108 not covered by the blocking element 138. Compared to the first oxygen scavenging material layer 136a, the second oxygen scavenging material layer 136b can be deposited with a smaller thickness. Furthermore, the second oxygen scavenging material layer 136b can comprise a different material than the first oxygen scavenging material layer 136a.

[0074] exist Figure 22 In this process, the second oxygen scavenging material layer 136b can be etched to form the second oxygen scavenging layer 110b, and the blocking element 138 can be removed. Figure 22 The structure shown has undergone Figures 11 to 12 Further processing as described in [the document].

[0075] Figures 23 to 27Another set of alternative steps for forming oxygen scavenging layers 110a and 110b with different widths and materials is shown. Figure 23 middle( Figure 23 Continued Figure 9 In the illustrated embodiment, a first oxygen scavenging material layer 136a can be deposited on the dielectric layer 122 and within the opening 112 using the deposition techniques described herein. Preferably, a conformal deposition process such as an ALD process or a highly conformal CVD process can be used. A barrier element 138 can be deposited to cover a portion of the first oxygen scavenging material layer 136a, while leaving the remaining portion of the first oxygen scavenging material layer 136a uncovered.

[0076] refer to Figure 24 A second oxygen scavenging material layer 136b can be deposited on the portion of the first oxygen scavenging material layer 136a not covered by the blocking element 138. The second oxygen scavenging material layer 136b can be deposited with a greater thickness than the first oxygen scavenging material layer 136a. Furthermore, the second oxygen scavenging material layer 136b can comprise a different material than the first oxygen scavenging material layer 136a.

[0077] refer to Figure 25 Anisotropic etching technology can be used to etch the first oxygen scavenging material layer 136a and the second oxygen scavenging material layer 136b to form the first oxygen scavenging layer 110a. The first oxygen scavenging layer 110a may have multiple sublayers and include materials from the first oxygen scavenging material layer 136a and the second oxygen scavenging material layer 136b. For example, the first oxygen scavenging layer 110a may include a first sublayer 140a and a second sublayer 140b disposed on the first sublayer 140a.

[0078] Although not shown, depending on the desired structure of the first oxygen scavenging layer 110a, an additional oxygen scavenging material layer can be deposited on the portion of the first oxygen scavenging material layer 136a not covered by the blocking element 138, such as... Figure 24 As shown.

[0079] refer to Figure 26 ( Figure 26 Continued Figure 25 In the illustrated embodiment, the blocking element 138 can be removed, and the first oxygen scavenging material layer 136a previously covered by the blocking element 138 can be etched to form a second oxygen scavenging layer 110b. Compared to the first oxygen scavenging layer 110a, the second oxygen scavenging layer 110b can have a smaller width.

[0080] It can Figure 26 The structure shown has undergone Figures 11 to 12 Further processing as described herein. For example, such as... Figure 27 As shown ( Figure 27 Continued Figure 26In the illustrated embodiment, a dielectric cap 128 can be deposited on the portion of resistive layer 108 not covered by oxygen scavenging layers 110a, 110b. A CMP process can be performed to ensure that the upper surfaces of dielectric layer 122, oxygen scavenging layers 110a, 110b, and dielectric cap 128 are substantially coplanar with each other. A second electrode 106a can be formed on the first oxygen scavenging layer 110a, and a third electrode 106b can be formed on the second oxygen scavenging layer 110b. The second electrode 106a and the third electrode 106b can be formed in the second dielectric region 126. Interconnect structures can be formed over the second electrode 106a and the third electrode 106b to provide electrical connections to the second electrode 106a and the third electrode 106b.

[0081] Throughout this disclosure, it should be understood that if a method is described herein as involving a series of steps, the order of these steps presented herein is not necessarily the only order in which they can be performed, and some said steps may be omitted and / or certain other steps not described herein may be added to the method. Furthermore, the terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article of manufacture, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to those processes, methods, articles of manufacture, or devices. The appearance of the phrase “in one embodiment” does not necessarily indicate the same embodiment.

[0082] The description of various embodiments in this disclosure is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. Furthermore, there is no intention to be bound by any theory set forth in the foregoing background or the following detailed description.

[0083] Furthermore, the various tasks and processes described herein can be incorporated into a more comprehensive procedure or process with additional functions not described in detail herein. Specifically, the various processes in the manufacture of integrated circuits are well known; therefore, for the sake of brevity, many processes are only briefly mentioned or omitted entirely without providing well-known process details.

[0084] Those skilled in the art will readily understand, upon fully reading this application, that the disclosed semiconductor devices and their formation methods can be used to manufacture a variety of different integrated circuit products, including but not limited to memory chips, NV memory devices, FinFET transistor devices, CMOS devices, etc.

Claims

1. A memory device, comprising: A dielectric layer with openings; The first electrode is located in the opening; A resistive layer disposed on the first electrode; A first oxygen scavenging layer is disposed on the resistive layer, wherein the first oxygen scavenging layer comprises a material different from the resistive layer, and wherein the first oxygen scavenging layer only partially covers the top surface of the resistive layer; as well as The second electrode that is in contact with the first oxygen scavenging layer.

2. The device according to claim 1, wherein, The first electrode is electrically connected to the second electrode through the first oxygen scavenging layer and the resistive layer.

3. The device according to claim 2, further comprising: A second oxygen scavenging layer is disposed on the resistive layer, wherein the second oxygen scavenging layer is spaced apart from the first oxygen scavenging layer, and the second oxygen scavenging layer comprises a material different from the resistive layer, and wherein the second oxygen scavenging layer only partially covers the top surface of the resistive layer.

4. The device according to claim 3, wherein, The first oxygen removal layer and the second oxygen removal layer each have an upper surface that is coplanar with the upper surface of the dielectric layer.

5. The device according to claim 4, wherein, The second electrode extends laterally to contact the second oxygen removal layer.

6. The device according to claim 5, further comprising: A bit line disposed above the second electrode and connected to the second electrode; as well as The source line is positioned below the first electrode and connected to the first electrode.

7. The device according to claim 4, further comprising: A third electrode is disposed on the second oxygen scavenging layer, wherein the first electrode is electrically connected to the third electrode through the second oxygen scavenging layer and the resistive layer.

8. The device according to claim 7, further comprising: The first line is positioned above the second electrode and connected to the second electrode; A second bit line disposed above and connected to the third electrode; as well as The source line is positioned below the first electrode and connected to the first electrode.

9. The device according to claim 3, further comprising: Along the sidewall of the opening, wherein the first oxygen scavenging layer and the second oxygen scavenging layer have sidewalls adjacent to the sidewall.

10. The device according to claim 9, wherein, The sides of the first oxygen scavenging layer and the second oxygen scavenging layer are aligned with the side edges of the resistive layer.

11. The device according to claim 9, wherein, The first oxygen scavenging layer and the second oxygen scavenging layer have a width smaller than that of the resistive layer.

12. The device according to claim 3, wherein, The second oxygen removal layer is spaced apart from the first oxygen removal layer by a dielectric cap disposed on the resistive layer, wherein the dielectric cap covers the portion of the top surface of the resistive layer that is not covered by the first oxygen removal layer and the second oxygen removal layer.

13. The device according to claim 3, wherein, The first oxygen removal layer and the second oxygen removal layer comprise tantalum, titanium, tungsten, hafnium oxide, or aluminum oxide.

14. A memory device, comprising: A dielectric layer with openings; Along the sidewall of the opening; The first electrode is located in the opening; A resistive layer disposed on the first electrode and along the sidewall; A first oxygen scavenging layer is disposed on the resistive layer, wherein the first oxygen scavenging layer comprises a material different from the resistive layer, and wherein the first oxygen scavenging layer only partially covers the top surface of the resistive layer; as well as A second electrode in contact with the first oxygen scavenging layer and the resistive layer.

15. The device according to claim 14, further comprising: A dielectric cap disposed on the resistive layer; A second oxygen scavenging layer is disposed on the resistive layer, wherein the second oxygen scavenging layer is spaced apart from the first oxygen scavenging layer by the dielectric cap, and wherein the second oxygen scavenging layer comprises a material different from the resistive layer, and wherein the second oxygen scavenging layer only partially covers the top surface of the resistive layer. The dielectric cap covers the portion of the top surface of the resistive layer that is not covered by the first oxygen scavenging layer and the second oxygen scavenging layer.

16. The device according to claim 15, wherein, The resistive layer has a first segment disposed on the first electrode and a second segment disposed along the sidewall.

17. The device according to claim 16, wherein, The second segment of the resistive layer has an upper surface that is coplanar with the upper surface of the dielectric layer.

18. The device according to claim 17, wherein, The second electrode extends laterally to contact the second oxygen scavenging layer and the resistive layer.

19. The device according to claim 17, further comprising: A third electrode is disposed on the second oxygen scavenging layer, wherein the third electrode also contacts the resistive layer.

20. A method of forming a memory device, comprising: An opening is formed in the dielectric layer; A first electrode is formed in the opening; A resistive layer is formed on the first electrode; An oxygen removal layer is formed on the resistive layer, wherein the oxygen removal layer comprises a material different from the resistive layer, and wherein the oxygen removal layer only partially covers the top surface of the resistive layer; as well as A second electrode is formed on the oxygen scavenging layer.

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