Resistive random access memory, manufacturing method thereof and operating method thereof

Abstract

The present invention relates to a resistance random access memory (RRAM), a method for manufacturing the same, and an operating method thereof. The RRAM comprises a first electrode, a second electrode, and a charge trapping layer. The second electrode is located on the first electrode. The charge trapping layer is located between the first and second electrodes. The charge trapping layer includes a first region and a second region. The first region has a first dopant and is adjacent to the first electrode. The second region has a second dopant and is adjacent to the second electrode. The RRAM of the present invention has a nonlinear resistance value and does not require additional selection elements. Therefore, the area can be reduced, thereby achieving a high-density three-dimensional stacked RRAM array.

Description

[0001] This application is a divisional application of Chinese patent application No. 201610863789.2 (filing date: September 29, 2016, invention title: Resistive Random Access Memory, Manufacturing Method Thereof, and Operating Method Thereof). Technical Field

[0002] The present invention relates to a memory, a manufacturing method thereof and an operating method thereof, and in particular to a resistance random access memory, a manufacturing method thereof and an operating method thereof. Background Art

[0003] A memristor is a two-terminal device that uses electric field-induced resistive switching to change its resistance state. Because this resistance change is non-volatile, memristors have applications in artificial neuromorphic synapses, fuzzy logic devices, and resistive random access memory (RRAM).

[0004] RRAM is widely used in the field of non-volatile memory. Due to its simple staggered array and low-temperature manufacturing, RRAM has the best potential to replace the existing flash memory. Although the staggered array of RRAM theoretically allows 4F 2 The minimum cell size (where F is the minimum feature size) and low-temperature processes allow the stacking of memory arrays to achieve unprecedented integration density. However, in a 1R structure (that is, with only one resistor element), there will be a sneak current through the adjacent unselected memory cell, which seriously affects the read margin and limits the maximum size of the staggered array. This problem can be solved by adding additional nonlinear selection devices in series with these resistance conversion elements. Therefore, architectures such as a diode and a resistor (1D1R) and a selector and a resistor (1S1R) seem to have become the main contenders for three-dimensional (3D) stacked memory applications.

[0005] However, applying the aforementioned 1D1R and 1S1R architectures to 3D staggered arrays is prone to process issues, preventing their practical application in 3D memory manufacturing. Therefore, implementing a nonlinear resistance-switching element without requiring additional selector elements has become a key challenge in developing 3D memory with RRAM. Summary of the Invention

[0006] The present invention provides a resistance random access memory, a manufacturing method thereof, and an operating method thereof. The resistance random access memory has a nonlinear resistance value and does not require additional selection elements, thereby reducing the area and achieving a high-density three-dimensional stacked RRAM array.

[0007] The present invention provides a resistance random access memory, a manufacturing method thereof and an operating method thereof, which does not have the existing forming, filament and ion movement, thereby achieving the effect of low power consumption.

[0008] The present invention provides a resistance random access memory (RRAM) comprising a first electrode, a second electrode, and a charge trapping layer. The second electrode is located on the first electrode. The charge trapping layer is located between the first and second electrodes. The charge trapping layer includes a first region and a second region. The first region has a first dopant and is adjacent to the first electrode. The second region has a second dopant and is adjacent to the second electrode.

[0009] The present invention provides a method for manufacturing a resistance random access memory, comprising the following steps: providing a first electrode; forming a charge trapping layer on the first electrode; and forming a second electrode on the charge trapping layer.

[0010] The present invention provides a method for operating a memory element, comprising the following steps. The resistive random access memory (RRAM) described above is provided. During a set operation, a positive bias is applied to the second electrode, causing multiple electrons to be injected from the first electrode into the first region of the charge trapping layer and blocked by the second region of the charge trapping layer. During a reset operation, a negative bias is applied to the second electrode, causing electrons to escape from the first region of the charge trapping layer to the first electrode.

[0011] Based on the above, the resistive random access memory of the present invention is only a 1R memory structure, which has a nonlinear resistance value and does not require additional selection elements. Therefore, compared with existing RRAM (such as 1D1R and 1S1R structures), the RRAM of the present invention has a smaller area. In addition, the RRAM of the present invention can omit the initial formation step (forming-free), so it does not require a large initial formation voltage for activation to avoid damage to the RRAM structure, thereby improving reliability. On the other hand, the RRAM of the present invention does not require the formation of a filament and ion movement, thereby achieving low power consumption.

[0012] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1FIG. 1 is a cross-sectional diagram of a resistance random access memory according to a first embodiment of the present invention.

[0014] Figure 2A FIG. 4 is a perspective view of a resistance random access memory according to a second embodiment of the present invention.

[0015] Figure 2B for Figure 2A Schematic cross-sectional view of a storage unit.

[0016] Figures 3A to 3D for Figure 1 Schematic diagram of the operation of resistive random access memory.

[0017] Description of Figure Numbers:

[0018] 10, 20: Resistive Random Access Memory;

[0019] 201: base;

[0020] 102, 202: first electrode;

[0021] 203: dielectric layer;

[0022] 104, 204: charge trapping layer;

[0023] 205: storage unit;

[0024] 106, 206: first area;

[0025] 108, 208: Second area;

[0026] 110, 210: second electrode;

[0027] D1: first direction;

[0028] D2: second direction;

[0029] D3: third direction;

[0030] S: stacked structure. DETAILED DESCRIPTION

[0031] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Identical or similar reference numerals denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0032] Figure 1 FIG. 1 is a cross-sectional diagram of a resistance random access memory according to a first embodiment of the present invention.

[0033] Please refer to Figure 1 The resistance random access memory 10 of the first embodiment of the present invention includes a first electrode 102, a charge trapping layer 104, and a second electrode 110. The second electrode 110 is located on the first electrode 102. In one embodiment, the materials of the first electrode 102 and the second electrode 110 each include a conductive material, which can be formed by physical vapor deposition. The conductive material can be, for example, a metal material, a metal nitride, or a similar conductive material. The metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed from at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. In one embodiment, the first electrode 102 and the second electrode 110 can be different materials. For example, the first electrode 102 can be a TiN layer, and the second electrode 110 can be a Ta layer. Alternatively, the first electrode 102 may be a Ta layer, and the second electrode 110 may be a Hf layer. In another embodiment, the first electrode 102 and the second electrode 110 may be made of the same material. For example, the first electrode 102 and the second electrode 110 may both be TiN layers or Ta layers.

[0034] The charge trapping layer 104 is located between the first electrode 102 and the second electrode 110 . The charge trapping layer 104 includes a first region 106 and a second region 108 . The first region 106 has a first dopant and is adjacent to the first electrode 102 . The second region 108 has a second dopant and is adjacent to the second electrode 110 .

[0035] In one embodiment, the charge trapping layer 104 is made of an insulating material with a band gap of less than 5 eV. The insulating material includes at least one selected from the group consisting of TiO2, NiO, HfO, HfO2, ZrO, ZrO2, Ta2O5, ZnO, WO3, CoO, and Nb2O5. For example, the charge trapping layer 104 may be made of TiO2. However, the present invention is not limited thereto. In other embodiments, the band gap of the charge trapping layer 104 material may be adjusted as needed.

[0036] In one embodiment, the first dopant and the second dopant each include at least one selected from the group consisting of Ti, Zr, Fe, Co, Al, S, N, Ca, Cu, Pb, Sr, Hf, B, C, Mo, Zn, and Mg. In one embodiment, the first dopant and the second dopant may be different. For example, the first dopant may be Al, and the second dopant may be Hf. However, the present invention is not limited thereto. In other embodiments, as long as the types of the first dopant and the second dopant are adjusted so that the energy gap of the second region 108 containing the second dopant is greater than the energy gap of the first region 106 containing the first dopant, it falls within the scope of the present invention. In one embodiment, the energy gap of the second region 108 is at least 1 eV greater than the energy gap of the first region 106. Therefore, this embodiment can enhance the electron trapping capability of the first region 106 of the charge trapping layer 104 and suppress ionic movement in the first region 106 under an applied electric field, thereby keeping oxygen vacancies or other ions immobilized. On the other hand, the second region 108 of the charge trapping layer 104 can prevent or block electrons from flowing from the first region 106 (or the first electrode 102) to the second electrode 110, thereby further enhancing the electron trapping capability of the first region 106. In other words, the second region 108 of the charge trapping layer 104 can control the retention capability of the non-volatile resistance state, thereby improving the reliability of the resistance random access memory 10.

[0037] In one embodiment, the concentration of the first dopant in the first region 106 is between 1 at% and 50 at%. The concentration of the second dopant in the second region 108 is between 10 at% and 90 at%. In one embodiment, the thickness of the first region 106 may be approximately 5-15 nm, and the thickness of the second region 108 may be approximately 5-10 nm. However, the present invention is not limited thereto, and the thicknesses of the first region 106 and the second region 108 can be adjusted according to user requirements.

[0038] In one embodiment, when the first dopant and the second dopant are the same, the concentration of the first dopant in the first region 106 may be lower than the concentration of the second dopant in the second region 108. However, the present invention is not limited thereto. In other embodiments, when the first dopant and the second dopant are different, the concentration of the first dopant in the first region 106 may also be lower than the concentration of the second dopant in the second region 108.

[0039] In another embodiment, when the first dopant and the second dopant are the same, the concentration of the first dopant (or the concentration of the second dopant) in the first region 106 and the second region 108 of the charge trapping layer 104 may be distributed in a gradient, such that the concentration of the first dopant near the first electrode 102 is lower than the concentration of the second dopant near the second electrode 110.

[0040] The RRAM 10 of the first embodiment described above may be, for example, a planar charge trapping layer RRAM. However, the present invention is not limited thereto. In other embodiments, the RRAM may also be a stacked charge trapping layer RRAM, as described in detail below.

[0041] Figure 2A FIG. 4 is a perspective view of a resistance random access memory according to a second embodiment of the present invention. Figure 2B for Figure 2A Schematic cross-sectional view of a storage unit.

[0042] Please refer to Figure 2A and Figure 2B The resistance random access memory 20 of the second embodiment of the present invention includes a substrate 201, a plurality of first electrodes 202, a plurality of dielectric layers 203, a charge trapping layer 204, and a plurality of second electrodes 210. In one embodiment, the substrate 201 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate on an insulating layer (SOI).

[0043] The first electrode 202 and the dielectric layer 203 both extend along a first direction D1 and are stacked along a third direction D3 to form a stacked structure S. The materials and formation methods of the first electrode 202 are similar to those of the first electrode 102 described above and are not further described here. The material of the dielectric layer 203 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and may be formed by chemical vapor deposition, thermal oxidation, or the like.

[0044] The charge trapping layer 204 conformally and blanketly covers the surface (ie, the top surface and sidewalls) of the stacked structure S (which includes the first electrode 202 and the dielectric layer 203 stacked on each other).

[0045] The second electrode 210 extends along the second direction D2 and conformally covers the surface (i.e., the top surface and sidewalls) of the stacked structure S (which includes the stacked first electrode 202 and the dielectric layer 203). The intersection or overlap between the first electrode 202 and the second electrode 210 forms a memory cell 205. The materials and formation methods of the second electrode 210 are similar to those of the second electrode 110 described above and are not further described here. In one embodiment, the first direction D1, the second direction D2, and the third direction D3 are substantially perpendicular to each other.

[0046] like Figure 2BAs shown, memory cell 205 may include a portion of first electrode 202, a portion of charge trapping layer 204, and a portion of second electrode 210. Portions of charge trapping layer 204 are located on the sidewalls of a portion of first electrode 202, forming a vertical charge trapping layer. Portions of second electrode 210 are located on portion of charge trapping layer 204, such that portion of charge trapping layer 204 is located between portions of first electrode 202 and second electrode 210. Specifically, charge trapping layer 204 also includes a first region 206 and a second region 208. First region 206 has a first dopant and is adjacent to first electrode 202. Second region 208 has a second dopant and is adjacent to second electrode 210. Since the materials, concentrations, and thicknesses of charge trapping layer 204, first region 206, and second region 208 of the second embodiment are similar to those of charge trapping layer 104, first region 106, and second region 108 of the first embodiment, they will not be further described here.

[0047] Next, the manufacturing method of the resistance random access memory of the present invention will be described in detail. The resistance random access memory 10 of the first embodiment will be used as an example for description.

[0048] First, a first electrode 102 is provided. Next, a charge trapping layer 104 is formed on the first electrode 102. Thereafter, a second electrode 110 is formed on the charge trapping layer 104. Since the materials for the first electrode 102, the charge trapping layer 104, and the second electrode 110 have been described above, they will not be repeated here.

[0049] In one embodiment, the charge trapping layer 104 may be formed in situ by an atomic layer deposition process. In one embodiment, the atomic layer deposition process may be, for example, a plasma-enhanced atomic layer deposition (PEALD) process.

[0050] Specifically, the atomic layer deposition process includes performing multiple first deposition cycles to form multiple first material layers having an insulating material. Thereafter, multiple second deposition cycles are performed to form multiple second material layers having a first dopant. Then, the first deposition cycle and the second deposition cycle are repeated until a first region 106 of the charge trapping layer 104 having a desired thickness is formed. In one embodiment, the number of first deposition cycles may be greater than the number of second deposition cycles. For example, seven first deposition cycles may be performed to form seven TiO2 layers, and then one second deposition cycle may be performed to form one Al2O3 layer. Then, the steps of seven first deposition cycles and one second deposition cycle are repeated until the thickness of the first region 106 of the charge trapping layer 104 is approximately 10 nm. However, the present invention is not limited thereto, and as long as the number of first deposition cycles is greater than the number of second deposition cycles, it falls within the scope of the present invention.

[0051] The first region 106 of the charge trapping layer 104 is in-situ formed on the first electrode 102 by the atomic layer deposition process. The thickness and Al doping dose (or doping concentration) of the first region 106 can be adjusted, so that the breakdown voltage, operating voltage, and operating current level of the resistance random access memory can be effectively adjusted.

[0052] Similarly, after forming the first region 106 of the charge trapping layer 104, multiple third deposition cycles may be performed to form multiple third material layers comprising an insulating material. Subsequently, multiple fourth deposition cycles may be performed to form multiple fourth material layers comprising a second dopant. The third and fourth deposition cycles are then repeated until the second region 108 of the charge trapping layer 104 having a desired thickness is formed. In one embodiment, the number of fourth deposition cycles may be greater than the number of third deposition cycles. For example, one third deposition cycle may be performed to form one TiO2 layer, followed by nine fourth deposition cycles to form nine HfO2 layers. The third and fourth deposition cycles are then repeated once and nine times until the thickness of the second region 108 of the charge trapping layer 104 is approximately 10 nm. However, the present invention is not limited to this; as long as the number of fourth deposition cycles is greater than the number of third deposition cycles, it falls within the scope of the present invention.

[0053] The second region 108 of the charge trapping layer 104 is in-situ formed on the first electrode 102 by the atomic layer deposition process. The thickness and Hf doping dose (or doping concentration) of the second region 108 can be adjusted, so that the operating current level, resistance state retention, and equilibrium level of the resistance random access memory can be effectively adjusted.

[0054] Furthermore, because this embodiment uses an atomic layer deposition process to in-situ form the charge trapping layer, the resulting charge trapping layer can be conformally and uniformly deposited on the vertical sidewalls of the first electrode. Therefore, this atomic layer deposition process is suitable for high-density three-dimensional stacked RRAM arrays, meeting the current trend of thinner and smaller devices.

[0055] In another embodiment, the method for forming the charge trapping layer 104 may also include forming a material layer (e.g., a TiO2 layer) by chemical deposition, followed by an ion implantation process to dope Al into the TiO2 layer, thereby forming the first region 106 of the charge trapping layer 104. Alternatively, a material layer (e.g., an HfO2 layer) may be formed on the first region 106 by chemical deposition, followed by an ion implantation process to dope Ti into the HfO2 layer, thereby forming the second region 108 of the charge trapping layer 104.

[0056] Figures 3A to 3D for Figure 1 Schematic diagram of the operation of resistive random access memory.

[0057] The following description will be made by taking the resistance random access memory 10 of the first embodiment as an example. Figure 3A During the set state, a positive bias voltage (e.g., +4.0V) is applied to the second electrode 110, causing multiple electrons to be injected from the grounded (GND) first electrode 102 into the first region 106 of the charge trapping layer 104 and blocked by the second region 108 of the charge trapping layer 104. At this point, the resistance state of the charge trapping layer 104 changes from a high resistance state (HRS) to a low resistance state (LRS).

[0058] Please refer to Figure 3B During LRS reading, a negative read bias (e.g., -2 V) is applied to the second electrode 110, so that Fowler-Nordheim (FN) electrons are injected from the second electrode 110 into the first region 106, and the sum of the captured electrons and the FN electrons in the first region 106 is used to judge the state as a low resistance.

[0059] Please refer to Figure 3C During a reset, a negative bias (e.g., -8.0 V) is applied to the second electrode 110, causing the electrons to escape from the first region 106 of the charge storage layer 104 to the grounded first electrode 102. At this point, the resistance state of the charge trapping layer 104 changes from a low resistance state (LRS) to a high resistance state (HRS).

[0060] Please refer to Figure 3D During HRS reading, a negative reading bias (e.g., -2V) is applied to the second electrode 110, so that FN electrons are injected from the second electrode 110 into the first region 106. Since only FN electrons remain in the first region 106 without captured electrons, it is judged to be in a high resistance state.

[0061] In summary, the resistive random access memory of the present invention is a 1R memory structure, which has a nonlinear resistance value and does not require additional selection elements. Therefore, compared to existing RRAM (such as 1D1R and 1S1R architectures), the RRAM of the present invention has a smaller area. In addition, the RRAM of the present invention can omit the initial generation step, and therefore, does not require a high initial generation voltage for activation, thereby avoiding damage to the RRAM structure and thus improving reliability. On the other hand, the RRAM of the present invention can also omit filament formation and ion movement, thereby achieving low power consumption.

[0062] Furthermore, the present invention uses an atomic layer deposition process to in-situ form a charge trapping layer. Therefore, this atomic layer deposition process is applicable to high-density three-dimensional stacked RRAM arrays, which meets the current trend of thinner and smaller technologies.

[0063] Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined by the appended claims.

Claims

1. A resistance random access memory comprising: a first electrode; a second electrode, located on the first electrode, wherein the material of the first electrode is the same as that of the second electrode; A charge trapping layer is located between the first electrode and the second electrode, wherein the charge trapping layer is made of an insulating material with an energy gap of less than 5 eV, the insulating material comprising one selected from the group consisting of TiO2, HfO, HfO2, ZrO, ZrO2, Ta2O5, WO3, CoO, and Nb2O5, and the charge trapping layer comprises: a first region having a first dopant and being close to the first electrode; as well as A second region having a second dopant and being close to the second electrode, wherein the concentration of the first dopant in the first region is less than the concentration of the second dopant in the second region, wherein the concentration of the first dopant in the first region is between 1at% and 50at%, and the concentration of the second dopant in the second region is between 10at% and 90at%, so that the energy gap of the second region is at least 1eV larger than the energy gap of the first region, wherein the resistive random access memory is only a 1R memory structure.

2. The resistance random access memory according to claim 1, wherein the first dopant comprises at least one selected from the group consisting of Ti, Zr, Fe, Co, Al, S, N, Ca, Cu, Pb, Sr, Hf, B, C, Mo, Zn, and Mg.

3. The resistance random access memory according to claim 1, wherein the second dopant comprises at least one selected from the group consisting of Ti, Zr, Fe, Co, Al, S, N, Ca, Cu, Pb, Sr, Hf, B, C, Mo, Zn, and Mg. 4 . The resistance random access memory according to claim 1 , wherein the first dopant is different from the second dopant. 5 . The resistance random access memory according to claim 1 , wherein the first dopant and the second dopant are the same, and a concentration of the first dopant in the first region and a concentration of the second dopant in the second region are distributed in a gradient. 6 . The resistance random access memory according to claim 1 , wherein the first electrode extends along a first direction, the second electrode extends along a second direction, and the first direction and the second direction are substantially perpendicular to each other.

7. The resistance random access memory according to claim 6, wherein there are a plurality of first electrodes, the plurality of first electrodes and the plurality of dielectric layers all extend along the first direction and are stacked on each other along a third direction, and the charge trapping layer at least covers sidewalls of the plurality of first electrodes. 8 . The resistance random access memory according to claim 7 , wherein the charge trapping layer conformally covers surfaces of the first electrodes and the dielectric layers. 9 . The resistance random access memory according to claim 7 , wherein an overlap between each of the plurality of first electrodes and the corresponding second electrode forms at least one memory cell.

10. A method for manufacturing a resistance random access memory, comprising: providing a first electrode; forming a charge trapping layer on the first electrode, wherein the charge trapping layer is made of an insulating material having an energy gap of less than 5 eV, the insulating material comprising one selected from the group consisting of TiO2, HfO, HfO2, ZrO, ZrO2, Ta2O5, WO3, CoO, and Nb2O5; as well as forming a second electrode on the charge trapping layer, wherein the material of the first electrode is the same as that of the second electrode, and wherein the charge trapping layer comprises: a first region having a first dopant and being close to the first electrode; as well as a second region having a second dopant and being adjacent to the second electrode, wherein a concentration of the first dopant in the first region is less than a concentration of the second dopant in the second region, wherein the concentration of the first dopant in the first region is between 1 at % and 50 at %, and the concentration of the second dopant in the second region is between 10 at % and 90 at %, such that an energy gap of the second region is at least 1 eV greater than an energy gap of the first region, The resistance random access memory is a 1R memory structure.

11. The method for manufacturing a resistance random access memory according to claim 10 , wherein a method of forming the charge trapping layer comprises an atomic layer deposition process, and the atomic layer deposition process comprises: performing a plurality of first deposition cycles to form a plurality of first material layers having the insulating material; performing a plurality of second deposition cycles to form a plurality of second material layers having the first dopant, wherein the number of the plurality of first deposition cycles is greater than the number of the plurality of second deposition cycles; as well as The plurality of first deposition cycles and the plurality of second deposition cycles are repeated until the first region of the charge trapping layer is formed to a desired thickness, wherein the first region is close to the first electrode.

12. The method for manufacturing a resistance random access memory according to claim 11, wherein the atomic layer deposition process further comprises: performing a plurality of third deposition cycles to form a plurality of third material layers having the insulating material; performing a plurality of fourth deposition cycles to form a plurality of fourth material layers having the second dopant, wherein the number of the plurality of fourth deposition cycles is greater than the number of the plurality of third deposition cycles; as well as The plurality of third deposition cycles and the plurality of fourth deposition cycles are repeated until the second region of the charge trapping layer is formed to a desired thickness, wherein the second region is close to the second electrode.

13. A method for operating a resistance random access memory, comprising: Providing a resistance random access memory according to any one of claims 1 to 9; When setting, a positive bias is applied to the second electrode, so that a plurality of electrons are injected from the first electrode into the first region of the charge trapping layer and are blocked by the second region of the charge trapping layer; as well as During reset, a negative bias is applied to the second electrode, so that the electrons escape from the first region of the charge trapping layer to the first electrode.

14. The operating method of a resistance random access memory according to claim 13, further comprising applying a negative read bias to the second electrode during reading, so that FN electrons are injected from the second electrode into the first region, and determining whether the high resistance state or the low resistance state is determined by the total number of electrons in the first region. 15 . The operating method of the resistance random access memory according to claim 13 , wherein before setting or resetting, generating is not performed.

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