A fast response power-on / off reset circuit

Abstract

The application relates to the technical field of semiconductor integrated circuits, and particularly discloses a fast-response power-on and power-off reset circuit, which comprises a reset signal generation module, a fast power-on trigger module, a power-on reset module and a slow power-on trigger and power-off module; the reset signal generation module is used for outputting a power-on and power-off reset signal; the fast power-on trigger module is used for outputting a first trigger signal; the power-on reset module is used for outputting a reset adjustment signal; the slow power-on trigger and power-off module is used for outputting a second trigger signal; the slow power-on trigger and power-off module comprises a clamping module; the clamping module is used for clamping the second trigger signal to a high level when the power supply voltage VCC is powered off, so that the first trigger signal is a low level, and the power-on and power-off reset signal is a high level; the circuit controls the first trigger signal output by the fast power-on trigger module when the power supply voltage VCC is powered off by arranging the clamping module in the slow power-on trigger and power-off module, and ensures that the chip can be normally reset during use.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, in particular to a fast-response power-on and power-off reset circuit. BACKGROUND

[0002] The power-on and power-off reset circuit is widely used in flash memory chip design. It generates a reset signal when the power supply voltage is powered on and powered off, resets the internal circuit of the flash memory chip, and ensures that the internal circuit of the flash memory chip can start normally.

[0003] In the existing power-on and power-off reset circuit, it is generally triggered only in the case of separate fast power-on, fast power-off, slow power-on and slow power-off. If fast power-on or slow power-on is performed immediately after fast power-off, it is easy to trigger the situation to cause the flash memory chip to be unable to reset, especially when the power supply voltage is at the intermediate potential of fast power-off to non-0, which will cause the power-on and power-off reset circuit to be unable to generate the corresponding reset signal, resulting in the chip being unable to reset normally, and thus unable to work normally.

[0004] At present, there is no effective technical solution to the above problems. SUMMARY

[0005] The purpose of the present application is to provide a fast-response power-on and power-off reset circuit to avoid the situation of being unable to trigger the reset when the power supply voltage VCC is powered on after fast power-off to the intermediate potential of non-0, so as to ensure that the chip can be reset normally during use.

[0006] The present application provides a fast-response power-on and power-off reset circuit for generating a power-on and power-off reset signal when the power supply voltage VCC is powered on or powered off, the circuit comprising:

[0007] a reset signal generation module for outputting the power-on and power-off reset signal;

[0008] a fast power-on trigger module for outputting a first trigger signal, the input and output ends of which are connected with the power supply voltage VCC and the input end of the reset signal generation module, respectively;

[0009] a power-on reset module for outputting a reset adjustment signal, the input end of which is connected with the power supply voltage VCC and the output end of the fast power-on trigger module, and the output end of which is connected with the input end of the fast power-on trigger module and the input end of the reset signal generation module;

[0010] a slow power-on trigger and power-off module for outputting a second trigger signal, the input end of which is connected with the power supply voltage VCC, and the output end of which is connected with the input end of the fast power-on trigger module and the input end of the reset signal generation module;

[0011] The slow power-on trigger and power-off module comprises a clamping module for clamping the second trigger signal to a high level when the power supply voltage VCC is powered off, so that the first trigger signal is low and the power-on and power-off reset signal is high.

[0012] The fast response power-on and power-off reset circuit of the present application clamps the input voltage of the clamping module to the equivalent of the power supply voltage VCC when the power supply voltage VCC is powered off, flips the second trigger signal output by the slow power-on trigger and power-off module to high level instantaneously when the power supply voltage VCC drops, and pulls the first trigger signal generated by the fast power-on trigger module to low level instantaneously. At this time, the power supply voltage VCC can also normally trigger the generation of the corresponding power-on and power-off reset signal by the reset signal generation module when it is powered on again, so that the chip can be normally reset.

[0013] The fast response power-on and power-off reset circuit, wherein the slow power-on trigger and power-off module further comprises a first MOS transistor M1, a first capacitor C1, a first resistor R1 and a first inverter X1, the source of the first MOS transistor M1 is connected with the power supply voltage VCC, the drain of the first MOS transistor M1 is connected with the clamping module and the input of the first inverter X1, the first resistor R1 is connected with the power supply voltage VCC and one end of the first capacitor C1 respectively, the other end of the first capacitor C1 is connected with the clamping module, and the first inverter X1 is used for outputting the second trigger signal.

[0014] In the fast response power-on and power-off reset circuit of the example, the first resistor R1 and the first capacitor C1 constitute a low-pass filter for coupling the output voltage of the clamping module to a lower potential when the power supply voltage VCC is powered off rapidly, thereby pulling down the input voltage of the clamping module and making the second trigger signal output by the slow power-on trigger and power-off module high.

[0015] The fast response power-on and power-off reset circuit, wherein the clamping module comprises a second MOS transistor M2 and a third MOS transistor M3, the drain of the second MOS transistor M2 is connected with the drain of the first MOS transistor M1 and the input of the first inverter X1, the source of the second MOS transistor M2 is connected with the drain and gate of the third MOS transistor M3 and the other end of the first capacitor C1, and the source of the third MOS transistor M3 is grounded.

[0016] In the fast response power-on and power-off reset circuit of the example, when the power supply voltage VCC is rapidly powered off, the voltage at point B is coupled to a lower potential under the action of a low-pass filter composed of the first resistor R1 and the first capacitor C1, so that the second MOS transistor M2 is turned on, thereby pulling down the voltage at point A, and after being inverted by the first inverter X1, the slow power-on trigger and power-off module outputs a high-level second trigger signal.

[0017] The fast response power-on and power-off reset circuit, wherein the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are grounded.

[0018] The fast response power-on and power-off reset circuit, wherein the clamping module comprises a second resistor R2, one end of the second resistor R2 is connected with the drain of the first MOS transistor M1 and the input end of the first inverter X1, and the other end of the second resistor R2 is grounded.

[0019] In the fast response power-on and power-off reset circuit of the example, when the power supply voltage VCC is slowly powered off, the first MOS transistor M1 is turned off, the voltage at point A is pulled down by the second resistor R2, and after being inverted by the first inverter X1, the slow power-on trigger and power-off module outputs a high-level second trigger signal.

[0020] The fast response power-on and power-off reset circuit, wherein the fast power-on trigger module comprises a second capacitor C2, a second inverter X2, a third inverter X3, a fourth non-inverting buffer X4, a fourth MOS transistor M4 and a fifth MOS transistor M5, one end of the second capacitor C2 is connected with the power supply voltage VCC, the other end of the second capacitor C2 is connected with the drain of the fourth MOS transistor M4, the output end of the second inverter X2 and the input end of the third inverter X3, the gate of the fourth MOS transistor M4 is connected with the output end of the power-on reset module, the input end of the second inverter X2 and the output end of the third inverter X3 are connected with the input end of the fourth non-inverting buffer X4 and the drain of the fifth MOS transistor M5, the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5 are grounded, the gate of the fifth MOS transistor M5 is connected with the input end of the reset signal generation module and the output end of the slow power-on trigger and power-off module, and the output end of the fourth non-inverting buffer X4 is used to output a first trigger signal.

[0021] The power-on reset circuit has a fast response, wherein the power-on reset module comprises a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11 and a fifth flip-flop X5, the source of the sixth MOS transistor M6 is connected with the power supply voltage VCC, the drain of the sixth MOS transistor M6 is connected with the source of the seventh MOS transistor M7, the gate of the sixth MOS transistor M6 is connected with the output of the fast power-on trigger module, the drain of the seventh MOS transistor M7 is connected with the drain of the eighth MOS transistor M8, the gate of the eighth MOS transistor M8, the gate of the seventh MOS transistor M7 and the gate of the tenth MOS transistor M10, the source of the ninth MOS transistor M9 is connected with the power supply voltage VCC, the gate of the ninth MOS transistor M9 is connected with the output of the fast power-on trigger module, the drain of the ninth MOS transistor M9 is connected with one end of a third resistor R3, the other end of the third resistor R3 is connected with the drain of the tenth MOS transistor M10, the drain of the eleventh MOS transistor M11 and the input of the fifth flip-flop X5, the gate of the eleventh MOS transistor M11 is connected with the output of the fast power-on trigger module, the source of the eighth MOS transistor M8, the source of the tenth MOS transistor M10 and the source of the eleventh MOS transistor M11 are grounded, and the output of the fifth flip-flop X5 is used for outputting a reset adjustment signal.

[0022] The power-on reset circuit has a fast response, wherein the fifth flip-flop X5 is a Schmitt trigger.

[0023] The power-on reset circuit has a fast response, wherein the reset signal generation module comprises a sixth inverter X6, a seventh inverter X7, an eighth NOR gate X8, a ninth NAND gate X9 and a tenth flip-flop X10, the input of the sixth inverter X6 is connected with the input of the fast power-on trigger module and the output of the power-on reset module, the output of the sixth inverter X6 is connected with one input of the eighth NOR gate X8, the other input of the eighth NOR gate X8 is connected with the output of the slow power-on trigger and power-off module, the input of the fast power-on trigger module and the input of the seventh inverter X7, the output of the eighth NOR gate X8 is connected with one input of the tenth flip-flop X10, the output of the seventh inverter X7 is connected with one input of the ninth NAND gate X9, the other input of the ninth NAND gate X9 is connected with the output of the fast power-on trigger module and the input of the power-on reset module, the output of the ninth NAND gate X9 is connected with the other input of the tenth flip-flop X10, and the output of the tenth flip-flop X10 is used for outputting the power-on and power-off reset signal.

[0024] The tenth flip-flop X10 is an SR latch, the output end of the eighth NOR gate X8 is connected with the R end of the SR latch, and the output end of the ninth NAND gate X9 is connected with the S end of the SR latch.

[0025] As can be seen from the above, the application provides a fast response power-on and power-off reset circuit, a clamping module is arranged in the slow power-on trigger and power-off module to control the first trigger signal output by the fast power-on trigger module when the power supply voltage VCC is powered off, so as to avoid the situation that the first trigger signal fails to flip when the power supply voltage VCC is rapidly powered off to an intermediate potential and is powered on, and to make the power-on and power-off work in coordination and ensure that the chip can be normally reset during use. BRIEF DESCRIPTION OF DRAWINGS

[0026] Fig. 1 A structural schematic diagram of a fast response power-on and power-off reset circuit provided by the application embodiment.

[0027] Fig. 2 A circuit diagram of a fast response power-on and power-off reset circuit provided by the application embodiment.

[0028] Fig. 3 A circuit diagram of a slow power-on trigger and power-off module.

[0029] Reference signs: 100, reset signal generation module; 200, fast power-on trigger module; 300, power-on reset module; 400, slow power-on trigger and power-off module; 410, clamping module. DETAILED DESCRIPTION

[0030] The technical solutions in the application embodiments will be clearly and completely described below with reference to the drawings in the application embodiments. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. The components of the application embodiments described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the application. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the application.

[0031] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0032] The existing power-on and power-off reset circuit triggers the generation of a corresponding high or low level reset signal to drive chip reset according to the change of the power supply voltage VCC. When the power supply voltage VCC is fast powered on or slowly powered on after being fast powered off to an intermediate potential, the reset signal may fail to complete the flip during the power-off process. At this time, fast power-on or slow power-on will cause the reset signal to have no change throughout the process, resulting in the chip being unable to reset normally.

[0033] Please refer to Figs. 1-3 , Figs. 1-3 is a fast response power-on and power-off reset circuit in some embodiments of the present application, which is used to generate a power-on and power-off reset signal when the power supply voltage VCC is powered on or powered off. The circuit comprises:

[0034] The reset signal generation module 100 is used to output the power-on and power-off reset signal.

[0035] The fast power-on trigger module 200 is used to output a first trigger signal, and its input and output ends are connected with the power supply voltage VCC and the input end of the reset signal generation module 100, respectively.

[0036] The power-on reset module 300 is used to output a reset adjustment signal, and its input end is connected with the power supply voltage VCC and the output end of the fast power-on trigger module 200, and its output end is connected with the input end of the fast power-on trigger module 200 and the input end of the reset signal generation module 100.

[0037] The slow power-on trigger and power-off module 400 is used to output a second trigger signal, and its input end is connected with the power supply voltage VCC, and its output end is connected with the input end of the fast power-on trigger module 200 and the input end of the reset signal generation module 100.

[0038] The slow power-on trigger and power-off module 400 comprises a clamping module 410, which is used to clamp the second trigger signal to a high level when the power supply voltage VCC is powered off, so that the first trigger signal is low, and the power-on and power-off reset signal is high.

[0039] The fast response power-on and power-off reset circuit of the present application can generate and output corresponding power-on and power-off reset signals according to the fast power-on, slow power-on, fast power-off and slow power-off changes of the power supply voltage VCC.

[0040] Specifically, when the power voltage VCC is fast powered on, the power voltage VCC starts at a low voltage state, so that the first trigger signal output by the fast power-on trigger module 200 is at a low level, and correspondingly, the power-on and power-off reset signal output by the reset signal generation module 100 is at a high level; as the power voltage VCC is fast powered on and increases, the first trigger signal output by the fast power-on trigger module 200 will change to a high level, so that the power-on and power-off reset signal output by the reset signal generation module 100 changes to a low level. Therefore, during the process of fast power-on of the power voltage VCC, the power-on and power-off reset signal output by the reset signal generation module 100 generates a pulse at a high level, that is, generates a fluctuation information from high level to low level, and the pulse is used for fast power-on reset of the power voltage VCC.

[0041] More specifically, when the power voltage VCC is slow powered on, the power voltage VCC starts at a low voltage state, so that the first trigger signal output by the fast power-on trigger module 200 is at a low level, and the power-on reset module 300 is opened. At this time, the reset adjustment signal output by the power-on reset module 300 is at a low level, and the power-on and power-off reset signal output by the reset signal generation module 100 is at a high level; as the power voltage VCC is slow powered on and increases, the reset adjustment signal output by the power-on reset module 300 flips to a high level, so that the first trigger signal output by the fast power-on trigger module 200 flips to a high level. At this time, the slow power-on trigger and power-off module 400 is opened, so that the second trigger signal output by the slow power-on trigger and power-off module 400 is at a low level, so that the power-on and power-off reset signal output by the reset signal generation module 100 changes to a low level. Therefore, during the process of slow power-on of the power voltage VCC, the power-on and power-off reset signal output by the reset signal generation module 100 generates a pulse at a high level, that is, generates a fluctuation information from high level to low level, and the pulse is used for slow power-on reset of the power voltage VCC.

[0042] More specifically, when the power voltage VCC is fast powered on, the power voltage VCC starts at a low voltage state, so that the first trigger signal output by the fast power-on trigger module 200 is at a low level, and correspondingly, the power-on and power-off reset signal output by the reset signal generation module 100 is at a high level; as the power voltage VCC is fast powered on and increases, the first trigger signal output by the fast power-on trigger module 200 will change to a high level, so that the power-on and power-off reset signal output by the reset signal generation module 100 changes to a low level. Therefore, during the process of fast power-on of the power voltage VCC, the power-on and power-off reset signal output by the reset signal generation module 100 generates a pulse at a high level, that is, generates a fluctuation information from high level to low level, and the pulse is used for fast power-on reset of the power voltage VCC.

[0043] More specifically, when the power voltage VCC is slowly powered down, the power voltage VCC is initially at a high voltage, the clamping module 410 pulls the voltage at the input end of the clamping module 410 to the size of the power voltage VCC, and when the power voltage VCC is slowly powered down, the clamping module 410 lowers the voltage at the input end of the clamping module 410, so that the second trigger signal output by the slow power-on trigger and power-down module 400 is at a high level, thereby setting the output end of the reset signal generation module 100 to output a high-level power-on and power-down reset signal; the high-level power-on and power-down reset signal is used for slow power-down reset of the power voltage VCC.

[0044] Specifically, during the fast power-down and slow power-down processes, when the power voltage VCC is powered down, the clamping module 410 pulls the voltage at the input end of the clamping module 410 to a low level, so that the first trigger signal generated by the fast power-on trigger module 200 is pulled to a low level instantaneously, that is, the state of the fast power-on trigger module 200 at this time conforms to the preparation state of the fast power-on operation, so that the power voltage VCC is immediately powered on at this time and no trigger failure occurs.

[0045] The fast response power-on and power-down reset circuit of the embodiment of the present application clamps the input voltage of the clamping module 410 to the power voltage VCC when the power voltage VCC is powered down (fast power-down or slow power-down), instantaneously flips the second trigger signal output by the slow power-on trigger and power-down module 400 to a high level when the power voltage VCC is powered down, and instantaneously pulls the first trigger signal generated by the fast power-on trigger module 200 to a low level, at this time, the power voltage VCC is powered on again and can normally trigger the reset signal generation module 100 to generate a corresponding power-on and power-down reset signal, so that the chip can be normally reset; the fast response power-on and power-down reset circuit of the embodiment of the present application controls the first trigger signal output by the fast power-on trigger module 200 when the power voltage VCC is powered down by arranging the clamping module 410 in the slow power-on trigger and power-down module 400, so that the power-on and power-down cooperate to work, and ensure that the chip can be normally reset during use.

[0046] In some preferred embodiments, the slow power-on trigger and power-down module 400 further comprises a first MOS transistor M1, a first capacitor C1, a first resistor R1, and a first inverter X1, the source of the first MOS transistor M1 is connected with the power voltage VCC, the drain of the first MOS transistor M1 is connected with the clamping module 410 and the input end of the first inverter X1, the first resistor R1 is connected with the power voltage VCC and one end of the first capacitor C1 respectively, the other end of the first capacitor C1 is connected with the clamping module 410, and the first inverter X1 is used for outputting the second trigger signal.

[0047] Specifically, the first MOS transistor M1 is a PMOS transistor.

[0048] More specifically, the first resistor R1 and the first capacitor C1 form a low-pass filter, which is used to couple the voltage at the output of the clamping module 410 to a lower potential when the power supply voltage VCC is powered down quickly, so as to pull down the voltage at the input of the slow power-up trigger and power-down module 400, i.e. to pull down the voltage at the drain of the first MOS transistor M1 to a low level, and then to make the first inverter X1 output a high level, i.e. to make the second trigger signal output by the slow power-up trigger and power-down module 400 be a high level.

[0049] In some preferred embodiments, the clamping module 410 comprises a second MOS transistor M2 and a third MOS transistor M3, the drain of the second MOS transistor M2 is connected with the drain of the first MOS transistor M1 and the input of the first inverter X1, the source of the second MOS transistor M2 is connected with the drain and gate of the third MOS transistor M3 and the other end of the first capacitor C1, and the source of the third MOS transistor M3 is grounded.

[0050] Specifically, the second MOS transistor M2 and the third MOS transistor M3 are both NMOS transistors.

[0051] More specifically, during the process of powering down the power supply voltage VCC quickly, at the beginning, Fig. 2 The voltage at point B (the source of the second MOS transistor M2) is clamped to be within the threshold voltage of the third MOS transistor M3 by the third MOS transistor M3, and the voltage at point B is pulled down; more specifically, the second MOS transistor M2 and the third MOS transistor M3 are both intrinsic MOS transistors, and the threshold voltage of the intrinsic MOS transistor is around 0V, so the voltage at point B is also pulled down to be around 0V, and then Fig. 2 The voltage at point A (the drain of the first MOS transistor M1) is pulled to be the same as the power supply voltage VCC; when the power supply voltage VCC is powered down quickly, the voltage at point B is coupled to a lower potential under the action of the low-pass filter formed by the first resistor R1 and the first capacitor C1, so that the second MOS transistor M2 is turned on, and then the voltage at point A is pulled down, and after being inverted by the first inverter X1, the second trigger signal output by the slow power-up trigger and power-down module 400 is a high level.

[0052] In some preferred embodiments, the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are grounded.

[0053] In some preferred embodiments, the clamping module 410 comprises a second resistor R2, one end of the second resistor R2 is connected with the drain of the first MOS transistor M1 and the input of the first inverter X1, and the other end of the second resistor R2 is grounded.

[0054] Specifically, during the process of powering down the power supply voltage VCC slowly, at the beginning, Fig. 2The voltage at point A is pulled up to the size of the power voltage source VCC by the first MOS tube M1. When the power voltage VCC is slowly powered down, the first MOS tube M1 is closed, the voltage at point A is pulled low by the second resistor R2, and after being inverted by the first inverter X1, the slow power-on trigger and power-down module 400 outputs a high-level second trigger signal.

[0055] More specifically, the fast-response power-on and power-off reset circuit of the embodiment of the present application can convert the second trigger signal into a high level by using different devices in the clamping module 410 during fast power-down and slow power-down, can match the voltage of different rates of change for use, and can ensure that the reset signal generation module 100 can successfully generate a corresponding power-on and power-off reset signal, so as to ensure that the chip can be normally reset for use.

[0056] In some preferred embodiments, the fast power-on trigger module 200 includes a second capacitor C2, a second inverter X2, a third inverter X3, a fourth non-inverting buffer X4, a fourth MOS tube M4, and a fifth MOS tube M5. One end of the second capacitor is connected to the power voltage VCC, the other end of the second capacitor C2 is connected to the drain of the fourth MOS tube N4, the output end of the second inverter X2, and the input end of the third inverter X3, the gate of the fourth MOS tube is connected to the output end of the power-on reset module 300, the input end of the second inverter X2 and the output end of the third inverter X3 are connected to the input end of the fourth non-inverting buffer X4 and the drain of the fifth MOS tube M5, the source of the fourth MOS tube M4 and the source of the fifth MOS tube M5 are grounded, the gate of the fifth MOS tube M5 is connected to the input end of the reset signal generation module 100 and the output end of the slow power-on trigger and power-down module 400, and the output end of the fourth non-inverting buffer X4 is used to output the first trigger signal.

[0057] Specifically, the source of the fourth MOS tube M4 and the source of the fifth MOS tube M5 are both NMOS tubes.

[0058] More specifically, during the fast power-on of the power voltage VCC, at the beginning, the power voltage VCC is a low voltage, the second capacitor C2 pulls up the voltage at point A to the size of the power voltage VCC, and the first trigger signal output by the fourth non-inverting buffer X4 is a low level. Fig. 2The voltage at point D is coupled to a high level, which is inverted by the third inverter X3 and buffered by the fourth non-inverting buffer X4, and then becomes a low level as the first trigger signal of the fast power-on trigger module 200, so that the reset signal generation module 100 is set, and outputs a high level power-on and power-off reset signal (after power-off is completed, the power-on and power-off reset signal is always high level); when the power supply voltage VCC is increased to a sufficient value during the fast power-on process, the power-on reset module 300 inverts and outputs a high level reset adjustment signal to the gate of the fourth MOS tube M4, so that the voltage at point D is pulled to a low level by the fourth MOS tube M4, thereby inverting the first trigger signal of the fast power-on trigger module 200 to a high level, and then resetting the reset signal generation module 100 to output a low level power-on and power-off reset signal, that is, during the fast power-on process, the reset signal generation module 100 outputs a high level pulse (high and low level change).

[0059] In some preferred embodiments, the power-on reset module 300 comprises a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11 and a fifth flip-flop X5, the source of the sixth MOS tube M6 is connected with the power supply voltage VCC, the drain of the sixth MOS tube M6 is connected with the source of the seventh MOS tube M7, the gate of the sixth MOS tube M6 is connected with the output of the fast power-on trigger module 200, the drain of the seventh MOS tube M7 is connected with the drain of the eighth MOS tube M8, the gate of the eighth MOS tube M8, the gate of the seventh MOS tube M7 and the gate of the tenth MOS tube M10, the source of the ninth MOS tube M9 is connected with the power supply voltage VCC, the gate of the ninth MOS tube M9 is connected with the output of the fast power-on trigger module 200, the drain of the ninth MOS tube M9 is connected with one end of the third resistor R3, the other end of the third resistor R3 is connected with the drain of the tenth MOS tube M10, the drain of the eleventh MOS tube M11 and the input of the fifth flip-flop X5, the gate of the eleventh MOS tube M11 is connected with the output of the fast power-on trigger module 200, the source of the eighth MOS tube M8, the source of the tenth MOS tube M10 and the source of the eleventh MOS tube M11 are grounded, and the output of the fifth flip-flop X5 is used to output the reset adjustment signal.

[0060] Specifically, the ninth MOS tube M9, the sixth MOS tube M6 and the seventh MOS tube M7 are all PMOS tubes, and the eighth MOS tube M8, the tenth MOS tube M10 and the eleventh MOS tube M11 are all NMOS tubes.

[0061] More specifically, the power-on reset module 300 is used to generate a high level reset adjustment signal to pull the voltage at point D to a low level to adjust the first trigger signal to a high level when the power supply voltage VCC is powered on.

[0062] More specifically, in the slow power-on process of the power supply voltage VCC, at the beginning, the voltage at point A in the slow power-on trigger and power-down module 400 is pulled low by the second resistor R2, the second trigger signal output by the slow power-on trigger and power-down module 400 is high, the voltage at point C of the fast power-on trigger module 200 is pulled low by the fifth MOS transistor M5, the first trigger signal is low, at this time, the reset adjustment signal output by the power-on reset module 300 is low, the reset signal generation module 100 is set and outputs a high power-on and power-down reset signal; when the power supply voltage VCC is large enough in the slow power-on process, the reset adjustment signal of the power-on reset module 300 is flipped to high, the voltage at point D in the fast power-on trigger module 200 is pulled low by the fourth MOS transistor M4, so that the first trigger signal of the fast power-on trigger module 200 is flipped to high, at this time, the first MOS transistor M1 of the slow power-on trigger and power-down module 400 is turned on, the voltage at point A is pulled up to high, so that the second trigger signal output by the slow power-on trigger and power-down module 400 is low, the low second trigger signal or the high reset adjustment signal resets the reset signal generation module 100, so that the power-on and power-down reset signal becomes low, that is, in the slow power-on process, the reset signal generation module 100 outputs a high pulse (high-low level change).

[0063] In some preferred embodiments, the fifth flip-flop X5 is a Schmitt trigger.

[0064] Specifically, the Schmitt trigger has two stable states, but unlike general flip-flops, the Schmitt trigger uses potential triggering, and its state is maintained by the input signal potential; for input signals with different change directions of negative direction decrease and positive direction increase, the Schmitt trigger has different threshold voltages; in the application embodiment, the power-on reset module 300 sets the Schmitt trigger as the output end of the reset adjustment signal, which can ensure that the reset adjustment signal is flipped to high in time to reset the reset signal generation module 100.

[0065] In some preferred embodiments, the reset signal generation module 100 comprises a sixth inverter X6, a seventh inverter X7, an eighth NOR gate X8, a ninth NAND gate X9, and a tenth flip-flop X10, an input end of the sixth inverter X6 is connected with an input end of the fast power-on trigger module 200 and an output end of the power-on reset module 300, an output end of the sixth inverter X6 is connected with an input end of the eighth NOR gate X8, another input end of the eighth NOR gate X8 is connected with an output end of the slow power-on trigger and power-off module 400, an input end of the fast power-on trigger module 200, and an input end of the seventh inverter X7, an output end of the eighth NOR gate X8 is connected with an input end of the tenth flip-flop X10, an output end of the seventh inverter X7 is connected with an input end of the ninth NAND gate X9, another input end of the ninth NAND gate X9 is connected with an output end of the fast power-on trigger module 200 and an input end of the power-on reset module 300, an output end of the ninth NAND gate X9 is connected with another input end of the tenth flip-flop X10, and an output end of the tenth flip-flop X10 is used to output the power-on and power-off reset signal.

[0066] Specifically, the reset signal generation module 100 adjusts the output state of the tenth flip-flop X10 according to the relationship among the first trigger signal, the second trigger signal, and the reset adjustment signal, to generate a corresponding power-on and power-off reset signal, so that the working intervals of fast power-on, slow power-on, fast power-off, and slow power-off overlap, thereby enabling the fast power-on trigger module 200, the power-on reset module 300, and the slow power-on trigger and power-off module 400 to work in coordination to adjust the reset signal generation module 100, and thus ensuring that the chip can be normally reset during use.

[0067] In some preferred embodiments, the tenth flip-flop X10 is an SR latch, the output end of the eighth NOR gate X8 is connected with the R end of the SR latch, and the output end of the ninth NAND gate X9 is connected with the S end of the SR latch.

[0068] Specifically, the SR latch, also known as the RS flip-flop, can adjust its reset and set states according to the input signals at the S and R ends.

[0069] In summary, the embodiment of the present application provides a fast-response power-on and power-off reset circuit, which controls the first trigger signal output by the fast power-on trigger module 200 when the power supply voltage VCC is powered off, by setting the clamping module 410 in the slow power-on trigger and power-off module 400, thereby avoiding the situation that the first trigger signal fails to flip when the power supply voltage VCC is rapidly powered off to an intermediate potential and then powered on, enabling the power-on and power-off to work in coordination, and thus ensuring that the chip can be normally reset during use.

[0070] The function modules in the various embodiments of the present application can be integrated together to form an independent part, or can exist independently, or two or more modules can be integrated to form an independent part.

[0071] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0072] The above description is merely illustrative of the application, and not in limitation of the principles of the application. Any modification and change of the application, which can be made by those skilled in the art, shall fall within the scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall within the scope of the application.

Claims

1. A fast-response power-on / power-off reset circuit, used to generate a power-on / power-off reset signal when the power supply voltage VCC is powered on or off, characterized in that, The circuit includes: A reset signal generation module (100) is used to output the power-on and power-off reset signal; The fast power-on trigger module (200) is used to output a first trigger signal, and its input and output terminals are respectively connected to the power supply voltage VCC and the input terminal of the reset signal generation module (100); The power-on reset module (300) is used to output a reset adjustment signal. Its input terminal is connected to the power supply voltage VCC and the output terminal of the fast power-on trigger module (200), and its output terminal is connected to the input terminal of the fast power-on trigger module (200) and the input terminal of the reset signal generation module (100). The slow power-on trigger and power-off module (400) is used to output a second trigger signal. Its input terminal is connected to the power supply voltage VCC, and its output terminal is connected to the input terminal of the fast power-on trigger module (200) and the input terminal of the reset signal generation module (100). The slow power-on trigger and power-off module (400) includes a clamping module (410), which is used to clamp the second trigger signal to a high level when the power supply voltage VCC is powered off, so that the first trigger signal is at a low level and the power-on / power-off reset signal is at a high level.

2. The fast-response power-on / power-off reset circuit according to claim 1, characterized in that, The slow power-on trigger and power-off module (400) further includes: a first MOS transistor M1, a first capacitor C1, a first resistor R1 and a first inverter X1. The source of the first MOS transistor M1 is connected to the power supply voltage VCC. The drain of the first MOS transistor M1 is connected to the input terminal of the clamping module (410) and the first inverter X1. The two ends of the first resistor R1 are respectively connected to the power supply voltage VCC and one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the clamping module (410). The first inverter X1 is used to output a second trigger signal.

3. The fast-response power-on / power-off reset circuit according to claim 2, characterized in that, The clamping module (410) includes a second MOS transistor M2 and a third MOS transistor M3. The drain of the second MOS transistor M2 is connected to the drain of the first MOS transistor M1 and the input terminal of the first inverter X1. The source of the second MOS transistor M2 is connected to the drain and gate of the third MOS transistor M3 and the other end of the first capacitor C1. The source of the third MOS transistor M3 is grounded.

4. The fast-response power-on / power-off reset circuit according to claim 3, characterized in that, The gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are grounded.

5. A fast-response power-on / power-off reset circuit according to claim 2 or 3, characterized in that, The clamping module (410) includes a second resistor R2, one end of which is connected to the drain of the first MOS transistor M1 and the input of the first inverter X1, and the other end of which is grounded.

6. The fast-response power-on / power-off reset circuit according to claim 1, characterized in that, The fast power-on trigger module (200) includes: a second capacitor C2, a second inverter X2, a third inverter X3, a fourth non-inverting buffer X4, a fourth MOSFET M4, and a fifth MOSFET M5. One end of the second capacitor is connected to the power supply voltage VCC. The other end of the second capacitor C2 is connected to the drain of the fourth MOSFET M4, the output of the second inverter X2, and the input of the third inverter X3. The gate of the fourth MOSFET is connected to the output of the power-on reset module (300). The input of the second inverter X2 and the output of the third inverter X3 are connected to the input of the fourth non-inverting buffer X4 and the drain of the fifth MOSFET M5. The source of the fourth MOSFET M4 and the source of the fifth MOSFET M5 are grounded. The gate of the fifth MOSFET M5 is connected to the input of the reset signal generation module (100) and the output of the slow power-on trigger and power-off module (400). The output of the fourth non-inverting buffer X4 is used to output a first trigger signal.

7. The fast-response power-on / power-off reset circuit according to claim 1, characterized in that, The power-on reset module (300) includes: a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, and a fifth flip-flop X5. The source of the sixth MOSFET M6 is connected to the power supply voltage VCC, the drain of the sixth MOSFET M6 is connected to the source of the seventh MOSFET M7, the gate of the sixth MOSFET M6 is connected to the output terminal of the fast power-on trigger module (200), and the drain of the seventh MOSFET M7 is connected to the drain of the eighth MOSFET M8, the gate of the eighth MOSFET M8, the gate of the seventh MOSFET M7, and the gate of the tenth MOSFET M10. The ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, and the eleventh MOSFET M11 are all connected to the power supply voltage VCC. The source of the ninth MOS transistor M9 is connected to the power supply voltage VCC. The gate of the ninth MOS transistor M9 is connected to the output terminal of the fast power-on trigger module (200). The drain of the ninth MOS transistor M9 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the drain of the tenth MOS transistor M10, the drain of the eleventh MOS transistor M11, and the input terminal of the fifth flip-flop X5. The gate of the eleventh MOS transistor M11 is connected to the output terminal of the fast power-on trigger module (200). The sources of the eighth MOS transistor M8, the tenth MOS transistor M10, and the eleventh MOS transistor M11 are grounded. The output terminal of the fifth flip-flop X5 is used to output a reset adjustment signal.

8. A fast-response power-on / power-off reset circuit according to claim 7, characterized in that, The fifth trigger X5 is a Schmitt trigger.

9. A fast-response power-on / power-off reset circuit according to claim 1, characterized in that, The reset signal generation module (100) includes: a sixth inverter X6, a seventh inverter X7, an eighth NOR gate X8, a ninth NAND gate X9, and a tenth flip-flop X10. The input terminal of the sixth inverter X6 is connected to the input terminal of the fast power-on trigger module (200) and the output terminal of the power-on reset module (300). The output terminal of the sixth inverter X6 is connected to one input terminal of the eighth NOR gate X8. The other input terminal of the eighth NOR gate X8 is connected to the output terminal of the slow power-on trigger and power-off module (400) and the input terminal of the fast power-on trigger module (200). The output terminal of the seventh inverter X7 is connected to the input terminal of the eighth NOR gate X8, the output terminal of the eighth NOR gate X8 is connected to one input terminal of the tenth flip-flop X10, the output terminal of the seventh inverter X7 is connected to one input terminal of the ninth NAND gate X9, the other input terminal of the ninth NAND gate X9 is connected to the output terminal of the fast power-on trigger module (200) and the input terminal of the power-on reset module (300), the output terminal of the ninth NAND gate X9 is connected to the other input terminal of the tenth flip-flop X10, and the output terminal of the tenth flip-flop X10 is used to output the power-on and power-off reset signal.

10. A fast-response power-on / power-off reset circuit according to claim 9, characterized in that, The tenth flip-flop X10 is an SR latch, the output of the eighth NOR gate X8 is connected to the R terminal of the SR latch, and the output of the ninth NAND gate X9 is connected to the S terminal of the SR latch.

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