Granularity error reporting for multi-pass programming of non-volatile memory

Abstract

A system includes a memory component for writing flag bits into a set of memory cells programmed by a multi-pass programming command after a second programming pass has been completed in response to such a command. A processing means operatively coupled to the memory component is used to perform the multi-pass programming of the set of memory cells in association with logical addresses. Upon receiving a read request, the processing means determines that a second logical address within the read request does not match the logical address associated with data stored at a physical address in the set of memory cells. The processing means further determines the number of first values ​​within the plurality of flag bits, and reports an uncorrectable data error to a host computing device in response to the number of first values ​​not meeting a threshold criterion.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to granular error reporting for multi-pass programming of non-volatile memory. Background Technology

[0002] A memory subsystem can be a storage system, a memory module, or a combination of a storage device and a memory module. A memory subsystem may contain one or more memory components for storing data. For example, memory components can be non-volatile memory components and volatile memory components. Generally, a host system can utilize a memory subsystem to store data at memory components and retrieve data from memory components. Summary of the Invention

[0003] A system includes: a memory component configured to write a plurality of flag bits into a set of memory cells programmed by a multi-pass programming command after completing a second pass programming in response to the multi-pass programming command; and a processing means operatively coupled to the memory component, the processing means being configured to: perform multi-pass programming of the set of memory cells in association with logical addresses; upon receiving a read request, determine that a second logical address in the read request does not match the logical address associated with data stored at a physical address in the set of memory cells; determine a number of first values ​​in the plurality of flag bits; and, in response to the number of first values ​​not meeting a threshold criterion, report to a host computing device an uncorrectable data error caused by at least some data stored on the first page of the set of memory cells.

[0004] This disclosure further provides a method comprising: performing multiple passes of programming a set of memory cells of a memory component in response to a write request having a logical address; writing a plurality of flag bits into the set of memory cells in response to completing a second pass of programming in the multiple passes; determining, in response to a read request, that a second logical address of the read request does not match the logical address associated with a physical address of the set of memory cells; determining a number of first values ​​in the plurality of flag bits; and reporting a page fault indicating that the home page has no data to a host computing device in response to the number of the first values ​​satisfying a threshold criterion, the home page having been programmed during the second pass of programming.

[0005] This disclosure also provides a system comprising: a memory component; and a processing means operatively coupled to the memory component, the processing means being configured to: perform multiple passes of programming a set of memory cells of the memory component in response to a write request including a logical address; upon receiving a read request, determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address in the set of memory cells; sum the first data from the first pass of programming to generate combined data; generate a first value by performing an arithmetic operation on the combined data; generate a difference by comparing the first value with a second value of the second data from the second pass of programming; and report a page fault to a host computing device in response to the difference satisfying a threshold criterion. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1A An example computing environment including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 1B According to some embodiments of this disclosure Figure 1A A block diagram of the memory subsystem.

[0009] Figure 2A This is a graph representing the state of programming into a set of memory cells before and after a second programming pass, according to some embodiments of the present disclosure.

[0010] Figure 2B This is a graphical representation of how programming data can be read a second time when the first page does not contain data, according to some embodiments of this disclosure.

[0011] Figure 3 This is a flowchart of an example method for providing granular error reporting for multi-pass programming of non-volatile memory according to some embodiments of the present disclosure.

[0012] Figure 4 This is a flowchart of an example method for providing granular error reporting for multi-pass programming of non-volatile memory according to other embodiments of this disclosure.

[0013] Figure 5 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0014] This disclosure relates to granular and precise error reporting for multi-pass programming of non-volatile (NVM) memory. The memory subsystem may be a storage device, a memory module, or a mixture of both. Examples of storage devices and memory modules are described below. Figure 1A Description. Generally speaking, a host system may utilize a memory subsystem that includes one or more memory components. The host system can provide data that will be stored in the memory subsystem and can request data that will be retrieved from the memory subsystem.

[0015] A memory subsystem may include multiple memory components capable of storing data from a host system. Each memory component may contain a different type of media. Examples of media include, but are not limited to, cross-point arrays of non-volatile memory and flash-based memory such as single-level cell (SLC) memory, three-level cell (TLC) memory, and four-level cell (QLC) memory. The characteristics of different types of media may vary for each media type. One example of a characteristic associated with a memory component is data density. Data density corresponds to the amount of data (e.g., data bits) that can be stored per memory cell (e.g., NAND memory cell) of the memory component. Using an example of flash-based memory, a four-level cell (QLC) can store four data bits, while a single-level cell (SLC) can store one data bit. Therefore, a memory component containing QLC memory cells will have a higher data density than a memory component containing SLC memory cells. Although the examples used herein relate to QLC memory, in additional embodiments, the principles and concepts also apply to TLC memory or other multi-level cell memories.

[0016] In a QLC memory, each of the set of memory cells is programmed with four bits using 16 voltage levels (for 16 states) during multiple programming passes. In the first programming pass, each of the next page (LP), previous page (UP), and extra logical page (XP) is programmed into the set of memory cells to complete the programming of the first three bits, for example, eight states per bit. In the second programming pass, the first page (TP) is programmed to complete the programming of the fourth bit, and a total of eight extra states are present in the same physical memory cell.

[0017] However, situations such as power failures can cause the second programming pass to fail or not complete, even if the first programming pass is complete and readable. In this case, the first three bits (LP, UP, XP) have been written, but the fourth bit (TP) has not. A more complex problem is that the error correction code (ECC) check (e.g., low-density parity check (LDPC)) for the written data may still pass. This is because the data read from the supposedly missing TP is an arithmetic combination of the first three bits (LP, UP, XP) written to the same physical location in the memory cell during the first programming pass. Because the data is missing—for example, TP is empty—when a read request is filled into the location in the NVM memory, the second logical address in the read request will not match the logical address where data is stored at the physical address of the memory component. This address mismatch triggers the memory controller to detect and report a decoding error to the host, such as an uncorrectable data error. The memory controller's firmware cannot determine whether this decoding error is genuine. Therefore, the memory controller typically reports a decoding error and stops, causing the software program accessing the memory to suspend and creating a deadlock situation. There is no other solution besides performing deadlock recovery, which in some cases requires restarting the software program, leading to user confusion and decreased productivity.

[0018] This disclosure addresses the aforementioned and other shortcomings by providing additional error reporting granularity beyond simply reporting decoding errors. By providing detection and reporting of empty page errors in the event that the aforementioned TP page is empty, the memory controller can trigger a restart of the write operation. A restart of the write operation causes the host system to resend data for proper programming, for example, by erasing and writing data to the memory components. Therefore, reporting errors distinct from memory decoding errors provides a far better solution than recovering from deadlock situations and paused procedures.

[0019] In one embodiment, the memory component may, in response to completing a second programming pass in a multi-pass programming process, write multiple flag bits (e.g., from "1" to "0") of a flag byte stored in NVM memory. In response to a read request, the memory controller may detect that a second logical address within the read request does not match the logical address associated with the physical address of the set of memory cells. The memory controller may then perform a check to determine the number of first values ​​(e.g., one in the case of a write of one to zero) among the multiple flag bits. In response to the number of first values ​​not meeting a threshold criterion, the memory controller may report an uncorrectable data error to the host computing device because TP is not empty. The threshold criterion may be that the number of first values ​​is greater than or equal to approximately 50% of the number of the multiple flag bits. However, if the number of first values ​​meets this threshold criterion, then no flag bits are set after the second programming pass, and TP is empty. In this case, the memory controller may report a page fault.

[0020] In additional or alternative embodiments, specifically, when the above-described detection results in a page fault, the memory controller may sum the first data from the first pass of programming to produce combined data (e.g., LP+UP+XP). The memory controller may further calculate a second value by performing arithmetic operations on the combined data, for example, in one embodiment, producing (LP+UP+XP) modulo 2. The memory controller may then generate a difference by comparing the second value with a third value of the second data from the second pass of programming (e.g., TP). The memory controller may report a page fault to the host computing device in response to the difference meeting a threshold criterion, for example, the number of bits less than 5% to 15% of the second value. Otherwise, if the difference does not meet this threshold criterion, the memory controller may report an uncorrectable data error to the host computing device.

[0021] Figure 1A An example computing environment 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as memory components 112A to 112N. Memory components 112A to 112N may be volatile memory components, non-volatile memory components, or combinations thereof. The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A An example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 uses the memory subsystem 110 to, for example, write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes, for example, electrical, optical, magnetic, and other connections.

[0023] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, or such computing device including memory and processing. Host system 120 may include or be coupled to memory subsystem 110 such that host system 120 can read data from or write data to memory subsystem 110. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. As used herein, “coupled to” generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize the NVM High Speed ​​(NVMe) interface to access the memory components 112A to 112N. The physical host interface provides an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0024] Memory components 112A to 112N may comprise different types of non-volatile memory components and / or any combination of volatile memory components. Examples of non-volatile memory components include NAND flash memory. Each of memory components 112A to 112N may comprise one or more arrays of memory cells (e.g., NAND memory cells), such as single-level cell (SLC) or multi-level cell (MLC) arrays (e.g., three-level cell (TLC) or four-level cell (QLC) arrays). In some embodiments, a particular memory component may comprise both SLC and MLC portions of memory cells. Each memory cell may store one or more data bits (e.g., data blocks) for use by the host system 120. Although non-volatile memory components (e.g., NAND flash memory) have been described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase-change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without having previously been erased. Additionally, the memory cells of memory components 112A to 112N may be grouped into memory pages or data blocks, which refer to the cells of the memory component used to store data.

[0025] Memory system controller 115 (hereinafter referred to as the "controller") can communicate with memory components 112A to 112N to perform operations, such as reading, writing, or erasing data at memory components 112A to 112N, and other such operations. Controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. Controller 115 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. Controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of memory subsystem 110, including processing communication between memory subsystem 110 and host system 120. In some embodiments, local memory 119 may include memory registers storing memory indicators, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although the example memory subsystem 110 in FIG1 has been shown to include controller 115, in another embodiment of this disclosure, memory subsystem 110 may not include controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0026] Generally, controller 115 can receive commands or operations from host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to memory components 112A to 112N. Controller 115 can handle other operations such as wear leveling, garbage collection, error detection and correction coding (ECC), encryption, caching, and address translation between logical block addresses and physical block addresses associated with memory components 112A to 112N. Controller 115 may further include a host interface circuitry that communicates with host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing memory components 112A to 112N and translate responses associated with memory components 112A to 112N into information for host system 120.

[0027] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the controller 115 and decode the addresses to access memory components 112A to 112N.

[0028] The memory subsystem 110 includes an error determination component 113 for granular and precise error reporting that can be used for multi-pass programming of non-volatile (NVM) memory as disclosed herein. In some embodiments, the controller 115 includes at least a portion of the error determination component 113. For example, the controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the error determination component 113 is part of the host system 120, an application, or an operating system.

[0029] Error determination component 113 can receive or detect errors associated with memory components 112A to 112N of memory subsystem 110, said errors may be at the granularity of one or more data blocks (e.g., a set of memory cells). In response to verifying a specific threshold criterion when a logical address within a read request does not match a logical address where data is stored at a physical address in the memory component, error determination component 113 may report an error at a specific granularity to host system 120. For example, the error may be a page fault, such as a second pass of programming where the TP is empty, or an uncorrectable page fault, such as the presence of a genuine decoding error. Further details regarding the operation of error determination component 113 are described below.

[0030] As previously discussed, in a QLC memory, each of a set of memory cells is programmed using 16 voltage levels (for 16 states) during multiple programming passes, with four bits, such as... Figure 2A As shown in the diagram. In the first pass of programming, each of the next page (LP), previous page (UP), and extra logical page (XP) is programmed into the set of memory cells to complete the programming of the first three bits, for example, eight states per bit. In the second pass of programming, the first page (TP) is programmed to complete the programming of the fourth bit, and there are a total of eight extra states in the same physical memory cell. By programming the set of states at different voltage levels in two separate passes, adjacent states—which are brought closer together by shrinking NAND memory—are less likely to be interfered with or incorrectly programmed, for example, due to the coupling restraint effect between voltage states. Therefore, multi-pass programming of non-volatile memory reduces the number of write errors.

[0031] However, there are often situations that cause the second programming pass to fail or not complete, even if the first programming pass is complete and readable. The most common scenario that could lead to this is that the first programming pass is complete, but a power failure (or other write-related error) causes the second programming pass to fail. In this case, the first three bits (LP, UP, XP) have been written, but the fourth bit (TP) has not. A more complex issue is that the error correction code (ECC) check of the written data (e.g., low-density parity check (LDPC)) may still pass. This is because the data read from the supposedly missing TP is an arithmetic combination of the first three bits (LP, UP, XP) written to the same physical location in the memory cell during the first programming pass. In one embodiment, the arithmetic combination is (LP+UP+XP) modulo 2 ("2"), but other combinations are conceivable. The ECC check in a conventional LDPC engine for (LP+UP+XP) passes just as well as the ECC check for (LP+UP+XP) modulo 2. In this way, although the ECC check of the write operation passes, the data is incomplete and will produce an error when the controller attempts to read the data, as will be explained in detail.

[0032] More precisely, Figure 2B This is a graph illustrating how a second pass programming (e.g., TP data) can be read when the first page contains no data, according to some embodiments of this disclosure. In the case of deep error handling, the firmware of the memory controller may lower the read level by approximately 300 millivolts. As shown, data reads during a TP read where the TP data is empty include reads at RL1, RL3, RL5, RL7, RL9, RL11, RL13, and RL15, where “RL” denotes “read level”. The memory component can thus automatically allocate TP data to cells between reads based on the 16-state Gray code shown in Table 1, which is an arithmetic combination of LP, UP, and XP data. For example, in one embodiment, TP´=(LP+UP+XP) modulo 2, where LP+UP+XP can be determined as a logical OR operation.

[0033] 8-bit XP 8 Status UP Position 8-state LP bits TP' (read as:) 1 1 1 1 0 1 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 0 0 0 0 1 0 1 1 1 0 0

[0034] Table 1

[0035] In various embodiments, because the data is absent—for example, the TP is empty—and therefore the data and its associated logical address are absent, even if the data actually read can be verified by ECC. Therefore, when a read request is filled into the location in the NVM memory, the second logical address in the read request will not match the logical address associated with the data stored at the physical address of the memory component, for example, because the logical address of the TP does not exist. This address mismatch triggers the memory controller (e.g., the processing device) to detect (and report to the host) a decoding error, such as an uncorrectable data error. The firmware of the memory controller cannot determine whether this decoding error is genuine. Therefore, the memory controller typically reports a decoding error and stops, causing the software program accessing the memory to suspend. A deadlock situation can similarly cause software hangup; for example, in a deadlock situation, the memory controller waits for another process to complete its hold on the memory location while that process waits for the memory controller to finish its access. There is no solution other than performing deadlock recovery, which in some cases requires restarting the software program, leading to user confusion and decreased productivity. However, since an empty TP is not a real decoding error, reporting it in this way is incorrect and could lead to a worst-case scenario where the software program has been suspended.

[0036] Figure 1B According to some embodiments of this disclosure Figure 1A A block diagram of the memory subsystem 110. In an embodiment, the memory subsystem 110 includes a controller 115 coupled to a memory component 112A, which is depicted as an example of any of memory components 112A to 112N. Memory component 112A may include a local media controller 130, a flag byte 140 (e.g., stored within a memory cell), and a ROM block 150. In one embodiment, the flag byte 140 is a TP_PROGRAMMED_FLAG byte in the LP data of a group of memory cells. The local media controller 130 may couple the controller 115, the ROM block 150, and the flag byte 140 together, as shown. In one embodiment, the local media controller 130 performs operations received from the controller 115 on one or more memory cells of the memory component 112A.

[0037] In one embodiment, the local media controller 130 is coupled to the controller 115 via an Open NAND Flash Interface (ONFI) 125, which serves as a communication interface between the controller 115 and the memory component 112A when the controller 115 is an SSD controller and the memory component 112A is a NAND component of the memory. Furthermore, in some embodiments, the local media controller 130 is a microcontroller that includes a hardware state machine that translates commands (sent by the controller 115) from the ONFI interface to access memory cells. For example, the local media controller 130 may include control logic embodied in a state machine, which is typically immutable and follows commands or operations indicated by the controller 115. In this disclosure, in addition to memory cells, the state machine of the local media controller 130 is further used to interface with one or both of the ROM block 150 and the flag byte 140.

[0038] In various embodiments, the flag byte 140 contains a plurality of flag bits 142 (e.g., 48 bits), some of which are written upon successful completion of the corresponding set of memory cells. Therefore, a flag byte 140 may exist for each block of memory in memory component 112A, and these are not shown for ease of explanation. In response to a multi-pass programming command, the controller 115 may perform multiple writes to the set of memory cells. Assuming a second pass of programming is complete, the local media controller 130 may record such completion by writing several flag bits 142 in the flag byte 140. In one embodiment, all flag bits 142 begin with a value of one (“1”), and after the second pass of programming of the TP is completed, the local media controller 130 may write a value of zero (“0”) to half or more of the flag bits 142. In another embodiment, the flag bits 142 begin with a value of zero (“0”), and in response to the completion of the second pass of programming, the local media controller 130 may write a value of one (“1”) to half or more of the flag bits 142. In this way, the threshold for a blank page can be the number of first values ​​(whether one in the first embodiment or zero in the second embodiment) of flag bit 142 that are greater than a specific threshold, such as 50% of flag bits 142 (e.g., 24 bits). In other words, more than 50% of the remaining flag bits being the first value indicates that actual data cannot be written during the second programming pass, and therefore should be reported as a blank page fault.

[0039] For further reference Figure 1BROM block 150 may be part of a memory cell of memory component 112A, and in one embodiment is reserved solely as ROM for system use. ROM block 150 may contain a fixed data structure of configuration parameters for NAND device operations. In an embodiment, ROM block 150 may include lookup table 152. When a write command is executed and data is written to the block of memory cells, local media controller 130 may update lookup table 152 to create a mapping between the logical address in the write command and the physical address (e.g., NAND location) of the data being written in memory component 112A. Therefore, lookup table 152 may also be referred to as a logical-physical address mapping table.

[0040] In an embodiment, when a read request containing a second logical address is subsequently received, the local media controller 130 may access lookup table 152 and determine the physical address in memory component 112A. Assume the second logical address matches the logical address of a previous write command. The local media controller 130 may then retrieve the previously written data and logical address from the location in memory component 112A corresponding to the physical address. If this logical address (retrieved from the NAND location) does not match the second logical address in the read request, then the controller 115 detects an error and reports the error to the host system 120. The error is typically a decoding error, such as an uncorrectable data error. However, as discussed, in the case where the error is actually caused by a null page fault due to incomplete second-pass programming, the controller 115 may report a null page fault to the host system 120, as referenced... Figure 3-4 This will be discussed in more detail.

[0041] Figure 3 This is a flowchart of an example method 300 for providing granular error reporting for multiple-pass programming of non-volatile memory according to some embodiments of the present disclosure. Method 300 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1A-1B The process is executed by controller 115 (e.g., error determination component 113) and / or local media controller 130. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed simultaneously. Additionally, in various embodiments, one or more processes may be omitted. Therefore, not all processes are necessary in every embodiment. Other process flows are possible.

[0042] At operation 310, in response to completing a second pass programming of a set of memory cells (e.g., TP), the memory component writes multiple flag bits into the set of memory cells. As discussed above, these multiple flag bits may begin with a value of one (“1”) and become a value of zero (“0”) upon writing (or vice versa). If the second pass programming is complete, it may write zero values ​​to 50% or more of the multiple bits, for example, 60% or more, or some other percentage, depending on the number of bits written after the second pass programming is completed. At operation 320, upon receiving a read request, the processing logic may determine that the second logical address of the read request does not match the logical address associated with the data stored at the physical address of the set of memory cells. This determination typically results in a decoding error, e.g., an uncorrectable data error. However, in practice, method 300 may perform additional diagnostics on the error to determine whether the error is caused by an empty TP.

[0043] For further reference Figure 3 At operation 330, the processing logic may determine the number of first values ​​among a plurality of flag bits, for example, the number of values ​​one (“1”) in the first embodiment discussed earlier. For example, if the number of values ​​one exceeds 50% of the plurality of flag bits, then the second pass programming is incomplete, and a page fault is an appropriate error to report. At operation 340, the processing logic may determine whether the number of first values ​​meets a threshold criterion, for example, greater than or equal to approximately 50% of the number of the plurality of flag bits. At operation 350, in response to the number of first values ​​not meeting the threshold criterion (e.g., the number of flag bits is less than 50% of the number of “1”), the processing logic may report an uncorrectable data error to the computing device, for example, due to the fact that the number of flag bits indicates that the second pass programming is complete. At operation 360, in response to the number of first values ​​meeting the threshold criterion (e.g., the number of flag bits is greater than or equal to 50% of the number of “1”), the processing logic may report a page fault to the host computing device, for example, the page programmed during the second pass programming is empty.

[0044] Figure 4 This is a flowchart of an example method 400 for providing granular error reporting for multi-pass programming of non-volatile memory according to other embodiments of this disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1A-1BThe process is executed by controller 115 (e.g., error determination component 113) and / or local media controller 130. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed simultaneously. Additionally, in various embodiments, one or more processes may be omitted. Therefore, not all processes are necessary in every embodiment. Other process flows are possible.

[0045] At operation 410, in response to a write request with a logical address, the processing logic may perform multiple passes of programming a set of memory cells. At operation 420, upon receiving a read request, the processing logic may determine that a second logical address within the read request does not match the logical address associated with data stored at the physical address of the set of memory cells. This determination typically results in a decoding error, such as an uncorrectable data error. However, in practice, method 400 may perform additional diagnostics on the error to determine whether the error is caused by an empty TP. Method 400 may be for Figure 3 Method 300 to additional or alternative embodiments provides more granular error reporting in response to logical addressing mismatches.

[0046] At operation 430, the processing logic may sum the first data from the first pass of programming to produce combined data, for example, where the first data includes a sub-part of the data from each of the next page (LP), previous page (UP), and extra page (XP). For example, the summation of the first data may be performed via a logical OR operation. At operation 440, the processing logic may further produce (or compute) a first value by performing an arithmetic operation on the combined data. In one embodiment, the arithmetic operation is modulo N, so the first value may be (LP+UP+XP) modulo N (where N is 2, 4, 6, etc.), or the result of performing some other arithmetic operation on the combination of the first data. At operation 450, the processing logic may produce a difference by comparing the first value with a second value of the second data from the second pass of programming. For example, the second value may be data read from an address corresponding to the logical address of the second pass of programming. As previously discussed, when TP is empty, the second data read may be the same as or similar to the arithmetic combination of the first data, for example, the combination of LP+UP+XP. In one embodiment, for example, the determination of the difference may be performed using an XOR operation.

[0047] Continue to refer to Figure 4At operation 460, the processing logic can determine whether the difference meets a threshold criterion, for example, 5% to 15% of the number of bits less than a first value. In one embodiment, for example, this threshold criterion can be between 500 and 700 bits. This threshold criterion can be selected because the second data should be approximately the same as the arithmetic operation performed on the combined first data when the home page is empty. As discussed above, in one embodiment, the content read as the second data when TP is empty can thus be approximately the same as (LP+UP+XP) modulo 2. At operation 470, in response to the difference not meeting the threshold criterion, the processing logic can report an uncorrectable data error to the host computing device, for example, a real decoding error has occurred because arithmetic has verified that the home page is not empty. At operation 480, in response to the difference meeting the threshold criterion, the processing logic can report a page null error, for example, the home page programmed during the second programming pass is empty.

[0048] Method 400 can provide an alternative to Method 300, or can provide as an alternative to Method 300. Figure 3 Method 300's confirmation check. If used as a confirmation check, then method 400 can be executed after method 300 generates a page fault, for example, to confirm that it is a page fault before reporting the error to host system 120. This double-checking method can be advantageous because method 300 can be executed quickly by performing a single read of multiple flag bits 142 to determine whether the second pass of programming is complete. However, because flag bits 142 can also be subject to write errors, the confirmation check implementation of method 400 can ensure that the home page is empty before reporting the error as a page fault. Compared to method 300, method 400's additional data reads and arithmetic steps are more resource-intensive, but if any additional waiting time can ensure that the correct error is reported and the correct action is taken in response to the error, then the effort is worthwhile.

[0049] Figure 5 An example machine of computer system 500 is shown, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A-1B The memory subsystem 110), or may be used to perform operations of the controller 115 (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1A(Operation of error determination component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a qualified server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0050] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0051] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0052] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 communicating via network 520.

[0053] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, main memory 504, and processing device 502, which also constitute machine-readable storage media. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1A-1B The memory subsystem 110.

[0054] In one embodiment, instruction 526 includes implementing a component corresponding to the error determination component (e.g., Figure 1A The error determination component 113) or the firmware of the local media controller 130 contains functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0055] Some of the previously described sections have presented algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most efficient way for those skilled in the art of data processing to communicate their work to others skilled in the art. Here and generally, an algorithm is conceived as a self-consistent sequence of operations that produces a desired result. These operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been found convenient, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0056] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0057] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0058] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. Structures for various such systems will be presented in the following description. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0059] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0060] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of this disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: A memory component, the memory component being configured to write multiple flag bits into a set of memory cells programmed by the multiple programming command after completing a second programming pass in response to a multiple programming command; as well as A processing device operatively coupled to the memory assembly, the processing device being configured to perform the following operations: Multiple passes of programming are performed on the set of memory cells in association with logical addresses; Upon receiving a read request, it is determined that the second logical address within the read request does not match the logical address associated with the data stored at the physical address of the set of memory cells; Determine the number of first values ​​within the plurality of flag bits; and In response to the first value not meeting the threshold criterion, an uncorrectable data error is reported to the host computing device due to at least some data stored on the home page of the set of memory units.

2. The system of claim 1, wherein the threshold criterion comprises 50% or more of the number of the plurality of flag bits.

3. The system according to claim 1, wherein, In response to the number of the first value satisfying the threshold criterion, the processing device is further configured to report a blank page error indicating that the home page does not have data to the host computing device.

4. The system according to claim 1, wherein, In response to the number of the first value satisfying the threshold criterion, the processing device is further configured to perform the following operations: Combine the first data from the first pass of programming to produce combined data; Generate a second value that includes arithmetic operations performed on the combined data; The difference is generated by comparing the second value with the third value of the second data in the second pass of programming; as well as In response to the difference meeting the second threshold criterion, a page fault is reported to the host computing device.

5. The system according to claim 4, wherein the arithmetic operation includes modulo 2.

6. The system of claim 4, wherein in response to the difference being greater than or equal to the second threshold criterion, the processing device reports the uncorrectable data error to the host computing device.

7. The system of claim 4, wherein the first data includes a sub-portion of data for each of the next page, previous page, and additional pages, and the second data includes data for the first page programmed during the second pass of programming.

8. The system of claim 4, wherein the second threshold criterion comprises 5% to 15% of the number of bits less than the second value.

9. A method comprising: In response to a write request with a logical address, perform multiple passes of programming on a set of memory cells of the memory component; In response to completing the second pass of the multi-pass programming, multiple flag bits are written into the set of memory cells; In response to a read request, it is determined that the second logical address of the read request does not match the logical address associated with the physical address of the set of memory cells; Determine the number of first values ​​within the plurality of flag bits; as well as In response to the first value's number satisfying a threshold criterion, a blank page error indicating that the home page has no data is reported to the host computing device, the home page having been programmed during the second programming pass.

10. The method of claim 9, wherein the threshold criterion comprises 50% or greater than or equal to the number of the plurality of flag bits, the method further comprising reporting an uncorrectable data error to the host computing device in response to the number of the first value not meeting the threshold criterion.

11. The method of claim 9, further comprising, before reporting the empty page error, confirming that the homepage is empty by: Combine the first data from the first pass of programming to produce combined data; A second value is generated by performing arithmetic operations on the combined data; A difference is generated by comparing the second value with a third value of the second data programmed in the homepage; and It is determined that the difference does not meet the second threshold criterion.

12. The method of claim 11, wherein performing the arithmetic operation includes calculating the modulo 2 of the combined data.

13. The method of claim 11, further comprising reporting an uncorrectable data error to the host computing device in response to determining that the difference meets the second threshold criterion.

14. The method of claim 11, wherein the second threshold criterion comprises 5% to 15% of the number of bits less than the second value.

15. The method of claim 11, wherein the first data includes a sub-portion of data for each of the next page, the previous page, and the additional page.

16. A system comprising: Memory components; as well as A processing device operatively coupled to the memory assembly, the processing device being configured to perform the following operations: In response to a write request including a logical address, multiple passes of programming are performed on a set of memory cells of the memory component; Upon receiving a read request, it is determined that the second logical address within the read request does not match the logical address associated with the data stored at the physical address of the set of memory cells; Sum the first data from the first pass of programming to generate combined data; A first value is generated by performing arithmetic operations on the combined data; The difference is generated by comparing the first value with the second value of the second data in the second pass of programming; as well as In response to the difference meeting the threshold criterion, a page fault is reported to the host computing device.

17. The system of claim 16, wherein the arithmetic operation includes modulo 2.

18. The system of claim 16, wherein in response to the difference not meeting the threshold criterion, the processing device reports an uncorrectable data error to the host computing device.

19. The system of claim 16, wherein the first data includes a sub-portion of data for each of the next page, previous page, and additional pages, and the second data includes data for the first page programmed during the second pass of programming.

20. The system of claim 16, wherein the threshold criterion comprises 5% to 15% of the number of bits less than the first value.

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