Method for providing device status in response to a read command for a write-only mode register bit, and memory device and system employing the same

Abstract

Memory devices, memory systems, and methods of operation thereof are disclosed in which a memory device reads data from one or more cells of a memory array of the memory device different from one or more write-only mode registers of the memory device in response to receiving a mode register read (MRR) command for the write-only mode registers. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. A status information mode can be optionally enabled or disabled. The memory device can include a DDR5 DRAM memory device.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 889,954, filed August 21, 2019, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure generally relates to methods for providing a state read from a write-only mode register bit and memory devices and systems employing the same. BACKGROUND

[0004] Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of memory cells. There are a variety of types of memory devices including magnetic hard disks, random access memory (RAM), read only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), and the like. Memory devices can be volatile or non-volatile. Improving memory devices can generally include increasing memory cell density, improving read / write speed or otherwise reducing operational latency, improving reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among others. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a simplified block diagram schematically illustrating a memory device according to an embodiment of the present technology.

[0006] Figure 2 is a simplified block diagram schematically illustrating a memory system according to an embodiment of the present technology.

[0007] Figure 3 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present technology.

[0008] Figure 4 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present technology. DETAILED DESCRIPTION

[0009] In addition to large memory arrays dedicated to storage of system and / or user data, memory devices often include separate storage areas, such as mode registers to store device state information (e.g., device settings, environmental conditions, usage statistics, metadata, feature support, feature implementations, device status, temperature, etc.). While many of these mode registers are read-only or read / write capable, design constraints (as set forth in more detail below) sometimes limit the functionality of some of the mode register bits such that read operations thereon are unreliable, disabled, or otherwise impossible. One approach to handling write-only bits is to configure the bits such that a mode register write (MRW) command to the bits results in a defined write operation, but a mode register read (MRR) command to the bits results in no data being returned (e.g., a zero is returned for the contents of the bits regardless of the actual data stored therein). The lack of response (e.g., a zero is returned) to MRR commands to these write-only bits results in wasted bus bandwidth, which in many applications results in suboptimal memory device performance.

[0010] Accordingly, several embodiments of the present technology are directed to memory devices, systems including memory devices, and methods of operating memory devices, in which the memory devices return device state information (e.g., device settings, environmental conditions, usage statistics, metadata, feature support, feature implementations, device status, temperature, etc.) not stored in target write-only mode register bits in response to mode register read commands to the write-only mode register bits. This arrangement enjoys several benefits, such as improved bus utilization and reduced time to obtain data indicative of memory device state (e.g., device state information).

[0011] Figure 1 is a block diagram schematically illustrating a memory device 100 according to embodiments of the present technology. The memory device 100 can include an array of memory cells, such as a memory array 150. The memory array 150 can include a plurality of banks (e.g., banks 0-15 in the example of Figure 1 The selection of word lines WL can be performed by a row decoder 140, and the selection of bit lines BL can be performed by a column decoder 145. A sense amplifier (SAMP) can be provided for a corresponding bit line BL and connected to at least one respective local I / O line pair (LIOT / B), which can then be coupled to at least one respective main I / O line pair (MIOT / B) through a transmission gate (TG), which can act as a switch.

[0012] The memory device 100 can employ a plurality of external terminals including command and address terminals coupled to a command bus and an address bus to receive command signals CMD and address signals ADDR, respectively. The memory device can additionally include a chip select terminal for receiving a chip select signal CS, clock terminals for receiving clock signals CK and CKF, data clock terminals for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, power terminals VDD, VSS, VDDQ, and VSSQ, and an on-die termination terminal ODT.

[0013] Address signals and bank address signals can be supplied externally to the command terminals and the address terminals. The address signals and bank address signals supplied to the address terminals can be transmitted to the address decoder 110 by the command / address input circuit 105. The address decoder 110 can receive the address signals and supply a decoded row address signal (XADD) to the row decoder 140, a decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive the bank address signals (BADD) and supply the bank address signals to both the row decoder 140 and the column decoder 145.

[0014] Command signals CMD, address signals ADDR, and chip select signals CS can be supplied from a memory controller to the command terminals and the address terminals. The command signals can represent various memory commands from the memory controller, including access commands, which can include read commands and write commands. The chip select signal CS can be used to select the memory device 100 to respond to the commands and addresses provided to the command and address terminals. When a valid CS signal is provided to the memory device 100, the commands and addresses can be decoded and memory operations can be performed. The command signals CMD can be provided as internal command signals ICMD to the command decoder 115 by the command / address input circuit 105. The command decoder 115 can include circuitry for decoding the internal command signals ICMD to generate various internal signals and commands for performing memory operations, for example, row command signals for selecting word lines and column command signals for selecting bit lines. The internal command signals can also include output and input activation commands, such as a clocking command CMDCK.

[0015] When a read command is issued and the row and column addresses are supplied in a timely manner, read data can be read from the memory cells in memory array 150 identified by these row and column addresses. The read command can be received by command decoder 115, which can provide internal commands to input / output circuitry 160, enabling read data to be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier 155 and input / output circuitry 160 according to the RDQS clock signal. The read data can be programmed in memory device 100, for example, in a mode register (…). Figure 1 The read data is provided at the time defined by the read delay information RL (not shown in the diagram). The read delay information RL can be defined in terms of the clock cycles of the CK clock signal. For example, the read delay information RL can be the number of clock cycles of the CK signal after the read command is received by the memory device 100 when the associated read data is provided.

[0016] When a write command is issued and the row and column addresses are supplied in a timely manner along with the command, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by a command decoder 115, which can provide an internal command to the input / output circuit 160 so that the write data can be received by the data receiver in the input / output circuit 160 and supplied to the memory array 150 through the input / output circuit 160 and the read / write amplifier 155. Write data can be written to the memory cells specified by the row and column addresses. Write data can be supplied to the data terminals at a time defined by the write delay WL information. The write delay WL information is programmable in the memory device 100, for example, programmed in the mode register (…). Figure 1 (Not shown in the image). The write delay information WL can be defined in terms of the clock cycles of the CK clock signal. For example, the write delay information WL can be the number of clock cycles of the CK signal after the write command is received by the memory device 100 when the associated write data is received.

[0017] Power supply potentials VDD and VSS can be supplied to the power supply terminals. These power supply potentials VDD and VSS can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the line decoder 140, the internal potentials VOD and VARY can be used in the sense amplifier included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0018] A power supply potential VDDQ can also be supplied to the power supply terminal. The power supply potential VDDQ can be supplied to the input / output circuit 160 along with the power supply potential VSS. In an embodiment of the technology, the power supply potential VDDQ can be the same potential as the power supply potential VDD. In another embodiment of the technology, the power supply potential VDDQ can be a different potential than the power supply potential VDD. However, a dedicated power supply potential VDDQ can be used for the input / output circuit 160 so that power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0019] An on-die termination signal ODT can be supplied to the on-die termination terminal. The on-die termination signal ODT can be supplied to the input / output circuit 160 to instruct the memory device 100 to enter an on-die termination mode (e.g., to provide one of a predetermined number of impedance levels at one or more of the other terminals of the memory device 100).

[0020] External clock signals and complementary external clock signals can be supplied to the clock terminal and the data clock terminal. The external clock signals CK, CKF, WCK, WCKF can be supplied to the clock input circuit 120. The CK and CKF signals can be complementary, and the WCK and WCKF signals can also be complementary. The complementary clock signals can have opposite clock levels and transitions between the opposite clock levels at the same time. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Further, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0021] Input buffers included in the clock input circuit 120 can receive the external clock signals. For example, the input buffers can receive the CK and CKF signals and the WCK and WCKF signals when enabled by the CKE signal from the command decoder 115. The clock input circuit 120 can receive the external clock signals to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to the internal clock circuit 130. The internal clock circuit 130 can provide various phase and frequency controlled internal clock signals based on the received internal clock signal ICLK and a clock enable signal CKE from the command / address input circuit 105. For example, the internal clock circuit 130 can include a clock path that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115, the command / address input circuit 105, and the data input / output circuit 160. Figure 1The internal clock circuit 130 can further provide an input / output (10) clock signal. The 10 clock signal can be supplied to the input / output circuit 160 and can be used as a timing signal for determining output timing of read data and input timing of write data. The 10 clock signal can be provided at multiple clock frequencies so that data can be output from and input to the memory device 100 at different data rates. Higher clock frequencies can be desirable when high memory speeds are needed. Lower clock frequencies can be desirable when lower power consumption is needed. The internal clock signal ICLK can also be supplied to the timing generator 135, and thus various internal clock signals can be generated.

[0022] The memory device 100 can further include one or more registers 118 for storing various data (e.g., device status information). The mode registers 118 can include read-only bits, read-write bits, write-only bits, or any combination thereof. In some embodiments, the mode registers 118 can be arranged in byte-size set addressable portions, with each individually addressable mode register containing 8 bits. Read-write and write-only mode register bits can be written in response to a mode register write (MRW) command, with the data to be written being provided via the CA interface, and read-write and read-only mode register bits can be read in response to a mode register read (MRR) command, with the stored data being output through the DQ data terminals. The mode registers 118 can also be read and written internally by various components of the memory device 100 (e.g., to populate read-only mode register bits with device status information, to determine the status of write-only mode register bits, etc.) without the need to exchange data with the terminals of the memory device.

[0023] Some mode registers can be centrally located (e.g., in a region of the memory device dedicated to storing mode registers), with control circuitry spread across the device to connect the central mode registers to circuits that utilize the information stored therein. However, other mode registers can be physically located near the circuitry for which they store settings. Because some of these mode registers are thus located in a region of the memory device that is crowded with additional circuitry, and because the circuitry that would be used to provide read access to those mode registers in response to MRR commands can be extensive, these mode registers can not have the circuitry to read the mode registers (or particular bits within them) in response to MRR commands, and thus can be considered write-only (or include write-only bits). While the information stored in these write-only mode registers (or write-only mode register bits) can still be accessible to the memory device itself, which can access the information therein during operation of the memory device (e.g., using the state of the mode register bits as input to a state machine implemented by the circuitry), the inability to output the information therein in response to MRR commands means that the information is generally not available to users of the memory device. One method of responding to MRR commands that read out information from write-only registers or bits involves returning a predetermined bit (e.g., typically 0). However, this method has drawbacks including poor bus utilization and thus suboptimal memory device performance.

[0024] According to one embodiment of the disclosure, a memory device such as memory device 100 can be configured to respond to MRR commands for write-only bits of a mode register (e.g., mode register 118) by returning device state information that is not stored in the write-only bits targeted as the MRR command. The device state information configured to be returned can include any of a number of different types of information, including, for example, feature implementation, feature support, device capability, device status, device configuration, environmental information (e.g., temperature), and so forth. By responding to MRR commands for write-only mode register bits with device state information, bus utilization can be improved and additional device state information about the memory device can be made more readily available.

[0025] For example, according to one embodiment of the disclosure, a byte-sized mode register can be configured to store information about refresh functions of a DRAM memory device. This exemplary mode register is illustrated in Table 1 below.

[0026] Table 1

[0027]

[0028] As can be seen with reference to Table 1, the MR bit with operand OP[3] stores information received from the host indicating whether an incoming refresh command from the host will contain a specified refresh rate. While this bit is a write-only bit (e.g., MRR commands are not readable), the memory device can be configured to return device status information regarding whether the memory device supports a refresh optimization feature (e.g., where the memory device can utilize a specified refresh rate received from the host). In use, the OP[3] bit will store a 0 or 1 to indicate whether the host is providing (i.e., has a 1) or not providing (i.e., has a 0) the refresh internal rate indication feature. However, when a MRR operation targets this OP[3] bit, rather than returning the stored value in the register, the memory device will return device status information indicating whether the memory device is implementing (i.e., has a 1) or not implementing (i.e., has a 0) support for the refresh optimization feature.

[0029] In other embodiments, other device status information can be provided in response to a MRR command targeting one or more write-only mode register bits, including device temperature, device status, device configuration, and the like. In this regard, according to one aspect of the disclosure, the device status information returned in response to a MRR command targeting a particular write-only mode register bit can be specified in another mode register, such that the information can be user-configurable.

[0030] According to another aspect of the disclosure, the foregoing method of providing device status information in response to a MRR command targeting one or more write-only mode register bits can be enabled or disabled by an end user of the memory device and / or memory module. For example, in embodiments where the feature is configurable, the feature can be enabled or disabled by changing the corresponding mode register value. Other methods of enabling and disabling the foregoing features can also be used, such as sending a command to the memory device, changing the applied voltage input to the memory device, and the like.

[0031] Figure 2 is a simplified block diagram schematically illustrating a memory system 200 according to an embodiment of the technology. The memory system 200 includes a host device 210 operably coupled to a memory module 220 (e.g., a dual in-line memory module (DIMM)). The memory module 220 can optionally include a controller 230 operably connected to a plurality of memory devices 250 by a bus 240. In addition to or instead of the controller 230, the memory module 220 can optionally include a register clock driver (RCD).

[0032] Figure 3This is a flowchart illustrating a method of operating a memory system (e.g., a memory module comprising one or more memory devices) according to embodiments of the present invention. The method includes receiving a command at the memory device to read data from a write-only mode register (block 310). According to one aspect of this disclosure, the receiving feature of block 310 may be implemented via command / address input circuitry 105, as described above. Figure 1 The method is described in more detail below. It further includes reading and / or outputting device state information about the memory device in response to a command, wherein the device state information is not stored in a write-only mode register (block 320). According to one aspect of this disclosure, the output characteristics of block 320 can be implemented using input / output circuitry 160, as described above. Figure 1 A more detailed explanation follows.

[0033] Figure 4 This is a flowchart illustrating a method of operating a memory system (e.g., a memory module comprising one or more memory devices) according to an embodiment of the present invention. The method includes receiving a first command (block 410) at a memory device to store data in a write-only mode register. According to one aspect of this disclosure, the receiving feature of block 410 may be implemented via command / address input circuitry 105, as described above. Figure 1 The method is described in more detail below. The method further includes storing data in a write-only mode register (box 420) in response to a first command. According to one aspect of this disclosure, the storage features of box 420 can be implemented using mode register 118, as described above. Figure 1 The method is described in more detail below. The method further includes receiving a second command (block 430) at the memory device to read data from a write-only mode register. According to one aspect of this disclosure, the receiving feature of block 430 may be implemented via command / address input circuitry 105, as described above. Figure 1 The method is described in more detail below. It further includes reading and / or outputting device state information about the memory device in response to a second command, wherein the device state information is not stored in a write-only mode register (block 440). According to one aspect of this disclosure, the output characteristics of block 440 can be implemented using input / output circuitry 160, as described above. Figure 1 A more detailed explanation follows.

[0034] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the methods may be combined.

[0035] Although memory modules and devices have been shown and described in the foregoing example embodiments with respect to DRAM devices, embodiments of the present technology can have application to other memory technologies, including SRAM, SDRAM, NAND and / or NOR flash, phase change memory (PCM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), etc. Moreover, while memory modules have been illustrated and described as dual in-line memory modules (DIMMs) having nine memory devices, embodiments of the present disclosure can include more or fewer memory devices, and / or relate to other memory modules or packaging formats (e.g., single in-line memory modules (SIMMs), small outline DIMMs (SODIMMs), single in-line pin packages (SIPPs), custom memory packages, etc.).

[0036] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signal can represent a bus of signals, where the bus can have a variety of bit widths.

[0037] Devices discussed herein that include memory devices can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during initial formation or growth of the substrate.

[0038] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0039] As used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of’ or “one or more of’ indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a referral to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both condition A and condition B without deviating from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be interpreted as “based, at least in part, on.”

[0040] From the foregoing, it will be appreciated that specific embodiments of the application have been described herein for purposes of illustration, but that various modifications can be made without deviating from the scope of the present application. In no way is the application limited as described above unless as may be expressly claimed below. Conversely, other embodiments of the application can have been made without departing from the scope of the application. Accordingly, you are to read this disclosure containing a memory system and a device to avoid obscuring other aspects of the technology. In general, it will be understood that various other devices, systems and methods notwithstanding, which are or can be employed by those skilled in the art, can be utilized in accordance with the present technology.

Claims

1. A method for operating a memory device, comprising: receiving, at the memory device, a command to read a write-only bit from a mode register; and in response to the command, reading data indicative of a status of the memory device, the status indicating whether the memory device supports a feature, wherein the data indicative of the status is read instead of the write-only bit.

2. The method of claim 1, further comprising determining that a status information mode of the memory device is enabled, and wherein the data is read based at least in part on the determination.

3. The method of claim 2, wherein determining that the status information mode of the memory device is enabled includes reading a setting stored in another mode register of the memory device.

4. The method of claim 1, wherein the data indicative of the status of the memory device comprises a device setting, an environmental condition, usage statistics, metadata, feature support, feature implementation, device status, temperature, or a combination thereof.

5. The method of claim 1, wherein the command is a mode register read (MRR) command.

6. A method for operating a host device, comprising: sending a command to read data from a write-only bit of a mode register of a memory device; and in response to the command, receiving data indicative of a status of the memory device instead of the write-only bit of the mode register, the status indicating whether the memory device supports a feature.

7. The method of claim 6, further comprising enabling a status information mode of the memory device, and wherein the data is received based at least in part on the enabling.

8. The method of claim 7, wherein enabling the status information mode of the memory device includes writing a setting to another mode register of the memory device.

9. The method of claim 6, wherein the data indicative of the status of the memory device comprises a device setting, an environmental condition, usage statistics, metadata, feature support, feature implementation, device status, temperature, or a combination thereof.

10. The method of claim 6, wherein the command is a mode register read (MRR) command.

11. The method of claim 6, wherein the memory device is a dynamic random access memory (DRAM) device.

12. A memory device, comprising: a memory array; a mode register including at least one write-only mode register bit; and circuitry configured to read, in response to a command to read data from the at least one write-only mode register bit, data indicative of a status of the memory device, the status indicating whether the memory device supports a feature, wherein the circuitry is configured to read the data indicative of the status instead of the at least one write-only mode register bit.

13. The memory device of claim 12, wherein the circuitry is further configured to determine that a status information mode of the memory device is enabled, and wherein the data is read based at least in part on the determination.

14. The memory device of claim 13, wherein the circuitry is configured to determine that a status information mode of the memory device is enabled by reading a setting stored in another mode register of the memory device.

15. The memory device of claim 12, wherein the data indicative of the status of the memory device comprises device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, or a combination thereof.

16. The memory device of claim 12, wherein the command is a mode register read (MRR) command.

17. A memory system, comprising: a host device; and a memory device operably coupled to the host device, the memory device including: a memory array, a write-only mode register bit, and circuitry configured to read data indicative of a status of the memory device in response to a command to read data from the write-only mode register bit, the status indicating whether the memory device supports a feature, wherein the circuitry is configured to read the data indicative of the status instead of the write-only mode register bit.

18. The memory system of claim 17, wherein the circuitry is further configured to determine that a status information mode of the memory device is enabled, and wherein the circuitry is configured to read the data based at least in part on the determination.

19. The memory system of claim 18, wherein the circuitry is configured to determine that the status information mode of the memory device is enabled by reading a setting stored in another mode register of the memory device.

20. The memory system of claim 17, wherein the data indicative of the status of the memory device comprises device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, or a combination thereof.

21. The memory system of claim 17, wherein the command is a mode register read (MRR) command.

22. A method for operating a memory device, comprising: receiving, at the memory device, a first command to store write-only data in a mode register; in response to the first command, storing the write-only data in the mode register; receiving, at the memory device, a second command to read from the mode register; and in response to the second command, outputting data indicative of a status of the memory device, the status indicating whether the memory device supports a feature, wherein the data is output instead of the write-only data stored in the mode register.

23. The method of claim 22, wherein the write-only data indicates whether a refresh command from a host to the memory device will include a specified refresh rate, and wherein the data indicative of the status of the memory device indicates whether the memory device is capable of using the specified refresh rate received from the host.

24. The method of claim 22, wherein the data indicative of the status comprises a first bit value or a second bit value, the first bit value indicating that the feature is not implemented by the memory device and the second bit value indicating that the feature is implemented by the memory device.

25. The method of claim 22, wherein the write-only data comprises a first bit value or a second bit value, the first bit value indicating that the feature is disabled and the second bit value indicating that the feature is enabled.

26. A method for operating a host device, comprising: sending a first command to write write-only data to a mode register of a memory device; sending a second command to read from the mode register; and in response to the second command, receiving data indicative of a status of the memory device instead of the write-only data, the status indicating whether a feature is supported by the memory device.

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