Instruction synchronization device, chip and computer equipment, and data processing method

Abstract

The disclosed embodiments provide an instruction synchronization device, chip, computer device, and data processing method. By inserting trigger instructions and wait instructions into an instruction queue and adjusting the count value of a counter using the trigger instructions and wait instructions, the instructions following the wait instruction can only be sent if the count value meets a preset numerical condition. Therefore, the above-mentioned method can control the order in which instructions in the multiple instruction queues are sent, thereby achieving instruction synchronization between the multiple instruction queues. The above-mentioned embodiments use hardware to achieve synchronization between instruction queues, thereby improving the efficiency of the hardware system.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to an instruction synchronization device, a chip, a computer device, and a data processing method. Background Art

[0002] Graphics processors and artificial intelligence accelerator chips often use multiple processes to increase processor computing power and enable parallel data processing. These numerous parallel processes have synchronization dependencies. For example, instructions in one process must be sent only after instructions in another process have been sent. Therefore, it is necessary to design a synchronization mechanism between instructions. However, the instruction synchronization mechanisms used in related technologies result in low hardware system efficiency. Summary of the Invention

[0003] In a first aspect, an embodiment of the present disclosure provides an instruction synchronization device, comprising: a counter, and multiple instruction queues; each instruction queue in the multiple instruction queues is used to store instructions, and the instructions include execution instructions and at least one of trigger instructions and wait instructions; the counter is used to make a first adjustment to the count value in response to receiving a trigger instruction, and to make a second adjustment to the count value in response to receiving a wait instruction; the adjustment method of the first adjustment is different from the adjustment method of the second adjustment; wherein, the instruction located after the wait instruction in an instruction queue is sent when the count value meets a preset numerical condition, and the preset numerical condition is determined based on the initial count value of the counter, the adjustment method of the first adjustment, and the adjustment method of the second adjustment.

[0004] In some embodiments, each instruction queue is used to parse the stored instructions, send the parsed trigger instructions and wait instructions to the counter, and send the parsed execution instructions to the execution unit.

[0005] In some embodiments, the adjustment method of one of the first adjustment and the second adjustment is to increase the count value according to a first preset step size, and the adjustment method of the other is to reduce the count value according to a second preset step size; the first preset step size is determined based on the number of waiting queues related to the target synchronization event in the multiple instruction queues, and the second preset step size is determined based on the number of waiting queues related to the target synchronization event in the multiple instruction queues.

[0006] In some embodiments, the trigger instruction carries the first preset step length, and the wait instruction carries the second preset step length.

[0007] In some embodiments, the first preset step size is equal to the product of the number of the waiting queues and a preset multiple, and the second preset step size is equal to the product of the number of the waiting queues and the preset multiple.

[0008] In some embodiments, the preset numerical condition is determined based on the initial counting value, the first preset step size, the second preset step size, and a preset multiple.

[0009] In some embodiments, the preset numerical condition is: the count value and the target count value satisfy a preset numerical relationship, and the target count value is: n*m*a-1+k0; wherein n is the first preset step size, m is the second preset step size, a is the preset multiple, and k0 is the initial count value; when the adjustment method of the first adjustment is to increase the count value and the adjustment method of the second adjustment is to reduce the count value, the numerical relationship is that the count value is greater than the target count value; when the adjustment method of the first adjustment is to reduce the count value and the adjustment method of the second adjustment is to increase the count value, the numerical relationship is that the count value is less than the target count value.

[0010] In some embodiments, the multiple instruction queues include a wait queue and a waiting queue; the wait queue includes multiple trigger instructions, each trigger instruction corresponds to a synchronization event, and the multiple trigger instructions are used to adjust the count value of the same counter; the first trigger instruction in the wait queue also includes a target wait instruction; each first wait instruction in the waiting queue also includes a target trigger instruction; the i-th first trigger instruction in the wait queue and the i-th first wait instruction in the waiting queue are instructions corresponding to the i-th synchronization event, and i is a positive integer.

[0011] In some embodiments, the number of the counters is greater than 1; the trigger instructions and wait instructions included in each instruction queue include: identification information of the counter, which is used for the instruction queue to send the trigger instructions and wait instructions included in the instruction queue to the corresponding counter.

[0012] In some embodiments, the instruction synchronization device further includes: an execution unit, configured to execute the received execution instruction.

[0013] In some embodiments, the instruction synchronization device further includes: an arbitration unit, configured to send the execution instructions sent by each instruction queue in the plurality of instruction queues to the execution unit according to a preset priority.

[0014] In some embodiments, the instruction synchronization device further includes: a multiplexer, configured to send the instruction to a corresponding instruction queue among the plurality of instruction queues.

[0015] In some embodiments, the trigger instruction and the wait instruction both include: identification information of an instruction queue, which is used by the multiplexer to send the trigger instruction and the wait instruction to the corresponding instruction queue.

[0016] In a second aspect, an embodiment of the present disclosure provides a chip, comprising: the instruction synchronization device described in any embodiment of the present disclosure.

[0017] In a third aspect, an embodiment of the present disclosure provides a computer device, comprising: the chip described in any embodiment of the present disclosure.

[0018] In a fourth aspect, an embodiment of the present disclosure provides a data processing method, which is applied to the instruction synchronization device described in any embodiment of the present disclosure, and the method includes: each instruction queue in a plurality of instruction queues stores instructions, and the instructions include execution instructions and at least one of trigger instructions and wait instructions; the counter makes a first adjustment to the count value in response to receiving the trigger instruction, and makes a second adjustment to the count value in response to receiving the wait instruction; the adjustment method of the first adjustment is different from the adjustment method of the second adjustment; each instruction queue sends the instruction located after the wait instruction in the queue when the count value meets a preset numerical condition, and the preset numerical condition is determined based on the initial count value of the counter, the adjustment method of the first adjustment, and the adjustment method of the second adjustment.

[0019] In some embodiments, the method further includes: each instruction queue parsing the stored instructions, sending the parsed trigger instructions and wait instructions to the counter, and sending the parsed execution instructions to the execution unit.

[0020] In some embodiments, the counter makes a first adjustment to the count value in response to receiving a trigger instruction, and makes a second adjustment to the count value in response to receiving a wait instruction, including: increasing the count value according to a first preset step size in response to receiving a trigger instruction, and decreasing the count value according to a second preset step size in response to receiving a wait instruction; or decreasing the count value according to a first preset step size in response to receiving a trigger instruction, and increasing the count value according to a second preset step size in response to receiving a wait instruction.

[0021] In some embodiments, the first preset step size is determined based on the number of waiting queues related to the target synchronization event in the multiple instruction queues, and the second preset step size is determined based on the number of waiting queues related to the target synchronization event in the multiple instruction queues.

[0022] In some embodiments, the method further includes: the counter acquiring the first preset step length carried in the trigger instruction, and acquiring the second preset step length carried in the wait instruction.

[0023] In some embodiments, the first preset step size is equal to the product of the number of the waiting queues and a preset multiple, and the second preset step size is equal to the product of the number of the waiting queues and the preset multiple.

[0024] In some embodiments, the preset numerical condition is determined based on the initial counting value, the first preset step size, the second preset step size, and a preset multiple.

[0025] In some embodiments, the preset numerical condition is: the count value and the target count value satisfy a preset numerical relationship, and the target count value is: n*m*a-1+k0; wherein n is the first preset step size, m is the second preset step size, a is the preset multiple, and k0 is the initial count value.

[0026] In some embodiments, the method further includes: when the adjustment method of the first adjustment is to increase the count value and the adjustment method of the second adjustment is to reduce the count value, each instruction queue determines the numerical relationship as the count value being greater than the target count value; when the adjustment method of the first adjustment is to reduce the count value and the adjustment method of the second adjustment is to increase the count value, each instruction queue determines the numerical relationship as the count value being less than the target count value.

[0027] In some embodiments, the multiple instruction queues include a wait queue and a waiting queue; the wait queue includes multiple trigger instructions, each trigger instruction corresponds to a synchronization event, and the multiple trigger instructions are used to adjust the count value of the same counter; the first trigger instruction in the wait queue also includes a target wait instruction; each first wait instruction in the waiting queue also includes a target trigger instruction; the first trigger instruction and the first wait instruction are both instructions corresponding to the remaining synchronization events except the last synchronization event.

[0028] In some embodiments, the number of counters is greater than 1; the method also includes: each instruction queue obtains the identification information of the counters included in the trigger instructions and wait instructions in this queue, and based on the identification information of the counters included in the trigger instructions and wait instructions in this queue, sends the trigger instructions and wait instructions in this queue to the corresponding counters.

[0029] In some embodiments, sending the parsed execution instruction to the execution unit includes: sending the parsed execution instruction to the arbitration unit, so that the arbitration unit sends the execution instruction sent by each instruction queue in the multiple instruction queues to the execution unit according to a preset priority.

[0030] In some embodiments, the method further includes: each instruction queue obtaining instructions sent by the multiplexer, and storing the instructions sent by the multiplexer.

[0031] In some embodiments, each instruction queue obtains the instruction sent by the multiplexer, including: each instruction queue obtains the instruction sent to the queue by the multiplexer based on identification information of the instruction queue included in the instruction.

[0032] The disclosed embodiment inserts trigger instructions and wait instructions into an instruction queue, and adjusts the count value of a counter using the trigger instructions and wait instructions. Since instructions following the wait instruction can only be sent if the count value meets a preset numerical condition, this method can control the order in which instructions in the multiple instruction queues are sent, thereby achieving instruction synchronization between the multiple instruction queues. The above embodiment uses hardware to achieve synchronization between instruction queues, thereby improving the efficiency of the hardware system.

[0033] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0035] Figure 1 It is a schematic diagram of the instruction synchronization process.

[0036] Figure 2 It is a structural diagram of the instruction synchronization device according to an embodiment of the present disclosure.

[0037] Figure 3 It is a schematic diagram of the instruction synchronization method of an embodiment of the present disclosure.

[0038] Figure 4 It is a schematic diagram of an instruction synchronization method according to another embodiment of the present disclosure.

[0039] Figure 5A This is a schematic diagram of an instruction synchronization method when multiple synchronization events are mapped to the same synchronization counter according to an embodiment of the present disclosure.

[0040] Figure 5B yes Figure 5A Schematic diagram of the order in which instructions are sent in the instruction queue.

[0041] Figure 6 It is a structural diagram of an instruction synchronization device according to another embodiment of the present disclosure.

[0042] Figure 7 It is a flowchart of the data processing method of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0044] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms "a", "the" and "the" used in this disclosure and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items. In addition, the term "at least one" herein means any combination of at least two of any one or more of a plurality of.

[0045] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining."

[0046] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present disclosure and to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings.

[0047] In a multi-process parallel processing scenario, a large number of processes working in parallel may have synchronization dependencies. For example, instructions in one process may need to be sent only after instructions in another process have been sent.

[0048] Instructions can be first issued to various instruction queues according to pre-set distribution rules. Instructions in different instruction queues may or may not have dependencies. If the instructions in two instruction queues do not have dependencies, the instructions in the two instruction queues can be sent in parallel, thereby improving the degree of parallelism between the instructions. If the instructions in two instruction queues do have dependencies, an instruction synchronization mechanism can be set up in the two queues to ensure that the dependent instructions are sent in a certain order.

[0049] See also Figure 1 , is a schematic diagram of instruction synchronization in some embodiments. Assuming that instructions q1 and q2 in instruction queue 1 depend on instructions Q1, Q2, and Q3 in instruction queue 2, that is, instructions q1 and q2 can only be sent when instructions Q1, Q2, and Q3 are all sent, the order in which each instruction is sent is shown as the time axis in the figure. Those skilled in the art will understand that the instruction sending order shown in the figure is only an exemplary description. In actual applications, the instructions in the same instruction queue are sent in sequence according to the order in which each instruction is stored in the instruction queue, and the instructions that do not have a dependency relationship between different instruction queues can be sent in any order. For example, the sending time of instruction Q4 can be earlier than the sending time of instruction q3, or instruction Q1 can also be sent between instruction q3 and instruction q4. However, since instructions q1 and q2 depend on instructions Q1, Q2, and Q3, the sending time of instructions Q1, Q2, and Q3 are all earlier than instruction q1, and all earlier than instruction q2.

[0050] In the related art, an instruction counter is deployed for each instruction queue to count the instructions sent by the current instruction queue, and other instruction queues are synchronized by waiting for the count value of the instruction counter of the corresponding instruction queue. However, in this instruction synchronization method, there is only a producer but no consumer, which may lead to overflow risk, and the instructions in each instruction queue may be of the same type. In order to solve the above problems, another related technology adopts a producer-consumer model to deploy a state synchronization counter between every two instruction queues to achieve instruction synchronization. However, this method adopts a static deployment method of state synchronization counters. Assuming that the number of instruction queues is N, the number of state synchronization counters that need to be deployed is N*(N-1), resulting in a waste of counters. In order to solve this technical problem, there is a related technology that dynamically allocates state synchronization counters according to synchronization events. However, this method is implemented in software, which reduces the efficiency of the hardware system.

[0051] Based on this, the present disclosure provides an instruction synchronization device, see Figure 2 and Figure 6 , the device comprises:

[0052] A counter 201 and a plurality of instruction queues 202; each instruction queue in the plurality of instruction queues 202 (e.g., instruction queue 1, instruction queue 2, instruction queue 3, instruction queue 4, etc.) is used to store instructions, including execution instructions and at least one of a trigger instruction Trigger and a wait instruction Wait;

[0053] The counter 201 is configured to make a first adjustment to the count value in response to receiving a trigger instruction Trigger, and to make a second adjustment to the count value in response to receiving a wait instruction Wait; an adjustment method of the first adjustment is different from an adjustment method of the second adjustment;

[0054] Among them, the instruction located after the waiting instruction Wait in an instruction queue 202 is sent when the count value meets the preset numerical condition, and the preset numerical condition is determined based on the initial count value of the counter 201, the adjustment method of the first adjustment and the adjustment method of the second adjustment.

[0055] In this embodiment, the number of counters (also called synchronous counters) 201 can be greater than or equal to 1, and the number of instruction queues 202 can be greater than or equal to 2. The figure shows a case where the number of counters 201 and the number of instruction queues 202 are both 4, but those skilled in the art will understand that the situation shown in the figure is not intended to limit the present disclosure. The number of counters 201 and the number of instruction queues 202 can be set to other numbers greater than 4 or less than 4 according to actual needs, and the number of counters 201 and the number of instruction queues 202 can be equal to or unequal to each other.

[0056] An instruction queue 202 can be used to store execution instructions, which are sent to the execution unit for execution. For example, the execution instruction may include, but is not limited to, at least one of various operation instructions such as addition instructions, multiplication instructions, and convolution multiplication instructions. The execution unit can respond to the execution instruction and perform operations on the acquired target data. The target data can be various forms of data, such as image data, voice data, and text data.

[0057] The instructions in one or more instruction queues may have dependencies with the instructions in one or more other instruction queues. In order to synchronize the dependent instructions, a trigger instruction Trigger and a wait instruction Wait may be inserted into the instruction queue. The instructions in each instruction queue may have different dependencies at different times. For example, at time t1, the instructions in instruction queue 1 need to wait for the instructions in instruction 2 to be sent before they can be sent (this situation is called instruction queue 1 waiting for instruction queue 2, instruction queue 1 is called the waiting queue, and instruction queue 2 is called the waiting queue); at time t2, there is no dependency between the instructions in instruction queue 1 and the instructions in instruction queue 2; at time t3, instruction queue 2 needs to wait for instruction queue 1.

[0058] In the above example, instruction queue 1 waiting for instruction queue 2 is called a synchronization event, the waiting queue involved in a synchronization event is called the waiting queue corresponding to the synchronization event, and the waiting queue involved in a synchronization event is called the waiting queue corresponding to the synchronization event. The same instruction queue may correspond to one or more synchronization events. For example, at a certain moment, an instruction in instruction queue 1 needs to wait for an instruction in instruction queue 2 to be sent before it can be sent; at another moment, an instruction in instruction queue 1 needs to wait for two instructions in instruction queue 3 to be sent before it can be sent; at another moment, three instructions in instruction queue 4 need to wait for two instructions in instruction queue 1 to be sent before they can be sent. In the above example, instruction queue 1 corresponds to three synchronization events respectively.

[0059] For ease of understanding, let's take two dependent instruction queues as an example. First, after receiving instructions, the instruction queue can store each instruction in the order in which it is received, and can also parse the stored instructions. Each instruction can include the type of instruction to which it belongs. The instruction queue can determine whether the instruction is an execution instruction, a trigger instruction, or a wait instruction based on the instruction type. Figure 3 , where Instruction 1, Instruction 2, Instruction 3, etc. represent execution instructions, Trigger and Wait represent trigger instructions and wait instructions, respectively. Instructions following the wait instruction in Instruction Queue 1 must wait for all instructions preceding the trigger instruction in Instruction Queue 2 to be sent before they can be sent. After parsing the execution instruction, the instruction queue can send the execution instruction to the execution unit; after parsing the trigger instruction or wait instruction, it can send the trigger instruction or wait instruction to counter 201.

[0060] The trigger instruction and the wait instruction can respectively trigger the counter's count value to be adjusted in a first adjustment mode or a second adjustment mode. For example, by sending a trigger instruction to the counter, the counter can be triggered to increase the count value, and by sending a wait instruction to the counter, the counter can be triggered to decrease the count value. Alternatively, by sending a trigger instruction to the counter, the counter can be triggered to decrease the count value, and by sending a wait instruction to the counter, the counter can be triggered to increase the count value.

[0061] In some embodiments, one of the first adjustment and the second adjustment is adjusted by increasing the count value according to a first preset step size, and the other is adjusted by decreasing the count value according to a second preset step size. For example, each trigger instruction can trigger the counter to increase the count value by 1, and each wait instruction can trigger the counter to decrease the count value by 1. Of course, in addition to using 1 as the first preset step size and the second preset step size, other positive integers can also be used as the first preset step size and the second preset step size. For example, in Figure 3 In the embodiment shown, the first preset step size and the second preset step size may both be 2. In this case, each trigger instruction may trigger the counter to add 2 to the count value, and each wait instruction may trigger the counter to subtract 2 from the count value. In a target synchronization event, when the number of waiting queues is different from the number of waited queues, the first preset step size may not be equal. Specifically, the first preset step size is determined based on the number of waiting queues associated with the target synchronization event in the multiple instruction queues, and the second preset step size is determined based on the number of waited queues associated with the target synchronization event in the multiple instruction queues. For example, assuming that the number of waiting queues is n and the number of waited queues is m, the first preset step size may be set to n*a, and the second preset step size may be set to m*a, where a is a positive integer.

[0062] In some embodiments, the trigger instruction carries the first preset step size, and the wait instruction carries the second preset step size. Because the instructions carry step size information, the counter can directly read the corresponding step size information from the instructions after receiving the trigger instruction or the wait instruction, thereby determining the step size for increasing or decreasing the count value. Furthermore, the trigger instruction may also carry identification information for representing the adjustment method for the first adjustment, and the wait instruction may also carry identification information for representing the adjustment method for the second adjustment, so that the counter can determine which adjustment method to use to adjust the counter's step size.

[0063] The instruction in an instruction queue that follows the waiting instruction is sent only when the count value of the counter meets the preset numerical condition. In this way, the sending order of the instructions in the instruction queue can be controlled based on the count value of the counter, thereby achieving instruction synchronization between the multiple instruction queues. In some embodiments, the preset numerical condition is determined based on the initial count value, the first preset step size, the second preset step size, and the preset multiple. Specifically, the preset numerical condition can be that the count value of the counter and the target count value meet a preset numerical relationship. Among them, the product of the first preset step size, the second preset step size, and the preset multiple can be determined, the product and the initial count value are summed, and the target count value is determined based on the summation result. Assuming that the first preset step size is recorded as n, the second preset step size is recorded as m, the preset multiple is recorded as a, and the initial count value is recorded as k0, the target count value can be recorded as n*m*a-1+k0.

[0064] Different numerical relationships can be determined in different situations. For example, in Method 1, the first adjustment method is to increase the count value, and the second adjustment method is to decrease the count value. In this case, the numerical relationship is that the count value is greater than the target count value. In Method 2, the first adjustment method is to decrease the count value, and the second adjustment method is to increase the count value. In this case, the numerical relationship is that the count value is less than the target count value. The following uses Method 1 as an example to illustrate the solution of the embodiment of the present disclosure.

[0065] exist Figure 3In the illustrated embodiment, m and n are both equal to 1, and it is assumed that the preset multiplier a is also equal to 1, and the initial count value of the counter is 0. Instructions 4 and 5 in instruction queue 1 must wait until instructions 1 and 2 in instruction queue 2 are completed before they can be sent. Therefore, a trigger instruction Trigger can be inserted after instruction 2 in instruction queue 2, and a wait instruction Wait can be inserted before instruction 4 in instruction queue 1. Instruction queue 2 can parse each instruction in its queue and send the parsed instructions sequentially. Instructions 1 and 2 are both execution instructions and can be sent to the execution unit in sequence. At the same time, instruction queue 1 can send the execution instructions in its queue (i.e., instruction 1, instruction 2, and instruction 3) in parallel. Instructions with the same label, such as instruction 1 and instruction 2, in the two instruction queues described above can be the same instruction or different instructions. The instruction label here only indicates the relative position of the instruction in the instruction queue to which it belongs and does not indicate the content or type of the instruction. Since the sending completion time of each instruction in different instruction queues that has no dependency relationship is random, it is possible that instruction 3 in instruction queue 1 is sent before instruction 2 in instruction queue 2, or it is possible that instruction 2 in instruction queue 2 is sent before instruction 3 in instruction queue 1.

[0066] Regardless of the above situation, since the trigger instruction and the wait instruction are inserted into the two instruction queues respectively, after the instruction queue 2 parses the trigger instruction Trigger, it will send the trigger instruction Trigger to the counter. After the counter receives the trigger instruction Trigger, it will add 1 to the count value. After the instruction queue 1 parses the wait instruction Wait, it can read the count value of the counter. Only when the count value of the counter is greater than 0, the instruction queue 1 will send the wait instruction Wait and the instructions after the wait instruction Wait. Otherwise, the wait instruction Wait and the instructions after the wait instruction Wait will not be sent. When the counter receives the wait instruction Wait, it can subtract 1 from the count value. In the above manner, a synchronization event is completed. If there are other synchronization events between the two instruction queues, continue to synchronize the instructions according to the above process.

[0067] exist Figure 4In the more general case shown, m and n are both positive integers greater than 1, and m and n can be unequal. This situation is called n instruction queues waiting for m instruction queues. Instructions 4 and 5 in each waiting queue (i.e., instruction queues 1 through n above the counter) must wait for instruction 3 in all waiting queues (i.e., instruction queues 1 through m below the counter) to be sent before they can be sent. Assuming the initial count value is 0 and the preset multiplier a is 1, after each waiting queue (e.g., instruction queue 1) sends a trigger instruction to the counter, the counter value is incremented by n. Thus, after all waiting queues have sent their trigger instructions, the counter value is n*m. Upon receiving a wait instruction, each waiting queue can read the counter value. If the count value is greater than n*m-1, the waiting queue can send a wait instruction to decrement the counter value by m. After all waiting queues have sent their wait instructions, the counter value returns to 0. This completes a synchronization event.

[0068] Of course, the situation shown in the figure is only an exemplary description. In actual applications, the positions of the instructions in the waiting state in each waiting queue in the instruction queue to which they belong may be different, and the positions of the instructions in the waiting state in each waited queue in the instruction queue to which they belong may also be different.

[0069] In the embodiment of determining the numerical relationship using the above-mentioned method 2, the synchronization process of the synchronization event is the same as Figure 3 and Figure 4 The illustrated embodiment is similar and will not be further described here. The only difference is that upon receiving a trigger instruction, the counter subtracts the corresponding value from the initial count value (e.g., 5). Upon receiving a wait instruction, the counter increments the corresponding value. Only when the count value is less than the initial count value can the wait instruction continue to be sent. In this way, a synchronization event is also completed.

[0070] When multiple synchronization events are mapped to one counter, the trigger instruction in the later synchronization event may cause the wait instruction in the earlier synchronization event to trigger incorrectly. Figure 5A and Figure 5B , assuming that there are two synchronization events, namely: (1) instruction queues 1 and 2 wait for instruction queues 3, 4, and 5; and (2) instruction queues 1 and 2 wait for instruction queue 3. Among them, Trigger1 in instruction queues 3, 4, and 5 and Wait1 in instruction queues 1 and 2 correspond to the first synchronization event, and Trigger2 in instruction queue 3 and Wait2 in instruction queues 1 and 2 correspond to the second synchronization event. The various instruction queues obtained by inserting trigger instructions and wait instructions in the above embodiment are as follows Figure 5A As shown in the first case, since the time when each instruction queue sends the trigger is random, in some cases, the trigger instruction Trigger2 in instruction queue 3 may be sent earlier than the time when the trigger instruction Trigger1 in instruction queue 4 is sent. The sending time sequence of each instruction is as follows: Figure 5B For simplicity, the figure only shows the sending order of the trigger instructions in instruction queues 3, 4, and 5.

[0071] Assuming the initial count value is 0, the counter increments by n for each trigger instruction received, and decrements by m for each wait instruction received, where n and m are the number of wait queues and the number of waited queues in a synchronization event, respectively. In the first synchronization event described above, n is 2 and m is 3. That is, when the counter count value is greater than 5, the wait instruction in the wait queue and the execution instruction following the wait instruction can be sent. In this embodiment, since Trigger2 in Instruction Queue 3 is sent before Trigger1 in Instruction Queue 4, after Instruction Queue 4 sends Trigger1, the counter count value will reach 6, triggering the wait queue to send the relevant instruction. However, the actual situation is that Trigger1 in Instruction Queue 5 has not yet been sent, and the relevant instructions in the wait queue do not meet the sending conditions. It can be seen that in the above situation, Trigger2 in Instruction Queue 3 will mistakenly trigger the Wait of Synchronous Event 1.

[0072] In order to solve the above problems, the multiple instruction queues described in the embodiment of the present disclosure include a wait queue and a waiting queue; the wait queue includes multiple trigger instructions, each trigger instruction corresponds to a synchronization event, and the multiple trigger instructions are used to adjust the count value of the same counter; the first trigger instruction in the wait queue also includes a target wait instruction; each first wait instruction in the waiting queue also includes a target trigger instruction; the i-th first trigger instruction in the wait queue and the i-th first wait instruction in the waiting queue are instructions corresponding to the i-th synchronization event, and i is a positive integer.

[0073] Among them, the number of waiting queues can be greater than or equal to 1, and the number of wait queues can also be greater than or equal to 1. The first trigger instructions corresponding to different synchronization events can come from one or more wait queues, and the first waiting instructions corresponding to different synchronization events can come from one or more waiting queues. Assuming that the total number of synchronization events is N, the first trigger instruction corresponding to the 1st synchronization event, the first trigger instruction corresponding to the 2nd synchronization event, ..., the first trigger instruction corresponding to the N-1th synchronization event, each include a target waiting instruction after it; and the first waiting instruction corresponding to the 1st synchronization event, the first waiting instruction corresponding to the 2nd synchronization event, ..., the first waiting instruction corresponding to the N-1th synchronization event, each include a target trigger instruction after it. The first trigger instruction corresponding to the Nth synchronization event may or may not include a target waiting instruction, and the first waiting instruction corresponding to the Nth synchronization event may or may not include a target trigger instruction.

[0074] If the first trigger instruction corresponding to a certain synchronization event comes from multiple waiting queues, then the first trigger instruction in each of these multiple waiting queues includes a target waiting instruction. For example, a synchronization event is instruction 1 in instruction queue 2 waiting for instruction 2 in instruction queue 3 and instruction 3 in instruction queue 4, then instruction queue 3 and instruction queue 4 both include the first trigger instruction corresponding to the synchronization event, so that the first trigger instruction in instruction queue 3 includes a target waiting instruction, and the first trigger instruction in instruction queue 4 also includes a target waiting instruction. Similarly, if the first waiting instruction corresponding to a certain synchronization event comes from multiple waiting queues, then the first trigger instruction in each of these multiple waiting queues includes a target trigger instruction. For example, a synchronization event is instruction 1 in instruction queue 1 and instruction 1 in instruction queue 2 waiting for instruction 2 in instruction queue 3, then instruction 1 and instruction queue 2 both include the first waiting instruction corresponding to the synchronization event, so that the first waiting instruction in instruction queue 1 includes a target trigger instruction, and the first waiting instruction in instruction queue 2 also includes a target trigger instruction.

[0075] See also Figure 5A Case 2 and Figure 5BIn the instruction sending order of case 2, the first trigger instruction is Trigger1 in instruction queue 3, the target waiting instruction is Wait after Trigger1 in instruction queue 3, the first waiting instruction is Wait1 in instruction queue 1 and Wait1 in instruction queue 2, and the target trigger instruction is Trigger after Wait1 in instruction queue 1 and Trigger after Wait1 in instruction queue 2. If the instructions in instruction queue 3 are sent faster, Trigger1 in instruction queue 3 may be sent first. However, since Wait is inserted after Trigger1 in instruction queue 3, when Trigger1 in instruction queue 3 is sent and Trigger1 in instruction queues 4 and 5 is not sent, Wait in instruction queue 3 does not meet the sending conditions. Therefore, after Trigger1 in instruction queue 3 is sent and completed, it will enter the waiting state. Similarly, Wait1 in instruction queue 1 and Wait1 in instruction queue 2 will cause instruction queues 1 and 2 to enter the waiting state. Therefore, Trigger 1 in instruction queue 4 and Trigger 1 in instruction queue 5 will be sent first. This ensures that the Trigger of the second synchronization event can take effect only after the Wait of the first synchronization event occurs normally.

[0076] exist Figure 5A and Figure 5B In the embodiment shown, the number of synchronization events mapped to the same counter is 2, that is, there is at least one waiting queue (instruction queue 3 in the figure) corresponding to two synchronization events respectively. In actual applications, the number of synchronization events mapped to the same counter may be greater than 2, and there may be more than one waiting queue corresponding to multiple synchronization events respectively. In addition, although the waiting queues in the two synchronization events shown in the figure are the same (both are instruction queue 1 and instruction queue 2), in actual applications, the waiting queues in different events may also be partially the same, or completely different. In addition, the position of the target waiting instruction after the first trigger instruction does not have to be adjacent to the first trigger instruction, as long as it is between the first trigger instruction and the next first trigger instruction after the first trigger instruction. Similarly, the position of the target trigger instruction after the first wait instruction does not have to be adjacent to the first wait instruction, as long as it is between the first wait instruction and the next first wait instruction after the first wait instruction. For example, in Figure 5A In the instruction queue 3 shown in the second case, the Wait after Trigger1 can be at any position between Trigger1 and Trigger2. Figure 5AIn the instruction queue 2 shown in the second case, the Trigger after Wait1 can be at any position between Wait1 and Wait2. In the above case, the false triggering of the synchronization event can also be avoided by inserting the target wait instruction and the target trigger instruction, which will not be repeated here.

[0077] In some embodiments, the number of counters 201 is greater than 1. In this case, each instruction queue includes a trigger instruction and a wait instruction, each of which includes counter identification information, so that the instruction queue sends the trigger instruction and wait instruction included in the instruction queue to the corresponding counter. Alternatively, the identification information of the trigger instruction and the identification information of the wait instruction can be bound to the identification information of the counter, respectively, so that the instruction queue sends the trigger instruction and the wait instruction to the corresponding counter.

[0078] In some embodiments, the instruction synchronization apparatus further includes an execution unit 203 for executing received execution instructions. The number of execution units can be greater than or equal to one, and one execution unit can receive and process execution instructions from one or more instruction queues. An execution unit can be a subunit within a processing unit with instruction execution capabilities. The processing unit can be divided into multiple groups of execution units at different granularities, each group of execution units being used to execute a processing task (e.g., an addition operation). Different granularities can be used in different scenarios based on practical needs. For example, assuming a processing unit includes R execution units, these R execution units can be divided into groups s1, each including r1 execution units, or into groups s2, each including r2 execution units, where R = s1 * r1 = s2 * r2. This division method offers greater flexibility. If a processing task requires fewer execution units, the execution units can be divided into more groups, thereby increasing the parallelism of task processing. Upon completing instruction processing, the execution unit can also return a response signal (ACK) to the arbitration unit, allowing the arbitration unit to continue sending new instructions.

[0079] In some embodiments, the instruction synchronization apparatus further includes an arbitration unit 204 configured to send execution instructions sent by each of the plurality of instruction queues to the execution unit according to a preset priority. The number of arbitration units 204 may be greater than or equal to one. While the figure illustrates a case where the number of arbitration units is equal to the number of instruction queues, in actual applications, the number of arbitration units and instruction queues may be unequal.

[0080] In some embodiments, the instruction synchronization apparatus further comprises a multiplexer 205 for sending the instruction to a corresponding instruction queue among the plurality of instruction queues. In some embodiments, both the trigger instruction and the wait instruction include identification information of the instruction queue, for the multiplexer 205 to send the trigger instruction and the wait instruction to the corresponding instruction queue.

[0081] The present disclosure provides a hardware-implemented dynamic deployment mechanism for instruction queue state synchronization counters, which saves counter overhead and eliminates overflow risks; at the same time, the use of hardware to implement dynamic deployment of counters also realizes efficient and flexible multi-process scheduling. The embodiment of the present disclosure has strong scalability and can adjust the number of state counters, the number of instruction queues, and the number of execution units according to needs. The instruction synchronization device of the embodiment of the present disclosure can be applied to processing chips such as artificial intelligence chips and graphics processing chips to achieve efficient and flexible instruction queue deployment and scheduling, thereby improving the parallel efficiency of the execution units.

[0082] The various instructions in the above embodiments, including trigger instructions, wait instructions, and execute instructions, can be generated in advance by offline compilation. Each instruction can be generated in the required order and sent to the instruction queue during offline compilation.

[0083] In some embodiments, the present disclosure further provides a chip comprising the instruction synchronization device described in any embodiment of the present disclosure. The chip may be an artificial intelligence chip, a graphics processing chip, or another type of processing chip. The details of the instruction synchronization device in this chip embodiment can be referenced to the aforementioned embodiments of the instruction synchronization device and are not further described here.

[0084] The present disclosure also provides a computer device, comprising the chip described in any embodiment of the present disclosure. The specific functions of the chip can be found in the description of the chip embodiment above, and will not be repeated here for the sake of brevity.

[0085] like Figure 7 As shown, an embodiment of the present disclosure further provides a data processing method, which is applied to the instruction synchronization device described in any embodiment of the present disclosure, and the method includes:

[0086] Step 701: Each instruction queue in a plurality of instruction queues stores instructions, wherein the instructions include execution instructions and at least one of trigger instructions and wait instructions;

[0087] Step 702: the counter performs a first adjustment on the count value in response to receiving a trigger instruction, and performs a second adjustment on the count value in response to receiving a wait instruction; the adjustment manner of the first adjustment is different from the adjustment manner of the second adjustment;

[0088] Step 703: Each instruction queue sends the instruction following the waiting instruction in the queue when the count value meets the preset numerical condition, and the preset numerical condition is determined based on the initial count value of the counter, the adjustment method of the first adjustment and the adjustment method of the second adjustment.

[0089] In some embodiments, the method further includes: each instruction queue parsing the stored instructions, sending the parsed trigger instructions and wait instructions to the counter, and sending the parsed execution instructions to the execution unit.

[0090] In some embodiments, the counter makes a first adjustment to the count value in response to receiving a trigger instruction, and makes a second adjustment to the count value in response to receiving a wait instruction, including: increasing the count value according to a first preset step size in response to receiving a trigger instruction, and decreasing the count value according to a second preset step size in response to receiving a wait instruction; or decreasing the count value according to a first preset step size in response to receiving a trigger instruction, and increasing the count value according to a second preset step size in response to receiving a wait instruction.

[0091] In some embodiments, the first preset step size is determined based on the number of waiting queues related to the target synchronization event in the multiple instruction queues, and the second preset step size is determined based on the number of waiting queues related to the target synchronization event in the multiple instruction queues.

[0092] In some embodiments, the method further includes: the counter acquiring the first preset step length carried in the trigger instruction, and acquiring the second preset step length carried in the wait instruction.

[0093] In some embodiments, the first preset step size is equal to the product of the number of the waiting queues and a preset multiple, and the second preset step size is equal to the product of the number of the waiting queues and the preset multiple.

[0094] In some embodiments, the preset numerical condition is determined based on the initial counting value, the first preset step size, the second preset step size, and a preset multiple.

[0095] In some embodiments, the preset numerical condition is: the count value and the target count value satisfy a preset numerical relationship, and the target count value is: n*m*a-1+k0; wherein n is the first preset step size, m is the second preset step size, a is the preset multiple, and k0 is the initial count value.

[0096] In some embodiments, the method further includes: when the adjustment method of the first adjustment is to increase the count value and the adjustment method of the second adjustment is to reduce the count value, each instruction queue determines the numerical relationship as the count value being greater than the target count value; when the adjustment method of the first adjustment is to reduce the count value and the adjustment method of the second adjustment is to increase the count value, each instruction queue determines the numerical relationship as the count value being less than the target count value.

[0097] In some embodiments, the multiple instruction queues include a wait queue and a waiting queue; the wait queue includes multiple trigger instructions, each trigger instruction corresponds to a synchronization event, and the multiple trigger instructions are used to adjust the count value of the same counter; the first trigger instruction in the wait queue also includes a target wait instruction; each first wait instruction in the waiting queue also includes a target trigger instruction; the first trigger instruction and the first wait instruction are both instructions corresponding to the remaining synchronization events except the last synchronization event.

[0098] In some embodiments, the number of counters is greater than 1; the method also includes: each instruction queue obtains the identification information of the counters included in the trigger instructions and wait instructions in this queue, and based on the identification information of the counters included in the trigger instructions and wait instructions in this queue, sends the trigger instructions and wait instructions in this queue to the corresponding counters.

[0099] In some embodiments, sending the parsed execution instruction to the execution unit includes: sending the parsed execution instruction to the arbitration unit, so that the arbitration unit sends the execution instruction sent by each instruction queue in the multiple instruction queues to the execution unit according to a preset priority.

[0100] In some embodiments, the method further includes: each instruction queue obtaining instructions sent by the multiplexer, and storing the instructions sent by the multiplexer.

[0101] In some embodiments, each instruction queue obtains the instruction sent by the multiplexer, including: each instruction queue obtains the instruction sent to the queue by the multiplexer based on identification information of the instruction queue included in the instruction.

[0102] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email transceiver, game console, tablet computer, wearable device, or any combination of these devices.

[0103] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device embodiment described above is merely illustrative, wherein the modules described as separate components may or may not be physically separated, and when implementing the embodiment scheme of this specification, the functions of each module can be implemented in the same one or more software and / or hardware. It is also possible to select some or all of the modules according to actual needs to achieve the purpose of the embodiment scheme. A person of ordinary skill in the art can understand and implement it without paying any creative work.

[0104] The above is only a specific implementation of the embodiment of this specification. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the embodiment of this specification. These improvements and modifications should also be regarded as the scope of protection of the embodiment of this specification.

Claims

1. A command synchronization device, characterized in that: The device comprises: counters, and multiple instruction queues; Each of the plurality of instruction queues is used to store instructions, wherein the instructions include execution instructions and at least one of trigger instructions and wait instructions; The counter is configured to make a first adjustment to a count value in response to receiving a trigger instruction, and to make a second adjustment to the count value in response to receiving a wait instruction; an adjustment method of the first adjustment is different from an adjustment method of the second adjustment; wherein an instruction in an instruction queue that follows the waiting instruction is sent when the count value satisfies a preset numerical condition, and the preset numerical condition is determined based on an initial count value of the counter, an adjustment method of the first adjustment, and an adjustment method of the second adjustment; One of the first adjustment and the second adjustment is an adjustment method of increasing the count value according to a first preset step size, and the other adjustment method is a adjustment method of decreasing the count value according to a second preset step size; The preset numerical condition is that the count value of the counter and the target count value meet a preset numerical relationship, and the target count value is obtained based on the following method: Determine the product of the first preset step size, the second preset step size, and a preset multiple; Summing the product and the initial count value, and determining the target count value based on the summation result; In a case where the first adjustment is to increase the count value and the second adjustment is to decrease the count value, the numerical relationship is that the count value is greater than the target count value; In a case where the first adjustment is performed in a manner of decreasing the count value and the second adjustment is performed in a manner of increasing the count value, the numerical relationship is that the count value is smaller than the target count value.

2. The instruction synchronization device according to claim 1, characterized in that: Each instruction queue is used to parse the stored instructions, send the parsed trigger instructions and wait instructions to the counter, and send the parsed execution instructions to the execution unit.

3. The instruction synchronization device according to claim 1, characterized in that: The first preset step size is determined based on the number of waiting queues related to the target synchronization event in the multiple instruction queues, and the second preset step size is determined based on the number of waiting queues related to the target synchronization event in the multiple instruction queues.

4. The instruction synchronization device according to claim 3, characterized in that: The trigger instruction carries the first preset step length, and the wait instruction carries the second preset step length.

5. The instruction synchronization device according to claim 3, characterized in that: The first preset step length is equal to the product of the number of the waiting queues and a preset multiple, and the second preset step length is equal to the product of the number of the waiting queues and the preset multiple.

6. The instruction synchronization device according to claim 1, characterized in that: The target count value is: n*m*a-1+k0; Among them, n is the first preset step size, m is the second preset step size, a is the preset multiple, and k0 is the initial counting value.

7. The instruction synchronization device according to claim 1, characterized in that: The multiple instruction queues include a waiting queue and a waiting queue; the waiting queue includes multiple trigger instructions, each trigger instruction corresponds to a synchronization event, and the multiple trigger instructions are used to adjust the count value of the same counter; The first trigger instruction in the waiting queue also includes a target waiting instruction; Each first waiting instruction in the waiting queue also includes a target trigger instruction; The i-th first trigger instruction in the waiting queue and the i-th first waiting instruction in the waiting queue are instructions corresponding to the i-th synchronization event, where i is a positive integer.

8. The instruction synchronization device according to claim 1, characterized in that: The number of the counters is greater than 1; each instruction queue includes the trigger instruction and the wait instruction including: The identification information of the counter is used for the instruction queue to send the trigger instruction and the wait instruction included in the instruction queue to the corresponding counter.

9. The instruction synchronization device according to claim 1, characterized in that: The instruction synchronization device also includes: The execution unit is used to execute the received execution instruction.

10. The instruction synchronization device according to claim 9, characterized in that: The instruction synchronization device also includes: The arbitration unit is configured to send the execution instructions sent by each instruction queue in the plurality of instruction queues to the execution unit according to a preset priority.

11. The instruction synchronization device according to claim 1, characterized in that: The instruction synchronization device also includes: A multiplexer is used to send the instruction to a corresponding instruction queue among the multiple instruction queues.

12. The instruction synchronization device according to claim 11, characterized in that: The trigger instruction and the wait instruction both include: The identification information of the instruction queue is used by the multiplexer to send the trigger instruction and the wait instruction to the corresponding instruction queue.

13. A chip, characterized in that: The chip includes: The instruction synchronization device according to any one of claims 1 to 12.

14. A computer device, characterized in that: Comprising the chip according to claim 13.

15. A data processing method, characterized in that: The method applied to the instruction synchronization device according to any one of claims 1 to 12 comprises: Each of the plurality of instruction queues stores instructions, the instructions including execution instructions and at least one of trigger instructions and wait instructions; The counter performs a first adjustment on the count value in response to receiving a trigger instruction, and performs a second adjustment on the count value in response to receiving a wait instruction; the adjustment manner of the first adjustment is different from the adjustment manner of the second adjustment; Each instruction queue sends the instruction following the waiting instruction in the queue when the count value meets the preset numerical condition, and the preset numerical condition is determined based on the initial count value of the counter, the adjustment method of the first adjustment and the adjustment method of the second adjustment.

Images