Storage System

Abstract

The embodiments provide a memory system capable of suppressing temperature rise and improving performance and reliability through die-level temperature control of the non-volatile semiconductor memory. The memory system of the embodiments includes: a non-volatile semiconductor memory having multiple dies, temperature sensors disposed for each die, and a memory controller. The temperature sensors measure the temperature of the dies. The memory controller schedules the execution of access commands per die based on the temperature, predetermined limit temperatures for each die, and access commands for accessing the non-volatile semiconductor memory.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2020-155774 (filed on September 16, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to storage systems. Background Technology

[0003] A storage system is known that has a non-volatile memory with storage cells stacked in a three-dimensional manner. In such a storage system, performance is tuned to prevent the temperature from rising excessively. Summary of the Invention

[0004] The problem to be solved by the implementation method is to provide a storage system that can suppress temperature rise and improve performance and reliability through die-level temperature control of non-volatile semiconductor memory.

[0005] The storage system described in this embodiment includes: a non-volatile semiconductor memory having multiple dies; temperature sensors, each disposed for each die; and a storage controller. The temperature sensors measure the temperature of the dies. The storage controller schedules access commands for each die based on the temperature, predetermined limit temperatures for each die, and access commands for accessing the non-volatile semiconductor memory. Attached Figure Description

[0006] Figure 1A It is a block diagram of an information processing system including the storage system involved in the implementation.

[0007] Figure 1B This is a block diagram of the non-volatile memory involved in the implementation method.

[0008] Figure 1C This is a block diagram of the storage controller involved in the implementation method.

[0009] Figure 2 This is a block diagram of the bare die involved in the implementation method.

[0010] Figure 3 This is a block diagram of the planar structure of the memory cell array involved in the implementation method.

[0011] Figure 4 This is a block diagram showing the structure of the blocks involved in the implementation method.

[0012] Figure 5 This is a circuit diagram of the blocks involved in the implementation method.

[0013] Figure 6 This is a block diagram showing the table used in the temperature control of the storage system involved in the implementation.

[0014] Figure 7A This is a diagram illustrating an example of the data structure of the IPC queue involved in the implementation.

[0015] Figure 7B This is a diagram illustrating an example of the data structure of a NAND modeled table involved in the implementation.

[0016] Figure 8 This is a block diagram illustrating an example of the functional configuration of the firmware involved in the implementation method.

[0017] Figure 9 This is a flowchart illustrating the temperature control of the storage system involved in the implementation method.

[0018] Figure 10 This is a schematic diagram of the scheduling table used in the temperature control of the storage system involved in the implementation.

[0019] Figure 11 This is a schematic diagram of a weighted table used in the temperature control of the storage system involved in the implementation.

[0020] Figure 12 This is a schematic diagram of the timing of temperature control operation for each die in the storage system according to the implementation method.

[0021] Label Explanation

[0022] 1. Storage System

[0023] 2. Main unit

[0024] 3. Non-volatile memory

[0025] 10, 10_1~10_16 nude films

[0026] 11, 11_1~10_16 memory cell array

[0027] 12 Sensing Amplifier Module

[0028] 13-line decoder module

[0029] 14 Input / Output Circuits

[0030] 15 Registers

[0031] 16 Logic Controller

[0032] 17 Sequencer

[0033] 18 Ready / Busy Control Circuit

[0034] 19 Voltage Generation Circuit

[0035] 20 Storage Controller

[0036] 21 CPU

[0037] 22. Built-in memory

[0038] 23. Host I / F Circuit

[0039] 24. Clock Control Department

[0040] Temperature sensors 25, 25_1 to 25_16

[0041] 26 NAND I / F Circuits

[0042] 27 Volatile Memory I / F Circuit

[0043] 30 P-type trap region

[0044] 31-36: Conductors

[0045] 37 insulating films

[0046] 38. Insulating film (charge storage layer)

[0047] 39 Tunnel Oxide Film

[0048] 40 Semiconductor Materials

[0049] 41 n + Impurity diffusion region

[0050] 42 p + Impurity diffusion region

[0051] 60 firmware

[0052] 70 Host I / F Processing Module

[0053] 80 Tables

[0054] 81 Inter-Process Communication (IPC) Queue

[0055] 82 NAND Modeling Table

[0056] 83. Arrange the scheduling table

[0057] 100 Information Processing System

[0058] 110 Volatile Memory Detailed Implementation

[0059] Next, the embodiments will be described with reference to the accompanying drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. The drawings are schematic.

[0060] Furthermore, the embodiments shown below are illustrative of apparatuses and methods for realizing technical ideas, and are not limited in terms of the material, shape, structure, or arrangement of components. Various modifications can be made to the embodiments.

[0061] [Implementation Method]

[0062] (Storage system architecture)

[0063] Figure 1A This is a block diagram of an information processing system 100 including the storage system 1 described in the embodiments. The information processing system 100 includes the storage system 1 and the host device 2. The storage system 1 described in the embodiments is configured, for example, as a solid-state hard disk drive (SSD). The host device 2 can be, for example, a computer with an interface including SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), or PCIe (PCI Express) (registered trademark).

[0064] like Figure 1A As shown, the storage system 1 includes multiple non-volatile memories 3, volatile memories 110, and a storage controller 20.

[0065] The non-volatile memory 3 is a non-volatile memory capable of storing data in a non-volatile manner. The non-volatile memory 3 is not limited to NAND flash memory; NOR flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), and ferroelectric random access memory (FeRAM) can also be used. Furthermore, magnetic tunnel junction (MTJ) resistive switching elements can also be used as non-volatile memory 3. Multiple non-volatile memories 3 can operate independently. The number of non-volatile memories 3 is arbitrary. Multiple non-volatile memories 3 and the storage controller 20 are connected via multiple channels.

[0066] Volatile memory 110 is a volatile memory capable of temporarily storing data. Volatile memory 110 may be, for example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). The number of volatile memories 110 is arbitrary.

[0067] The storage controller 20 is, for example, an IC such as a SoC, FPGA, or ASIC. The storage controller 20 is capable of performing various operations on the non-volatile memory 3 and the volatile memory 110. Furthermore, the storage controller 20 can perform operations based on requests from the external host device 2 and operations independent of requests from the host device 2.

[0068] Next, the detailed structure of the non-volatile memory 3 will be explained.

[0069] Figure 1B yes Figure 1A The block diagram shown illustrates the non-volatile memory 3 included in the storage system 1. The non-volatile memory 3 comprises multiple dies 10_1, 10_2, ..., 10_16. Figure 1B An example with 16 dies (i.e., die 10_1, die 10_2, ..., die 10_16) is shown. For example, die 10_1 has a memory cell array 11_1 and a temperature sensor 25_1. Similarly, die 10_2 has a memory cell array 11_2 and a temperature sensor 25_2. In addition, die 10_16 has a memory cell array 11_16 and a temperature sensor 25_16. Sometimes, the multiple dies 10_1 to 10_16 are collectively referred to as die 10. Sometimes, the multiple memory cell arrays 11_1, 11_2, ..., 11_16 are collectively referred to as memory cell array 11. Sometimes, the multiple temperature sensors 25_1, 25_2, ..., 25_16 are collectively referred to as temperature sensor 25.

[0070] Temperature sensor 25 measures the temperature within the die 10 on which it is mounted. For example, temperature sensor 25_1 measures the temperature at the location where it is mounted. Temperature sensor 25_1 measures the overall temperature of the die 10_1 and the temperature of the memory cell array 11_1 of the die 10_1. The measured temperature is referenced by CPU 21, for example, during temperature control processing.

[0071] Next, the detailed structure of the storage controller 20 will be described.

[0072] Figure 1C yes Figure 1AThe block diagram shown is of the storage controller 20 included in the storage system 1. (As shown...) Figure 1C As shown, the storage controller 20 includes a CPU (Central Processing Unit) 21, a built-in memory (RAM: RandomAccess Memory) 22, a host I / F circuit 23, a clock control unit 24, a NAND I / F circuit 26, and a volatile memory I / F circuit 27.

[0073] CPU 21 can control the overall operation of the storage controller 20 by executing firmware. For example, CPU 21 responds to read requests received from host device 2 and issues read commands. CPU 21 sends the issued commands to NAND I / F circuit 26. In addition, CPU 21 can perform temperature control processing for non-volatile memory.

[0074] Built-in memory 22 is used as the working area of ​​CPU 21. Built-in memory 22 can be, for example, volatile memory such as SRAM (Static Random Access Memory). Built-in memory 22 contains, for example, parameters and various management tables for managing non-volatile memory 3. For example, built-in memory 22 stores a wait queue for commands issued to non-volatile memory 3. Additionally, built-in memory 22 stores an address translation table (LUT) for translating logical addresses associated with data stored in block BLK of non-volatile memory 3 into physical block addresses (PBAs) of block BLK. The address translation table is stored, for example, in non-volatile memory 3. The address translation table is read and loaded into built-in memory 22 when memory system 1 is started.

[0075] The host I / F circuit 23 is the hardware interface responsible for communication between the storage system 1 and the host device 2. The host I / F circuit 23 supports communication interface standards such as SATA, SAS, and PCIe (registered trademark). For example, the host I / F circuit 23 controls the transmission of data, commands, and addresses between the storage system 1 and the host device 2. The host I / F circuit 23 is connected to the host device 2.

[0076] The clock control unit 24 generates clocks that enable the CPU 21, host I / F circuit 23, NAND I / F circuit 26, volatile memory I / F circuit 27, and non-volatile memory 3 of the memory controller 20 to operate. Furthermore, the clock control unit 24 provides the generated clocks to the CPU 21, host I / F circuit 23, NAND I / F circuit 26, volatile memory I / F circuit 27, and non-volatile memory 3.

[0077] The NAND I / F circuit 26 is connected to multiple non-volatile memories 3. The NAND I / F circuit 26 is the hardware interface responsible for communication between the memory controller 20 and the non-volatile memories 3.

[0078] The volatile memory I / F circuit 27 is connected to the volatile memory 110. The volatile memory I / F circuit 27 is the hardware interface responsible for communication between the memory controller 20 and the volatile memory 110. The volatile memory I / F circuit 27 is constructed based on the volatile memory interface standard. Furthermore, the structure of the volatile memory I / F circuit 27 can be changed based on the type of volatile memory in the memory system 1.

[0079] The structure of the memory controller 20 described above is an example. The clock control unit 24 can also be externally connected to the memory controller 20.

[0080] (Structure of a bare film)

[0081] Next, the detailed structure of die 10_1, one of the multiple dies 10 included in the non-volatile memory 3, will be described.

[0082] Figure 2 This is a block diagram of the bare die 10_1 in the implementation method. For example... Figure 2 As shown, the die 10-1 includes a memory cell array 11-1, a sensing amplifier module 12, a row decoder module 13, an input / output circuit 14, a register 15, a logic controller 16, a sequencer 17, a ready / busy control circuit 18, a voltage generation circuit 19, and a temperature sensor 25-1.

[0083] The storage cell array 11_1 includes multiple block BLKs. A block BLK is a collection of multiple non-volatile storage cells associated with bit lines and word lines. A block BLK serves as, for example, a data erasure unit. Block BLKs can, for example, employ an MLC (Multi-Level Cell) method. According to the MLC method, each storage cell can store more than 2 bits of data. Alternatively, block BLKs can employ a TLC (Triple-Level Cell) method or a QLC (Quad-Level Cell) method. Through TLC and QLC methods, each storage cell can store more than 3 bits of data.

[0084] The sense amplifier module 12 can output the data DAT read from the memory cell array 11_1 to the memory controller 20 via the input / output circuit 14. In addition, the sense amplifier module 12 can transmit the write data DAT received from the memory controller 20 via the input / output circuit 14 to the memory cell array 11_1.

[0085] The row decoder module 13 can select the block BLK of the object performing various actions based on the block address held in the address register 15B. Furthermore, the row decoder module 13 can transmit the voltage supplied from the voltage generation circuit 19 to the selected block BLK.

[0086] The input / output circuit 14 is capable of transmitting and receiving 8-bit wide input / output signals (I / O1 to I / O8) with the memory controller 20. For example, the input / output circuit 14 transmits the write data DAT contained in the input / output signal I / O received from the memory controller 20 to the sense amplifier module 12. The input / output circuit 14 also sends the read data DAT transmitted from the sense amplifier module 12 as an input / output signal I / O to the memory controller 20.

[0087] Register 15 includes a status register 15A, an address register 15B, and a command register 15C. Status register 15A, for example, holds the status information STS of sequencer 17. Status register 15A transmits the status information STS to input / output circuit 14 based on the indication from sequencer 17. Address register 15B holds the address information ADD transmitted from input / output circuit 14. For example, the column address and block address contained in the address information ADD are used in sense amplifier module 12 and row decoder module 13, respectively. Command register 15C holds the command CMD transmitted from input / output circuit 14.

[0088] The logic controller 16 can control the input / output circuit 14 and the sequencer 17 based on various control signals received from the memory controller 20. These various control signals include, for example, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, and the write protection signal WPn. The signal CEn is used to enable the die 10_1. The signal CLE is used to notify the input / output circuit 14 that the signal input to the die 10_1 is a command (CMD). The signal ALE is used to notify the input / output circuit 14 that the signal input to the die 10_1 is an address (ADD). The signals WEn and REn are used, for example, to command the input / output circuit 14 to perform input and output of input / output signal I / O, respectively. The signal WPn is used, for example, to put the die 10_1 into a protected state when the power is turned on or off.

[0089] The sequencer 17 can control the overall operation of the die 10_1 based on the command CMD held in the command register 15C. For example, the sequencer 17 controls the sense amplifier module 12, the line decoder module 13, the voltage generation circuit 19, etc., to perform various operations such as write operations and read operations.

[0090] The ready / busy control circuit 18 can generate a ready / busy signal RBn based on the operating state of the sequencer 17. The signal RBn is a signal whose value is determined based on whether the die 10_1 is in a ready state that accepts commands from the memory controller 20 or in a busy state that does not accept commands.

[0091] The voltage generation circuit 19 generates the desired voltage based on the control of the sequencer 17. The voltage generation circuit 19 can supply the generated voltage to the memory cell array 11_1, the sense amplifier module 12, the row decoder module 13, etc. For example, the voltage generation circuit 19 applies the desired voltage to the select word lines and non-select word lines based on the page address held in the address register 15B.

[0092] Temperature sensor 25_1 measures the temperature of the bare die 10_1 on which temperature sensor 25_1 is installed. The measured temperature is used as a signal TMP by the storage controller 20 during temperature control processing.

[0093] (Planar structure of memory cell array)

[0094] Next, an example of the planar structure of the memory cell array 11 included in the non-volatile memory 3 will be described.

[0095] Figure 3This is a block diagram of the planar structure of the storage cell array 11_1 according to the implementation method. Figure 3 An example is shown where the memory cell array 11_1 included in die 10_1 is divided into multiple planes (subarrays).

[0096] Storage cell array 11_1 has multiple planes. Each plane has a subarray. Each subarray has multiple block BLKs.

[0097] Figure 4 It means Figure 3 A block diagram showing the structure of the memory blocks included in the memory cell array 11_1. Figure 4 Examples Figure 3 The example shown illustrates the structure of a block BLK. A block BLK contains multiple pages.

[0098] (Block structure)

[0099] Next, an example of the circuit structure of the block BLK included in the non-volatile memory 3 will be described. Figure 5 This is a circuit diagram of the blocks involved in the implementation method. Figure 5 The detailed circuit structure of a block BLK within the memory cell array 11 is illustrated. For example... Figure 5 As shown, a block BLK includes, for example, four string units SU (SU0 to SU3).

[0100] Each string unit SU includes multiple NAND strings NS that are associated with bit lines BL0 to BLm (where m is a natural number). Bit lines BL0 to BLm are shared among multiple blocks BLK.

[0101] Each NAND string NS includes, for example, multiple memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The multiple memory cell transistors MT are each capable of storing data in a non-volatile manner. Select transistors ST1 and ST2 are used to select the string cell SU. In each NAND string NS, the multiple memory cell transistors MT (MT0 to MT7) are connected in series between the source of select transistor ST1 and the drain of select transistor ST2.

[0102] As described above, select transistors ST1 and ST2 are each contained within multiple NAND strings NS of the string unit SU. The drains of the multiple select transistors ST1 are each connected to one of the bit lines BL0 to BLm. The gates of the multiple select transistors ST1 are each connected to one of the select gate lines SGD0 to SGD3. The sources of the multiple select transistors ST2 are shared by a single source line SL within a block BLK. Furthermore, the source line SL is shared among the multiple blocks BLK. Additionally, the gates of the multiple select transistors ST2 are shared by a single select gate line SGS.

[0103] Furthermore, the number of string cells (SU) in each BLK and the number of memory cell transistors (MT) and select transistors (ST1 and ST2) in each NAND string (NS) are examples and can be designed to be any number. The number of word lines (WL) and select gate lines (SGD and SGS) is varied based on the number of memory cell transistors (MT) and select transistors (ST1 and ST2).

[0104] (Temperature control of the storage system involved in the implementation)

[0105] Next, the table group 80 used in the temperature control of the storage system 1 according to the embodiment will be described.

[0106] Figure 6 This is a block diagram showing the table group 80 used in the temperature control of the storage system according to the embodiment. The tables used in the temperature control of the storage system 1 according to the embodiment are IPC queue 81, NAND modeling table 82, and scheduling table 83. IPC queue 81, NAND modeling table 82, and scheduling table 83 are stored in volatile memory 110 or RAM 22 in storage controller 20.

[0107] In IPC queue 81, access commands received by storage system 1 from host device 2 are stored separately for each of the multiple dies 10. Access commands are commands used to access non-volatile memory 3. Examples of access commands include read commands (RD), program commands (PG), and erase commands (ER).

[0108] In NAND modeling table 82, the critical temperature, current temperature, and modeling information are stored separately for each of the multiple dies 10. Critical temperatures and modeling information are pre-set for each die 10. The critical temperatures and modeling information can be changed. The critical temperature refers to the upper limit of the operating temperature set for each die 10 within a predetermined temperature range. The modeling information includes the command action time required for each access command and the degree of influence of that command action time on the temperature. For example, the degree of influence of the command action time on the temperature is the command action time required to raise the temperature by 1°C.

[0109] The scheduling table 83 is a table created within the storage system 1 based on access commands stored in the IPC queue 81, limit temperatures stored in the NAND modeling table 82, the current temperature, and modeling information. The storage system 1 controls the temperature of the die 10 by executing access commands to the non-volatile memory 3 according to the scheduling table 83.

[0110] Figure 7A This is an example of the data structure for IPC queue 81. Figure 7A The example illustrates an IPC queue 81 that stores seven access commands for accessing the bare die 10_1. Additionally, Figure 7A An example is shown of an IPC queue 81 that stores more than 10 access commands for accessing the die 10-16. Access commands stored in the IPC queue 81 are executed sequentially on the non-volatile memory 3 via the NAND I / F circuit 26. Furthermore, completed access commands are removed from the IPC queue 81 in the order they were executed.

[0111] Figure 7B This is an example of a NAND modeled table 82 data structure. Figure 7B Table 82 illustrates the NAND modeling for die 10_1 with a critical temperature of 73°C and a current temperature of 69°C. Additionally, Figure 7B Table 82 illustrates the NAND modeling for die 10_2 with a critical temperature of 72°C and a current temperature of 70°C. Additionally, Figure 7B Table 82 illustrates the NAND modeling for a bare die 10-16 with a critical temperature of 73°C and a current temperature of 71°C. Additionally, Figure 7B Table 82 illustrates the NAND modeling for cases where the busy time (action time) required for each read command on die 10_1 is 0.1 ms, the busy time (command action time) required for each programming command is 1.0 ms, and the busy time (action time) required for each clear command is 5.0 ms. Additionally, Figure 7B Table 82 illustrates the NAND modeling for cases where the busy time (action time) required for each read command on die 10_2 is 0.1 ms, the busy time (command action time) required for each programming command is 1.2 ms, and the busy time (action time) required for each clear command is 5.2 ms. Additionally, Figure 7B Table 82 illustrates the NAND modeling for cases where the busy time (operation time) required for each read command on die 10-16 is 0.1 ms, the busy time (operation time) required for each programming command is 1.1 ms, and the busy time (operation time) required for each clear command is 5.1 ms. Additionally, Figure 7B Table 82 illustrates the NAND modeling for cases where the action time required to raise the temperature by 1°C is 1.5ms in die 10-1, 1.3ms in die 10-2, and 1.0ms in die 10-16.

[0112] Next, the firmware (control program) 60 used in the temperature control of the storage system 1 according to the embodiment will be described.

[0113] Figure 8 This is a block diagram illustrating an example of the functional configuration of the firmware involved in the implementation. The firmware 60 includes a scheduler 91 and a command dispatcher 92.

[0114] When the storage system 1 starts up, the CPU 21 reads the firmware (control program) 60 from the non-volatile memory 3 or the ROM (not shown) and stores it in the RAM 22. The CPU 21 then performs temperature control processing by executing the firmware 60 stored in the RAM 22. Based on the temperature control processing, the CPU 21 can also perform command processing, such as processing various commands from the host device 2. Alternatively, some or all of the temperature control processing can be performed by dedicated hardware within the storage controller 20.

[0115] The scheduler 91 acquires modeling information from the NAND modeling table 82 and access commands from the IPC queue 81. Based on the acquired modeling information and access commands, the scheduler 91 creates a scheduling table 83 (scheduling). The scheduler 91 then sends the created scheduling table 83 to the command distributor 92. Furthermore, during scheduling, the scheduler 91 performs PID (Proportional Integral Differential) control based on the current temperature stored in the NAND modeling table 82, ensuring that the individual detection values ​​of the multiple temperature sensors 25 do not exceed the limit temperature. This enables gentle rate control.

[0116] Command distributor 92 obtains temperature information from multiple temperature sensors 25. Command distributor 92 inputs the obtained temperature information as the current temperature into NAND modeling table 82. Additionally, command distributor 92 executes access commands based on the scheduling table 83 received from scheduling unit 91.

[0117] (The temperature control process of the storage system involved in the implementation)

[0118] Next, the temperature control process of the storage system 1 according to the embodiment will be described.

[0119] Figure 9 A flowchart illustrating the temperature control of the storage system 1 according to the implementation method.

[0120] When the host device 2 requests the start of temperature control (start), the command distributor 92 obtains temperature information from the temperature sensors 25 respectively set on the multiple dies 10 (S101).

[0121] Command distributor 92 inputs the acquired temperature information as the current temperature into NAND modeling table 82 (S102). Furthermore, command distributor 92 notifies scheduler 91 that the processing of S102 is complete.

[0122] When notified that processing in S102 has been completed, the scheduler 91 calculates the busy time T based on the limit temperature, the current temperature, and the modeling information stored in the NAND modeling table 82. busyDie (S103). Calculate the busy time T for each of the multiple bare films 10. busyDie For busy time T busyDie This is calculated by multiplying the action time (rise time) required to raise the temperature by 1°C by the difference between the threshold temperature and the current temperature. Figure 7B In the example, for the busy time T of bare die 10_1 busyDie The rise time (1.5 ms) × the difference between the threshold temperature and the current temperature (4 °C) = 6.0 ms. Similarly, the busy time T for a 10-2 die... busyDie The rise time becomes the difference between the threshold temperature and the current temperature (2°C) of 1.3 ms. Similarly, the busy time T for a 10-16 die is... busyDie The rise time (1.0 ms) × the difference between the threshold temperature and the current temperature (2 °C) = 2.0 ms.

[0123] The scheduler 91 calculates the required time T for each of the multiple dies 10 based on the access commands for each die 10 stored in the IPC queue 81. ipcReq (S104). In Figure 7A The example illustrates IPC queue 81 with 5 read commands (RD), 1 program command (PG), and 1 clear command (ER). Additionally, in... Figure 7B Table 82 illustrates the NAND modeling for a bare die 10_1, showing that the time required to execute a read command (RD) is 0.1 ms, the time required to execute a program command (PG) is 1.0 ms, and the time required to execute a clear command (ER) is 5.0 ms. Therefore, the required time T... ipcReqThe time required to execute a read command (RD) × number of read commands (RD) + time required to execute a program command (PG) × number of program commands (PG) + time required to execute a clear command (ER) × number of clear commands (ER) = 0.1ms × 5 + 1.0ms × 1 + 5.0ms + 1 = 6.5ms.

[0124] Scheduler 91 determines the required time T calculated in S104. ipcReq Is it the busy time T calculated in S103? busyDie The above (S105).

[0125] The required time T calculated in S104 ipcReq The busy time T calculated in S103 busyDie In the above case (S105: Yes), the scheduler 91 weights the access commands of the IPC queue 81 to create a scheduling table 83 (S106). That is, the scheduler 91 creates the scheduling table 83 to ensure that the temperature of each die 10 does not exceed the limit temperature. Furthermore, the scheduler 91 notifies the command distributor 92 that the processing in S106 is complete.

[0126] When notified that the processing in S106 is complete, the command distributor 92 executes the access command (S110) according to the arrangement schedule table 83 created by the scheduler 91 in step S106. Furthermore, the command distributor 92 notifies the scheduler 91 that the processing in S110 is complete.

[0127] The required time T calculated in S104 ipcReq Not the busy time T calculated in S103 busyDie In the above case (S105: No), the scheduler 91 creates a scheduling table 83 to execute all access commands (S107).

[0128] Furthermore, scheduler 91 determines whether time T is required. ipcReq Less than busy time T busyDie Furthermore, a new access command was added to IPC queue 81 (S108).

[0129] At the required time T ipcReq Less than busy time T busyDie If a new access command is added to the IPC queue 81 (S108: Yes), the scheduler 91 adds the new access command to the scheduling table 83 in step S109 (S109). Furthermore, the scheduler 91 notifies the command distributor 92 that the processing in S109 is complete.

[0130] When notified that the processing in S109 is complete, the command distributor 92 executes the access command (S110) according to the arrangement schedule table 83 created by the scheduler 91 in steps S107 and S109. Furthermore, the command distributor 92 notifies the scheduler 91 that the processing in S110 is complete.

[0131] At the required time T ipcReq Not less than busy time T busyDie In the event that and / or no new request is added to the IPC queue 81 (S108: No), the scheduler 91 notifies the command distributor 92 that the processing of S108 has been completed.

[0132] When notified that the processing in S108 is complete, the command distributor 92 executes the access command (S110) according to the arrangement schedule table 83 created by the scheduler 91 in step S107. Furthermore, the command distributor 92 notifies the scheduler 91 that the processing in S110 is complete.

[0133] When notified that processing by S110 is complete, the scheduler 91 determines whether the adjustment parameter ProcMin is set (S111). The adjustment parameter ProcMin is a setting value for the standby time inserted between access commands executed for the die 10.

[0134] With the adjustment parameter ProcMin set (S111: Yes), scheduler 91 inserts standby time between access commands executed for die 10. Scheduler 91 then schedules the time during the inserted standby period (t...). breakPoint (S112) The access command is not executed. That is, after a time set as the standby time has elapsed since the processing corresponding to an access command was completed, the storage controller 20 sends a response corresponding to the access command to the host device 2. The longer the standby time, the greater the suppression of the performance of the storage system 1.

[0135] If the adjustment parameter ProcMin is not set (S111: No), scheduler 91 notifies command distributor 92 that the adjustment parameter ProcMin is not set (S113: No).

[0136] When the scheduler 91 notifies that the adjustment parameter ProcMin has not been set, the command distributor 92 determines whether the host device 2 has requested the end of the temperature control of the storage system 1 (S114).

[0137] Alternatively, when the scheduler 91 notifies that the processing of S112 has been completed, it is determined whether the host device 2 has requested the end of the temperature control of the storage system 1 (S114).

[0138] If the host device 2 is notified from the host device 2 that the power supply to the host device 2 has been disconnected (S114: Yes), the command distributor 92 ends a series of processes (end).

[0139] If the host device 2 is not notified from the host device 2 that the power supply to the host device 2 has been turned off (S114: No), the command distributor 92 performs the processing of S101.

[0140] Figure 10 This is a schematic diagram showing the scheduling table 83 used in the temperature control of the storage system 1 according to the embodiment. Additionally, Figure 11 A schematic diagram showing the weighted table used in the temperature control of the storage system 1 according to the embodiment. Figure 11 The weighted table is illustrated in the following case: the weight of the read command is 1, the weight of the programming command is 100, and the weight of the clear command is 500. Imagine scheduling the time T of the read command action by scheduler 91 in this case. busyRead Programming command action time T busyProg Clear command action time T busyErase Distribute equally (T) busyRead :T busyProg :T busyErase When the ratio is 1:1:1, scheduler 91 is arranged as follows: Figure 10 The scheduling table 83 is set up as illustrated, such that for 1000 read commands, the number of programming commands is 10 and the number of clear commands is 2.

[0141] In addition, the read command action time T busyRead Programming command action time T busyProg And the clear command action time T busyErase The ratio (T) busyRead :T busyProg :T busyErase It can be adjusted based on the state of the driver for the non-volatile memory 3 and the requirements of the driver. Additionally, the ratio T... busyRead :T busyProg :T busyErase It can also be adjusted dynamically. The dynamic contrast ratio T busyRead :T busyProg :T busyErase Making adjustments means adjusting the system at a predetermined timing ratio T during the operation of storage system 1. busyRead :T busyProg :T busyErase The value is adjusted. The predetermined timing, for example, refers to the timing of the temperature control process cycle.

[0142] Figure 12This is a schematic diagram showing the timing of the temperature control operation of each die 10 in the storage system according to the embodiment.

[0143] The storage system described in this embodiment dynamically changes the limit temperature of the die 10. Dynamically adjusting the limit temperature means adjusting the value of the limit temperature within a predetermined temperature range at predetermined time intervals during operation of the storage system 1. The predetermined time interval, for example, refers to the timing of a cycle in the temperature control process. Figure 12 As shown, for the die 10_1 that performs temperature control at time T1, the limit temperature is set to a value L1 that is close to the lower limit of the operating temperature. Additionally, for example... Figure 12 As shown, for die 10_2, which performs temperature control at time T2, the limit temperature is set to a value L2 that is close to the upper limit of the operating temperature. Similarly, for die 10_3, which performs temperature control at time T3, the limit temperature is set to a value L3 that is close to the upper limit of the operating temperature. Furthermore, for die 10_(n-1), which performs temperature control at time Tn-1, the limit temperature is set to a value L(n-1) that is close to the upper limit of the operating temperature. Finally, for die 10_n, which performs temperature control at time Tn, the limit temperature is set to a value Ln that is close to the lower limit of the operating temperature.

[0144] Furthermore, the storage system described in this embodiment uses a temperature-controlled cycle to vary the timing of the operation of each of the dies 10. For example, Figure 12 As shown, regarding die 10_1, which operates at time T1 in the first loop, it operates at time Tn in the second loop. Regarding die 10_1 performing temperature control at time Tn, the limit temperature is set to a value Ln close to the lower limit of the operating temperature. Additionally, for example... Figure 12 As shown, regarding the die 10_2 that was activated at time T2 in the first cycle, it is activated at time T1 in the second cycle. Regarding the die 10_2 that performs temperature control at time T1, the limit temperature is set to a value L1 close to the lower limit of the temperature at which it can operate. Additionally, for example... Figure 12 As shown, for die 10_3, which was activated at time T3 in the first cycle, it was activated at time T2 in the second cycle. For die 10_3 that performs temperature control at time T2, the limit temperature is set to a value L2 that is close to the upper limit of the temperature at which it can operate.

[0145] The memory system of this embodiment provides temperature sensors for each of the multiple dies 10, thereby enabling thermal throttling of each die. Furthermore, the memory system of this embodiment can also optimize the utilization of non-volatile semiconductor memory.

[0146] The storage system described in this embodiment takes into account the required time T for each of the multiple bare dies 10. ipcReq Busy Time T busyDie Temperature control is achieved. Therefore, the load on multiple dies 10 can be distributed so that temperature control is fairly distributed across all command operations. Furthermore, the possibility of the driver becoming unresponsive for temperature control is reduced, improving responsiveness from the host device 2 perspective.

[0147] In addition, the storage system involved in this embodiment uses limit temperature, current temperature, modeling information, and busy time T. busyDie Required time T ipcReq Read command action time T busyRead Programming command action time T busyProg Clear command action time T busyErase There are many adjustable parameters, such as driver state machine. The more adjustable parameters there are, the more design options are available. These adjustable parameters can be dynamically allocated based on the driver state machine.

[0148] Furthermore, by implementing temperature control on a per-die basis (die 10), the architecture of host devices 2, such as IOD (I / O Die), is also effective.

[0149] Thus, according to the storage system of this embodiment, temperature rise can be suppressed and performance and reliability can be improved through die-level temperature control of the non-volatile semiconductor memory.

[0150] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system comprising: a nonvolatile semiconductor memory having a plurality of dies; a temperature sensor provided for each of the dies; and a storage controller that controls the nonvolatile semiconductor memory and the temperature sensor, the temperature sensor measures a temperature of the die, the storage controller manages a limit temperature that is different for each of the plurality of dies, the storage controller, for each of the dies, performs scheduling of an access command for accessing the nonvolatile semiconductor memory based on the temperature, the limit temperature, and the access command.

2. The storage system according to claim 1, the storage controller comprises a command distributor and a scheduling scheduler, the command distributor acquires the temperature, stores the acquired temperature and the limit temperature in association with each of the dies in a modeling table, the scheduling scheduler creates a scheduling table based on the modeling table and the access command, the command distributor performs an operation of the access command for the nonvolatile semiconductor memory in accordance with the scheduling table created by the scheduling scheduler.

3. The storage system according to claim 2, the modeling table includes a command operation time and an influence degree, the influence degree is a command operation time required to raise the temperature of the die by a predetermined temperature, the scheduling scheduler creates the scheduling table based on the temperature and the limit temperature, and further based on the command operation time and the influence degree included in the modeling table for each of the dies.

4. The storage system according to claim 3, the scheduling scheduler, for each of the dies, calculates a busy time and a required time based on the temperature, the limit temperature, the command operation time, the influence degree, and the access command, the busy time is calculated by multiplying the influence degree by a difference between the limit temperature and the temperature, the required time is calculated by multiplying the command operation time by a number of the access commands, in a case where the calculated required time is smaller than the busy time, the scheduling table is created so that all of the access commands are executed.

5. The storage system according to claim 3, the scheduling scheduler, for each of the dies, calculates a busy time and a required time based on the temperature, the limit temperature, the command operation time, the influence degree, and the access command, the busy time is calculated by multiplying the influence degree by a difference between the limit temperature and the temperature, the required time is calculated by multiplying the command operation time by a number of the access commands, in a case where the calculated required time is the busy time or more, weighting of the access commands is performed to create the scheduling table so that the temperature of the die does not exceed the limit temperature.

6. The storage system according to claim 5, the scheduling scheduler, when performing the weighting of the access commands, adjusts a weight for each of the access commands according to a length of the command operation time determined in advance for each of the dies.

7. The storage system according to claim 6, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The schedule scheduler makes the schedule table according to the ratio of the command action time predetermined for each of the dies.

8. The storage system according to claim 7, The schedule scheduler adjusts the value of the ratio of the command action time at a predetermined timing during the storage system action.

9. The storage system according to claim 8, The predetermined timing is the timing of the cycle of the temperature control processing for the plurality of dies.

10. The storage system according to claim 2, The schedule scheduler adjusts the value of the limit temperature at a predetermined timing during the storage system action within the temperature range in which each of the dies can act.

11. The storage system according to claim 10, The predetermined timing is the timing of the cycle of the temperature control processing for the plurality of dies.

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