Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: providing a substrate, the substrate comprising a base and a fin located on the surface of the base, forming a gate structure spanning the fin and covering part of the top surface and sidewall of the fin, the gate structure comprising a gate layer, using the gate structure as a mask, forming a first trench in the fin between parts of adjacent gate structures, filling the first trench with an isolation material layer to form a first isolation structure, the size of the patterned layer when forming the first trench is relatively large, thereby increasing the process window of the patterning process, so that self-alignment can be achieved to form a double diffusion isolation structure, reducing the requirements for the photolithography process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the existing semiconductor field, the fin field effect transistor (FinFET) is an emerging multi-gate device. Compared with the planar metal-oxide semiconductor field effect transistor (MOSFET), the fin field effect transistor has stronger short channel suppression capability and stronger operating current, and is now widely used in various semiconductor devices.

[0003] With the continuous development of semiconductor technology, increasing the density of chip devices has become an inevitable trend. In order to make smaller and more densely distributed fins, the existing technology introduces partition technology, forming one or more partition grooves along the length of the fins, and then filling these grooves with insulating materials such as silicon oxide through processes such as thermal oxidation to divide the fins into multiple small fins, thereby manufacturing smaller fin field effect transistor devices.

[0004] However, the method for forming the FinFET structure in the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base and a fin located on the surface of the base; forming a gate structure spanning the fin and covering a portion of the top surface and side wall of the fin, the gate structure including a gate layer; using the gate structure as a mask, forming a first trench in the fin between some adjacent gate structures; filling the first trench with an isolation material layer to form a first isolation structure.

[0007] Optionally, the material of the first isolation structure includes silicon oxide.

[0008] Optionally, the depth of the first trench is 1000 angstroms to 4000 angstroms.

[0009] Optionally, the method further includes: after forming the gate layer, forming an interlayer dielectric layer on the surface of the substrate, wherein the interlayer dielectric layer is also located on the sidewalls of the gate structure and exposes the top surface of the gate structure.

[0010] Optionally, the method further includes: forming a second trench in the interlayer dielectric layer and communicating with the first trench; and the first isolation structure is also located in the second trench.

[0011] Optionally, the method for forming the first isolation structure includes: forming an isolation material layer on the interlayer dielectric layer, in the second trench and in the first trench; and planarizing the isolation material layer until the surface of the interlayer dielectric layer is exposed to form the first isolation structure.

[0012] Optionally, the material of the gate layer includes silicon.

[0013] Optionally, the method further includes: before forming the interlayer dielectric and after forming the gate structure, forming source and drain regions in the substrate on both sides of the gate structure.

[0014] Optionally, the first trench is formed after forming the gate structure and before forming the source and drain regions.

[0015] Optionally, the first trench is formed after forming the source and drain regions and before forming the interlayer dielectric layer.

[0016] Optionally, the method for forming the first groove includes: forming a patterned layer on the sidewalls and surface of the substrate and the gate structure, the patterned layer exposing a portion of the fin between adjacent gate structures; etching the fin and the source and drain regions using the patterned layer as a mask to form the first groove in the fin.

[0017] Optionally, the method further includes: removing the gate layer to form a gate opening in the interlayer dielectric layer; and filling the gate opening with a gate material to form a gate.

[0018] Optionally, the material of the gate includes metal.

[0019] Optionally, the first trench is formed after forming the interlayer dielectric and before forming the gate.

[0020] Optionally, the method for forming the first trench and the second trench includes: forming a patterned layer on the interlayer dielectric layer, the patterned layer exposing the interlayer dielectric layer between at least two adjacent gate structures; using the patterned layer and the gate structure as masks, etching the interlayer dielectric layer, the source and drain regions, and the fins to form the first trench and the second trench.

[0021] Optionally, after forming the gate, the first trench is formed.

[0022] Optionally, the method for forming the first groove also includes: forming a patterned layer on the interlayer dielectric layer, the patterned layer exposing the interlayer dielectric layer between at least two adjacent gates; using the patterned layer and the gate as masks, etching the interlayer dielectric layer, source and drain regions and part of the substrate to form the first groove and the second groove.

[0023] Optionally, the method further includes: forming a second isolation structure in the fin, wherein the second isolation structure is located in the fin below a portion of the gate layer.

[0024] Optionally, the method for forming the second isolation structure includes: removing at least one of the gate layers to form a third trench in the interlayer dielectric layer; etching a portion of the fin at the bottom of the third trench to form a fourth trench in the fin; and filling the fourth trench with an isolation material layer to form a second isolation structure.

[0025] Optionally, the material of the second isolation structure includes silicon oxide.

[0026] Optionally, the process of forming the third trench includes one of a dry etching process and a wet etching process, or a combination of the two.

[0027] Optionally, the fourth trench is formed after the first trench is formed and before the first isolation structure is formed; the method for forming the second isolation structure also includes: filling a protective layer in the first trench and the second trench; after forming the fourth trench, removing the protective layer; and filling an isolation material layer in the fourth trench while forming the first isolation structure to form a second isolation structure.

[0028] Optionally, the second isolation structure is also located in the third trench.

[0029] Optionally, the material of the protection layer includes a bottom anti-reflection layer material.

[0030] Optionally, the substrate surface further has a third isolation structure covering a portion of the sidewalls of the fin, the top surface of the third isolation structure is lower than the top surface of the fin, and the gate structure is located on the third isolation structure.

[0031] Optionally, the material of the third isolation structure includes silicon oxide.

[0032] Optionally, the gate structure further includes: sidewalls located on the top surface and side walls of the gate layer.

[0033] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0034] In the method for forming a semiconductor structure provided by the technical solution of the present invention, after forming a gate structure, a first trench is formed in the fin portion between some adjacent gate structures using the gate structure as a mask, and an isolation material layer is filled in the first trench to form a first isolation structure. The first trench is formed using the gate structure as a mask, so the size of the patterned layer when forming the first trench is larger, thereby increasing the process window of the patterning process, achieving self-alignment to form a double diffusion isolation structure, and reducing the requirements for the photolithography process.

[0035] Furthermore, since the first isolation structure and the second isolation structure are formed on the same substrate, and the first isolation structure is a double-diffusion isolation structure, the double-diffusion isolation structure has better isolation performance between the formed devices, and the second isolation structure is a single-diffusion isolation structure, the single-diffusion isolation structure can reduce the unit size of the chip. Therefore, one or two isolation structures can be selected as isolation devices according to the design requirements of the device, thereby improving the electrical performance of the device and obtaining a unit device of a reasonable size. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 to Figure 2 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0037] Figures 3 to 9 It is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0038] Figures 10 to 13 It is a schematic cross-sectional structure diagram corresponding to each step in a semiconductor structure forming method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0039] As described in the background art, the method for forming a FinFET structure in the prior art needs to be improved.

[0040] Figure 1 to Figure 2 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0041] Please refer to Figure 1 , providing a substrate 100, the substrate 100 comprising: a base 101, and a fin 102 located on the surface of the base; forming a hard mask material layer 103 on the surface of the substrate 100 and the sidewalls and surface of the fin 102, and forming a patterned photoresist layer 104 on the hard mask material layer 103.

[0042] Please refer to Figure 2, the hard mask material layer 103 is etched with the photoresist layer 104 to form a hard mask layer 105, the hard mask layer 105 partially exposes the surface of the fin 102, and the fin 102 is etched with the hard mask layer 105 as a mask to form a partition groove (not marked in the figure); the partition groove is filled with an insulating medium such as silicon oxide, silicon nitride, etc. to form a partition structure 106.

[0043] The above method is used in the fin isolation structure of the FinFET. The partition structure 106 is formed after the fin is formed and before the dummy gate structure is formed. According to the position of the partition, there are double diffusion break (DDB) and single diffusion break (SDB) technologies. The groove of the double diffusion break is located between two dummy gates, while the double diffusion break is located in the middle of the dummy gate. As the size of the device continues to shrink, the precision requirements for the photolithography process are getting higher and higher. Affected by the accuracy of the etching process, the size of the photoresist layer 104 pattern will change when it is transferred to the fin 102, thereby affecting the size of the partition groove, affecting the performance of the isolation structure 106, and ultimately affecting the device performance of the FinFET.

[0044] The present invention provides a method for forming a semiconductor structure. After forming a gate structure, the gate structure is used as a mask to form a first trench in the fin between some adjacent gate structures, and an isolation material layer is filled in the first trench to form a first isolation structure. The first trench is formed using the gate structure as a mask, so the size of the patterned layer when forming the first trench is relatively large, thereby increasing the process window of the patterning process, achieving self-alignment to form a double diffusion isolation structure, and reducing the requirements for the photolithography process.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figures 3 to 9 It is a schematic cross-sectional structure diagram corresponding to each step in a semiconductor structure forming method according to an embodiment of the present invention.

[0047] Please refer to Figure 3 , providing a substrate 200, wherein the substrate 200 includes a base 201 and a fin 202 on a surface of the base.

[0048] In this embodiment, the surface of the substrate 201 also has a third isolation structure 203 covering part of the sidewall of the fin 202, and the top surface of the third isolation structure 203 is lower than the top surface of the fin 202; subsequently, a gate structure is formed across the fin 202, and the gate structure is located on the third isolation structure 203. The third isolation structure 203 is used to achieve electrical insulation between different semiconductor devices.

[0049] The substrate 201 and the fin 202 are made of silicon.

[0050] Please refer to Figure 4 , forming a gate structure 204 that spans across the fin 202 and covers a portion of the top surface and sidewalls of the fin 202 , wherein the gate structure 204 includes a gate layer 205 .

[0051] In this embodiment, the gate structure 204 further includes: a sidewall 206 located on the sidewall surface of the gate layer 205. The sidewall 206 is used to locate the position of the first isolation structure and the source and drain regions in subsequent device manufacturing.

[0052] The material of the sidewall spacer 206 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon nitride. In this embodiment, the material of the sidewall spacer 206 is silicon nitride.

[0053] The method for forming the sidewall spacer 206 includes: forming a first sidewall spacer material layer on the surface of the substrate 200 , the surface and sidewall of the gate layer 205 , and etching the first sidewall spacer material layer until the surface of the substrate 200 is exposed.

[0054] The material of the gate layer 205 includes silicon. In this embodiment, the material of the gate layer 205 is polysilicon.

[0055] In one embodiment, the gate structure is directly used to form a transistor.

[0056] In yet another embodiment, the gate structure is used as a dummy gate, and the gate layer is subsequently replaced by a gate made of a metal material.

[0057] Subsequently, the gate structure is used as a mask to form a first trench in the fin portion between some adjacent gate structures. In this embodiment, the formation process of the first trench is as follows: Figures 5 to 7 shown.

[0058] Please refer to Figure 5 , source and drain regions 207 are formed in the fin 202 on both sides of the gate structure 204 .

[0059] The formation process of the source / drain region 207 includes an epitaxial growth process.

[0060] The source and drain regions 207 have doping ions, and the type of doping ions and the material of the source and drain regions are related to the transistor type. In this embodiment, the material of the source and drain regions 207 includes silicon carbide, and the doping ions are N-type ions. In other embodiments, the material of the source and drain regions includes silicon germanium, and the source and drain regions have doping ions, and the doping ions are P-type ions.

[0061] The process of introducing doping ions into the source / drain region 207 includes one or both of in-situ doping and ion implantation. In this embodiment, the doping ions into the source / drain region 207 are introduced by an ion implantation process.

[0062] Please refer to Figure 6 After the gate layer is formed, an interlayer dielectric layer 208 is formed on the surface of the substrate 200 . The interlayer dielectric layer 208 is also located on the sidewalls of the gate structure 204 and exposes the top surface of the gate structure 204 .

[0063] In this embodiment, the interlayer dielectric layer 208 is also located on the surface of the source and drain regions 207 and the third isolation structure 203 .

[0064] The interlayer dielectric layer 208 is used to isolate metal interconnects from devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field effect transistors when metal crosses different regions.

[0065] The material of the interlayer dielectric layer 208 includes silicon oxide.

[0066] In this embodiment, the method for forming the interlayer dielectric layer 208 includes: using a chemical vapor deposition process to form a dielectric material layer on the surface of the substrate 200, the surface of the source and drain region 207, the surface of the third isolation structure 203 and the surface of the gate structure 204; and using a chemical mechanical polishing process to flatten the dielectric material layer until the top surface of the gate structure 204 is exposed.

[0067] Please refer to Figure 7 , using the gate structure 204 as a mask, a first trench 209 is formed in the fin 202 between portions of adjacent gate structures 204 .

[0068] This embodiment further includes: forming a second trench 210 in the interlayer dielectric layer 208 that is connected to the first trench 209 .

[0069] The first trench has a depth of 1000 angstroms to 4000 angstroms.

[0070] The method for forming the first groove 209 and the second groove 210 includes: forming a patterned layer (not marked) on the interlayer dielectric layer 208, wherein the patterned layer exposes the interlayer dielectric layer between at least two adjacent gate structures 204; using the patterned layer and the gate structure 204 as masks, etching the interlayer dielectric layer 208, the source and drain regions 207 and the fin 202 to form the first groove 209 and the second groove 210.

[0071] In this embodiment, the process further includes: etching the substrate 201 below the fin 202 , and a portion of the first trench 209 is also located in the substrate 201 .

[0072] The process of forming the first groove 209 and the second groove 210 includes a dry etching process, and the parameters of the dry etching process include: the gases used include CF4, HBr, O2, and Cl2, wherein the flow rate of CF4 is 30 standard ml / min to 80 standard ml / min, the flow rate of HBr is 10 standard ml / min to 300 standard ml / min, the flow rate of O2 is 30 standard ml / min to 80 standard ml / min, and the flow rate of Cl2 is 50 standard ml / min to 3000 standard ml / min.

[0073] Using the gate structure 204 as a mask, the first groove is formed in the fin between some adjacent gate structures 204. The size of the patterning layer when forming the first groove is relatively large, thereby increasing the process window of the patterning process, and self-aligning the formation of the first groove can be achieved, reducing the requirements for the photolithography process.

[0074] In this embodiment, an isolation material layer is subsequently filled in the first trench 209 to form a first isolation structure. After the first isolation structure is formed, the gate layer 205 is removed, a gate opening is formed in the interlayer dielectric layer 208, and a gate material is filled in the gate opening to form a gate.

[0075] In another embodiment, the first trench is formed after the gate structure is formed and before the source and drain regions are formed; or the first trench is formed after the source and drain regions are formed and before the interlayer dielectric layer is formed. The method for forming the first trench includes: forming a patterned layer on the sidewalls and surface of the substrate and the gate structure, wherein the patterned layer exposes a portion of the fin between adjacent gate structures; etching the fin and the source and drain regions using the patterned layer as a mask to form the first trench in the fin.

[0076] In other embodiments, the first trench is formed after the interlayer dielectric layer is formed and before the gate is formed. The method for forming the first trench includes: forming a patterned layer on the interlayer dielectric layer, wherein the patterned layer exposes the interlayer dielectric layer between at least two adjacent gate structures; using the patterned layer and the gate structure as masks, etching the interlayer dielectric layer, the source and drain regions, and the fin to form the first trench and the second trench.

[0077] Alternatively, the first trench is formed after the gate is formed. The method for forming the first trench further includes: removing the source and drain regions at the etched position, and the method for forming the first trench further includes: forming a patterned layer on the interlayer dielectric layer, wherein the patterned layer exposes the interlayer dielectric layer between at least two adjacent gates; using the patterned layer and the gate as masks, etching the interlayer dielectric layer, the source and drain regions, and the fin to form the first trench and the second trench.

[0078] Please refer to Figure 8 , filling the first trench 209 with an isolation material layer to form a first isolation structure 211 .

[0079] In this embodiment, the first isolation structure 211 is also located in the second trench 210 . The method for forming the first isolation structure 211 further includes: continuously filling the second trench 210 with the isolation material layer to form the first isolation structure 211 .

[0080] The material of the first isolation structure 211 includes silicon oxide.

[0081] The process of filling the isolation material layer includes a chemical vapor deposition process.

[0082] The first isolation structure 211 is located between adjacent gate structures 204 and is a double diffusion isolation structure, which can achieve electrical isolation between different devices and has good insulation isolation performance.

[0083] Please refer to Fig. 9 After forming the first isolation structure 211 , the gate layer 205 is removed, and a gate opening (not shown in the figure) is formed in the interlayer dielectric layer 208 ; a gate material is filled in the gate opening to form a gate 212 .

[0084] The gate material includes metal.

[0085] In this embodiment, the method for forming the gate 212 further includes: planarizing the interlayer dielectric layer 208 to expose the surface of the gate layer 205. The planarization process is a mechanical chemical polishing process.

[0086] The process of removing the gate layer 205 is one of dry etching and wet etching or a combination of both.

[0087] In this embodiment, the process of removing the gate layer 205 is a wet etching process. The method of removing the gate layer 205 includes: the solution used includes tetramethylammonium hydroxide or potassium hydroxide solution, so that in the etching process of removing the gate layer 205, the gate layer 205 can have a larger etching selectivity relative to the interlayer dielectric 208, the first isolation structure 211 and the substrate 200.

[0088] The gate 212 is formed by an atomic layer deposition process, which has a good step coverage, so that the gate opening is well filled.

[0089] Figures 10 to 13 It is a schematic cross-sectional structure diagram corresponding to each step in a semiconductor structure forming method according to another embodiment of the present invention.

[0090] exist Figure 7 Based on Fig.10 , a protection layer 301 is filled in the first trench 209 and the second trench 210 .

[0091] The material of the protective layer 301 includes a bottom anti-reflection layer material. The formation process of the protective layer 301 includes a spin coating process. The bottom anti-reflection layer material can protect the first groove 209 and the second groove 210 when the second groove and the third groove are subsequently etched to form the second groove. When the protective layer 301 is removed after the third groove is formed, the first groove 209 and the second groove 210 will not be damaged and can be easily removed.

[0092] Please refer to Fig.11 , removing at least one of the gate layers 205 , forming a third trench 302 in the interlayer dielectric layer 208 , etching the fin 202 at the bottom of the second trench 302 , and forming a fourth trench 303 in the fin 202 .

[0093] In this embodiment, the process further includes: planarizing the interlayer dielectric layer 208 to expose the surface of the gate layer 205 and leaving a portion of the sidewall 206 on the sidewall of the gate layer 205. The planarization process is a mechanical chemical polishing process.

[0094] The process of removing at least one of the gate layers 205 is one of dry etching and wet etching or a combination of both.

[0095] In this embodiment, the process of removing at least one of the gate layers 205 is a wet etching process. The method of removing the gate layer 205 includes: using a solution including tetramethylammonium hydroxide or potassium hydroxide solution, so that in the etching process of removing the gate layer 205, the gate layer 205 can have a larger etching selectivity relative to the interlayer dielectric 208.

[0096] The process for forming the fourth groove 303 is a dry etching process. The parameters of the dry etching process include: the gases used include CF4, HBr, O2, and Cl2, wherein the flow rate of CF4 is 30 standard ml / min to 80 standard ml / min, the flow rate of HBr is 10 standard ml / min to 300 standard ml / min, the flow rate of O2 is 30 standard ml / min to 80 standard ml / min, and the flow rate of Cl2 is 50 standard ml / min to 3000 standard ml / min.

[0097] In this embodiment, the method for forming the fourth trench 303 further includes etching using the portion of the sidewall 206 retained on the sidewall of the gate layer 205 as a mask.

[0098] Please refer to Fig.12 After forming the fourth trench 303 , the protection layer 301 is removed, and while forming the first isolation structure 304 , an isolation material layer is filled in the fourth trench 303 to form a second isolation structure 305 .

[0099] The second isolation structure 305 is formed by filling the first trench 209 and the third trench 303 with an isolation material layer to form the first isolation structure 304 and the second isolation structure 305 respectively.

[0100] In this embodiment, the first isolation structure 304 is also located in the second trench 210, and the second isolation structure 305 is also located in the third trench 302. The method for forming the second isolation structure 305 further includes: filling the second trench 210 and the fourth trench 302 with an isolation material layer.

[0101] The material of the second isolation structure 305 includes silicon oxide.

[0102] The second isolation structure 305 is formed by a chemical vapor deposition process.

[0103] The process of removing the protective layer 301 includes a wet cleaning process. In this embodiment, water is used to remove the protective layer 301.

[0104] The first isolation structure 304 is located between adjacent gate layers 205 and is a double diffusion isolation structure, which can achieve electrical isolation between different devices and has good insulation isolation performance. The second isolation structure 305 is a single diffusion isolation structure, which can reduce the unit size of the chip. According to the design requirements of the device, two isolation structures can be selected as isolation devices, which can improve the electrical performance of the device and obtain a unit device of a reasonable size.

[0105] In this embodiment, the gate layer 205 is a dummy gate. In other embodiments, the gate structure is directly used to form a transistor. Fig.13 , remove the gate layer 205 , form a gate opening (not shown in the figure) in the interlayer dielectric layer 208 ; fill the gate opening with a gate material to form a gate 306 .

[0106] The gate 306 is made of metal.

[0107] The process of removing the gate layer 205 is one of dry etching and wet etching or a combination of both.

[0108] In this embodiment, the process of removing the gate layer 205 is a wet etching process. The method of removing the gate layer 205 includes: the solution used includes tetramethylammonium hydroxide or potassium hydroxide solution, so that in the etching process of removing the gate layer 205, the gate layer 205 can have a larger etching selectivity relative to the interlayer dielectric 208, the first isolation structure 304, the second isolation structure 305 and the substrate 200.

[0109] In this embodiment, the gate 306 is formed by an atomic layer deposition process, which has a good step coverage, so that the gate opening is well filled.

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base and a fin located on a surface of the base; forming a gate structure spanning the fin and covering a portion of a top surface and a sidewall of the fin, the gate structure comprising a gate layer; Using the gate structure as a mask, forming a first trench in the fin between portions of adjacent gate structures; An isolation material layer is filled in the first trench to form a first isolation structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first isolation structure includes silicon oxide.

3. The method for forming a semiconductor structure according to claim 1, wherein: The first trench has a depth of 1000 angstroms to 4000 angstroms.

4. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After the gate layer is formed, an interlayer dielectric layer is formed on the surface of the substrate. The interlayer dielectric layer is also located on the sidewalls of the gate structure and exposes the top surface of the gate structure.

5. The method for forming a semiconductor structure according to claim 4, wherein: Also includes: forming a second trench in the interlayer dielectric layer that is connected to the first trench; The first isolation structure is also located in the second trench.

6. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the first isolation structure includes: forming an isolation material layer on the interlayer dielectric layer, in the second trench and in the first trench; and planarizing the isolation material layer until the surface of the interlayer dielectric layer is exposed to form the first isolation structure.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate layer includes silicon.

8. The method for forming a semiconductor structure according to claim 5, wherein: Also includes: Before forming the interlayer dielectric layer and after forming the gate structure, source and drain regions are formed in the fins on both sides of the gate structure.

9. The method for forming a semiconductor structure according to claim 8, wherein: After forming the gate structure and before forming the source and drain regions, the first trench is formed.

10. The method for forming a semiconductor structure according to claim 8, wherein: After forming the source and drain regions and before forming the interlayer dielectric layer, the first trench is formed.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the first groove includes: forming a patterned layer on the sidewalls and surface of the substrate and the gate structure, wherein the patterned layer exposes a portion of the fin between adjacent gate structures; using the patterned layer as a mask, etching the fin and the source and drain regions to form the first groove in the fin.

12. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: removing the gate layer and forming a gate opening in the interlayer dielectric layer; A gate material is filled in the gate opening to form a gate.

13. The method for forming a semiconductor structure according to claim 12, wherein: The gate material includes metal.

14. The method for forming a semiconductor structure according to claim 12, wherein: After forming the interlayer dielectric layer and before forming the gate, the first trench is formed.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first trench and the second trench comprises: forming a patterned layer on the interlayer dielectric layer, wherein the patterned layer exposes the interlayer dielectric layer between at least two adjacent gate structures; using the patterned layer and the gate structure as masks, etching the interlayer dielectric layer, the source and drain regions, and the fins to form the first trench and the second trench.

16. The method for forming a semiconductor structure according to claim 12, wherein: After forming the gate, the first trench is formed.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the first groove also includes: forming a patterned layer on the interlayer dielectric layer, the patterned layer exposing the interlayer dielectric layer between at least two adjacent gates; using the patterned layer and the gate as masks, etching the interlayer dielectric layer, the source and drain regions and the fin to form the first groove and the second groove.

18. The method for forming a semiconductor structure according to claim 5, wherein: Also includes: A second isolation structure is formed in the fin, wherein the second isolation structure is located in the fin below a portion of the gate layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: The method for forming the second isolation structure includes: removing at least one of the gate layers to form a third trench in the interlayer dielectric layer; etching the fin at the bottom of the third trench to form a fourth trench in the fin; and filling the fourth trench with an isolation material layer to form a second isolation structure.

20. The method for forming a semiconductor structure according to claim 19, wherein: The material of the second isolation structure includes silicon oxide.

21. The method for forming a semiconductor structure according to claim 19, wherein: The process of forming the third trench includes one of a dry etching process and a wet etching process or a combination of the two.

22. The method for forming a semiconductor structure according to claim 21, wherein: The fourth trench is formed after the first trench is formed and before the first isolation structure is formed; The method for forming the second isolation structure also includes: filling a protective layer in the first trench and the second trench; removing the protective layer after forming the fourth trench; and filling an isolation material layer in the fourth trench while forming the first isolation structure to form a second isolation structure.

23. The method for forming a semiconductor structure according to claim 22, wherein: The second isolation structure is also located in the third trench.

24. The method for forming a semiconductor structure according to claim 22, wherein: The material of the protection layer includes a bottom anti-reflection layer material.

25. The method for forming a semiconductor structure according to claim 1, wherein: The substrate surface also has a third isolation structure covering a portion of the sidewalls of the fin, the top surface of the third isolation structure is lower than the top surface of the fin, and the gate structure is located on the third isolation structure.

26. The method for forming a semiconductor structure according to claim 25, wherein: The material of the third isolation structure includes silicon oxide.

27. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure further includes sidewalls located on the top surface and sidewalls of the gate layer.

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