A method for preparing an LDMOS device and a device

Abstract

The present invention provides a method for preparing an LDMOS device, wherein a substrate of a first type semiconductor material is provided to form a continuous polysilicon gate layer; the polysilicon gate layer is divided to divide the polysilicon gate layer into a first polysilicon gate layer corresponding to the well region and a second polysilicon gate layer corresponding to the drift region; the source and drain doping region and the first polysilicon gate layer are simultaneously heavily doped with second type semiconductor ions through a first mask, and the first type semiconductor ion heavily doped region and the second polysilicon gate layer are simultaneously heavily doped with first type semiconductor ions through a second mask. The beneficial effects of the technical solution of the present invention are: the maximum field strength and impact ionization of the channel are significantly reduced, and the hot carrier injection effect is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a preparation method and a device of an LDMOS device. Background Art

[0002] LDMOS (laterally-diffused metal-oxide semiconductor) is a semiconductor device commonly used in high-voltage power integrated circuits. High-voltage LDMOS meets the requirements of high-voltage resistance and power control, and is often used in radio frequency power circuits. The hot carrier injection effect in LDMOS devices will degrade device parameters, reduce device reliability and service life, so the hot carrier injection effect is often used as an important indicator for evaluating the service life of LDMOS devices.

[0003] In the manufacturing process of the existing LDMOS device, taking N-type LDMOS as an example, Figure 1 As shown, the polysilicon is doped by an ion implantation process performed simultaneously with the source and drain regions 108 to form an N-type doped gate 17, which causes a serious hot carrier injection effect on the LDMOS device, thereby affecting the working life of the LDMOS device. Summary of the invention

[0004] In view of the above problems existing in the prior art, a method for preparing an LDMOS device and a device for reducing the hot carrier injection effect are provided. The specific technical solution is as follows:

[0005] A method for preparing an LDMOS device, comprising the following steps:

[0006] Step S1, providing a substrate of a first-type semiconductor material, wherein the upper portion of the substrate includes a buried layer of a second-type semiconductor material, an epitaxial layer of a first-type semiconductor material is disposed on the top of the buried layer, a well region of the first-type semiconductor material is disposed on one side of the epitaxial layer, and a drift region is disposed on the other side, a field oxide layer is formed above the middle of the drift region, and both sides of the field oxide layer expose the upper surface of the drift region;

[0007] Step S2, forming a gate oxide layer that partially covers the well region on a side of the field oxide layer facing the well region;

[0008] Step S3, forming a continuous polysilicon gate layer on the upper surface of the gate oxide layer and the upper surface of the field oxide layer, so that the polysilicon gate layer covers the upper surface of the gate oxide layer and a portion of the upper surface of the field oxide layer;

[0009] Step S4, dividing the polysilicon gate layer into a first polysilicon gate layer corresponding to the well region and a second polysilicon gate layer corresponding to the drift region;

[0010] Step S5, forming sidewalls on both sides of the first polysilicon gate layer and the second polysilicon gate layer respectively;

[0011] Step S6, respectively defining source-drain doped regions on a side of the gate oxide layer facing away from the drift region and on a side of the field oxide layer facing away from the well region, and simultaneously heavily doping the source-drain doped regions and the first polysilicon gate layer with second-type semiconductor ions through a first mask; and, defining a first-type semiconductor ion heavily doped region on a side of the source-drain doped region facing away from the drift region, and simultaneously heavily doping the first-type semiconductor ion heavily doped region and the second polysilicon gate layer with first-type semiconductor ions through a second mask.

[0012] Preferably, the step S1 comprises:

[0013] Step S11, providing a substrate made of a first type semiconductor material;

[0014] Step S12, forming the buried layer on the upper part of the substrate by implanting second type semiconductor ions;

[0015] Step S13, growing the epitaxial layer on the upper surface of the buried layer;

[0016] Step S14, forming an oxide layer on the upper surface of the epitaxial layer, and etching the oxide layer to form the field oxide layer;

[0017] Step S15 , forming the well region and the drift region respectively by ion implantation, and performing annealing processes on the well region and the drift region respectively.

[0018] Preferably, in the step S2, the gate oxide layer is formed by a thermal oxidation process.

[0019] Preferably, in the step S3, the polysilicon gate layer is formed by a deposition process.

[0020] Preferably, in the step S4, a mask layer is formed by a photolithography process, and the polysilicon gate layer is etched through the mask layer to form the first polysilicon gate layer and the second polysilicon gate layer.

[0021] Preferably, the step S5 comprises the following steps:

[0022] Step S51, forming a first sidewall spacer on both sides of the first polysilicon gate layer and the second polysilicon gate layer respectively;

[0023] Step S52, forming a nitride layer on the upper surface of the epitaxial layer, the outer surface of the first sidewall, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer;

[0024] Step S53, etching and removing the nitride layer on the upper surface of the epitaxial layer, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer, retaining the nitride layer on the outer surface of the first sidewall to form a second sidewall.

[0025] Preferably, the step S6 comprises:

[0026] Step S611, forming a photoresist layer on the upper surface of the epitaxial layer, the outer surface of the second sidewall, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer;

[0027] Step S612, patterning the photoresist layer to open process windows corresponding to the source and drain doping regions and the first polysilicon gate layer;

[0028] Step S613, performing second type semiconductor ion implantation into the source / drain doping region and the first polysilicon gate layer through the photoresist layer;

[0029] Step S614, removing the photoresist layer, and performing heat treatment on the source / drain doped regions and the first polysilicon gate layer after ion implantation.

[0030] Preferably, the step S6 comprises:

[0031] Step S621, forming a photoresist layer on the upper surface of the epitaxial layer, the outer surface of the second sidewall, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer;

[0032] Step S622, patterning the photoresist layer to open a process window corresponding to the first-type semiconductor ion heavily doped region and the second polysilicon gate layer;

[0033] Step S623, performing first-type semiconductor ion implantation into the first-type semiconductor ion heavily doped region and the second polysilicon gate layer through the photoresist layer;

[0034] Step S624, removing the photoresist layer, and performing heat treatment on the first-type semiconductor ion heavily doped region and the second polysilicon gate layer after ion implantation.

[0035] Also included is an LDMOS device, which includes:

[0036] A substrate made of a first type semiconductor material;

[0037] A buried layer of a second type semiconductor material is disposed on the top of the substrate;

[0038] An epitaxial layer of a first type semiconductor material is disposed on the upper surface of the buried layer,

[0039] A well region of a first type semiconductor material is disposed on one side of the epitaxial layer, and an upper surface of the well region is flush with an upper surface of the epitaxial layer;

[0040] a drift region, disposed on a side of the epitaxial layer opposite to the well region, and an upper surface of the drift region is flush with an upper surface of the epitaxial layer;

[0041] A field oxygen layer is disposed on the upper surface of the drift region, and two sides of the field oxygen layer expose the upper surface of the drift region;

[0042] a gate oxide layer, disposed on a side of the field oxide layer facing the well region;

[0043] A first polysilicon gate layer heavily doped with second-type semiconductor ions, located on the upper surface of the gate oxide layer and corresponding to the well region;

[0044] A second polysilicon gate layer heavily doped with first-type semiconductor ions, located on the upper surface of the field oxide layer and corresponding to the drift region;

[0045] The source and drain regions heavily doped with second-type semiconductor ions are respectively located on a side of the gate oxide layer facing away from the drift region and a side of the field oxide layer facing away from the well region;

[0046] A first type semiconductor ion heavily doped region is located on a side of the gate oxide layer and the source and drain regions are facing away from the drift region.

[0047] Preferably, the first type semiconductor material is a P type semiconductor material; and the second type semiconductor material is an N type semiconductor material.

[0048] The technical solution of the present invention has the beneficial effect of significantly reducing the maximum field intensity and impact ionization of the channel and greatly improving the hot carrier injection effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0050] Figure 1 It is a structural schematic diagram of an LDMOS device in the prior art;

[0051] Figure 2 A flowchart of an embodiment of a method for preparing an LDMOS device of the present invention;

[0052] Figure 3is a flowchart of step S1 of an embodiment of a method for preparing an LDMOS device of the present invention;

[0053] Figure 4 is a flow chart of step S5 of an embodiment of the method for preparing an LDMOS device of the present invention;

[0054] Figure 5 This is a flow chart of the step of forming a second type heavily doped polysilicon gate in step S6 of an embodiment of the method for preparing an LDMOS device of the present invention;

[0055] Figure 6 This is a flow chart of the step of forming a first type heavily doped polysilicon gate in step S6 of an embodiment of the method for manufacturing an LDMOS device of the present invention;

[0056] Figure 7 This is a schematic diagram of the state when step S1 of the embodiment of the method for preparing an LDMOS device of the present invention is completed;

[0057] Figure 8 This is a schematic diagram of the state when step S4 of the embodiment of the method for preparing an LDMOS device of the present invention is completed;

[0058] Fig. 9 This is a schematic diagram of the state when step S6 of the embodiment of the method for preparing an LDMOS device of the present invention is completed;

[0059] Fig.10 A schematic structural diagram of an embodiment of an LDMOS device of the present invention;

[0060] Fig.11 A schematic diagram of a simulated electric field of an embodiment of an LDMOS device of the present invention;

[0061] Fig.12 FIG. 4 is a simulation curve diagram of substrate current and gate voltage of an embodiment of an LDMOS device of the present invention. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0064] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0065] like Figure 2 As shown, the technical solution of the present invention includes a method for preparing an LDMOS device, which includes the following steps:

[0066] Step S1, providing a substrate of a first type semiconductor material, the upper part of the substrate includes a buried layer of a second type semiconductor material, an epitaxial layer of the first type semiconductor material is arranged on the top of the buried layer, a well region of the first type semiconductor material is arranged on one side of the epitaxial layer, and a drift region is arranged on the other side, a field oxide layer is formed above the middle of the drift region, and the upper surface of the drift region is exposed on both sides of the field oxide layer;

[0067] Step S2, forming a gate oxide layer covering a portion of the well region on a side of the field oxide layer facing the well region;

[0068] Step S3, forming a continuous polysilicon gate layer on the upper surface of the gate oxide layer and the upper surface of the field oxide layer, so that the polysilicon gate layer covers the upper surface of the gate oxide layer and a portion of the upper surface of the field oxide layer;

[0069] Step S4, dividing the polysilicon gate layer into a first polysilicon gate layer corresponding to the well region and a second polysilicon gate layer corresponding to the drift region;

[0070] Step S5, forming sidewalls on both sides of the first polysilicon gate layer and the second polysilicon gate layer respectively;

[0071] Step S6, respectively defining source and drain doped regions on a side of the gate oxide layer facing away from the drift region and on a side of the field oxide layer facing away from the well region, and simultaneously heavily doping the source and drain doped regions and the first polysilicon gate layer with second-type semiconductor ions through a first mask, and defining a first-type semiconductor ion heavily doped region on a side of the source and drain doped regions on one side of the gate oxide layer facing away from the drift region, and simultaneously heavily doping the first-type semiconductor ion heavily doped region and the second polysilicon gate layer with first-type semiconductor ions through a second mask.

[0072] The above technical solution divides the continuous polysilicon gate layer used for doping to form the gate into the first polysilicon gate layer and the second polysilicon, and performs heavy doping through subsequent second-type semiconductor ion implantation and first-type semiconductor ion implantation, respectively forming the second-type polysilicon gate on the first polysilicon gate layer, and forming the first-type polysilicon gate with the second polysilicon gate layer. Compared with the existing LDMOS manufacturing process, taking N-type LDMOS as an example, the maximum field strength and impact ionization of the channel can be significantly reduced, and the hot carrier injection effect is greatly improved.

[0073] As a preferred embodiment, the first type semiconductor material may be a P-type semiconductor material. More preferably, the P-type semiconductor material may be P-type silicon.

[0074] As a preferred embodiment, the second type semiconductor material may be an N-type semiconductor material. More preferably, the N-type semiconductor material may be N-type silicon.

[0075] As a preferred embodiment, Figure 3 and Figure 7 As shown, step S1 includes,

[0076] Step S11, providing a substrate made of a first type semiconductor material;

[0077] Step S12, forming a buried layer 101 on the upper part of the substrate by implanting second type semiconductor ions;

[0078] Step S13, growing an epitaxial layer 102 on the upper surface of the buried layer;

[0079] Step S14, forming an oxide layer on the upper surface of the epitaxial layer, and etching the oxide layer to form a field oxide layer 103;

[0080] In step S15 , the well region 105 and the drift region 104 are formed by ion implantation, and an annealing process is performed on the well region 105 and the drift region 104 .

[0081] As a preferred embodiment, Figure 8 As shown, in step S2, the gate oxide layer 106 may be formed by a thermal oxidation process.

[0082] As a preferred implementation, in step S3, a continuous polysilicon gate layer 107 may be formed by a deposition process.

[0083] As a preferred implementation, in step S4 , a mask layer may be formed by a photolithography process, and the polysilicon gate layer 107 may be etched through the mask layer to form a first polysilicon gate layer 1071 and a second polysilicon gate layer 1072 .

[0084] As a preferred embodiment, Figure 4 As shown, step S5 includes the following steps:

[0085] Step S51, forming a first sidewall spacer on both sides of the first polysilicon gate layer and the second polysilicon gate layer respectively;

[0086] Step S52, forming a nitride layer on the upper surface of the epitaxial layer, the outer surface of the first sidewall, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer;

[0087] Step S53, etching and removing the nitride layer on the upper surface of the epitaxial layer, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer, retaining the nitride layer on the outer surface of the first sidewall spacer to form a second sidewall spacer.

[0088] As a preferred embodiment, Figure 5 and Fig. 9 As shown, step S6 includes,

[0089] Step S611, forming a photoresist layer (not formed on the upper surface of the epitaxial layer 102, the outer surface of the second sidewall, the upper surface of the first polysilicon gate layer 1071 and the upper surface of the second polysilicon gate layer 1072) Figure 8 )

[0090] Step S612, patterning the photoresist layer to open process windows corresponding to the source and drain regions 108 and the first polysilicon gate layer 1071;

[0091] Step S613, performing second-type semiconductor ion implantation on the source / drain region 108 and the first polysilicon gate layer 1071 through the photoresist layer to form the second-type semiconductor ion heavily doped source / drain region 108 and the second-type ion heavily doped polysilicon gate;

[0092] Step S614, removing the photoresist layer, and performing heat treatment on the source and drain regions 108 and the first polysilicon gate layer 1071 after ion implantation to activate the ion implantation regions and perform surface repair.

[0093] As a preferred embodiment, Figure 5 and Fig. 9 As shown, step S6 includes,

[0094] Step S621, forming a photoresist layer on the upper surface of the epitaxial layer 102, the outer surface of the second sidewall, the upper surface of the first polysilicon gate layer 1071 and the upper surface of the second polysilicon gate layer 1072;

[0095] Step S622, patterning the photoresist layer to open process windows corresponding to the first-type semiconductor ion heavily doped region 109 and the second polysilicon gate layer 1072;

[0096] Step S623, performing first-type semiconductor ion implantation into the first-type semiconductor ion heavily doped region 109 and the second polysilicon gate layer 1072 through the photoresist layer to form a first-type semiconductor ion heavily doped region and a first-type ion heavily doped polysilicon gate;

[0097] Step S624, removing the photoresist layer, and performing heat treatment on the first type semiconductor ion heavily doped region and the second polysilicon gate layer after ion implantation to activate the ion implantation region and perform surface repair.

[0098] The technical solution of the present invention also includes: Fig.10An LDMOS device is shown, comprising:

[0099] A substrate made of a first type semiconductor material;

[0100] A buried layer 101 of a second type semiconductor material is disposed on the top of the substrate;

[0101] An epitaxial layer 102 of a first type semiconductor material is disposed on the upper surface of the buried layer.

[0102] A well region 105 of a first type semiconductor material is disposed on one side of the epitaxial layer 102, and an upper surface of the well region 105 is flush with an upper surface of the epitaxial layer 102;

[0103] A drift region 104 is disposed on a side of the epitaxial layer 102 opposite to the well region 105, and an upper surface of the drift region 104 is flush with an upper surface of the epitaxial layer 102;

[0104] A field oxide layer 103 is disposed on the upper surface of the drift region 104 , and both sides of the field oxide layer 103 expose the upper surface of the drift region 104 ;

[0105] A gate oxide layer 106 is disposed on a side of the field oxide layer 103 facing the well region 105;

[0106] A first polysilicon gate layer 1071 heavily doped with second-type semiconductor ions is located on the upper surface of the gate oxide layer 106 and corresponds to the well region 105;

[0107] A second polysilicon gate layer 1072 heavily doped with first-type semiconductor ions is located on the upper surface of the field oxide layer 103 and corresponds to the drift region 104;

[0108] The source and drain regions 108 heavily doped with second-type semiconductor ions are respectively located on the side of the gate oxide layer 106 facing away from the drift region 104 and the side of the field oxide layer 103 facing away from the well region 105;

[0109] A first type semiconductor ion heavily doped region 109 is located on the side of the source / drain region 108 on the gate oxide layer 106 facing away from the drift region 104 .

[0110] As a preferred embodiment, the first type semiconductor material may be a P-type semiconductor material. More preferably, the P-type semiconductor material may be P-type silicon.

[0111] As a preferred embodiment, the second type semiconductor material may be an N-type semiconductor material. More preferably, the N-type semiconductor material may be N-type silicon.

[0112] like Figure 11-Figure 12From the simulation results, it can be seen that when the gate voltage of the LDMOS device provided by the above technical solution is 2V, the maximum electric field strength at the device channel is significantly reduced, and the substrate current Isub can be reduced by about 20%, which significantly reduces the maximum field strength and collision ionization of the device channel and greatly improves the hot carrier injection effect.

[0113] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing an LDMOS device, characterized in that: The following steps are included: Step S1, providing a substrate of a first-type semiconductor material, wherein the upper portion of the substrate includes a buried layer of a second-type semiconductor material, an epitaxial layer of a first-type semiconductor material is disposed on the top of the buried layer, a well region of the first-type semiconductor material is disposed on one side of the epitaxial layer, and a drift region is disposed on the other side, a field oxide layer is formed above the middle of the drift region, and both sides of the field oxide layer expose the upper surface of the drift region; Step S2, forming a gate oxide layer that partially covers the well region on a side of the field oxide layer facing the well region; Step S3, forming a continuous polysilicon gate layer on the upper surface of the gate oxide layer and the upper surface of the field oxide layer, so that the polysilicon gate layer covers the upper surface of the gate oxide layer and a portion of the upper surface of the field oxide layer; Step S4, dividing the polysilicon gate layer into a first polysilicon gate layer corresponding to the well region and a second polysilicon gate layer corresponding to the drift region; Step S5, forming sidewalls on both sides of the first polysilicon gate layer and the second polysilicon gate layer respectively; Step S6, respectively defining source-drain doped regions on a side of the gate oxide layer facing away from the drift region and on a side of the field oxide layer facing away from the well region, and simultaneously heavily doping the source-drain doped regions and the first polysilicon gate layer with second-type semiconductor ions through a first mask, and defining a first-type semiconductor ion heavily doped region on a side of the gate oxide layer facing away from the drift region, and simultaneously heavily doping the first-type semiconductor ion heavily doped region and the second polysilicon gate layer with first-type semiconductor ions through a second mask.

2. The preparation method according to claim 1, characterized in that The step S1 comprises: Step S11, providing a substrate made of a first type semiconductor material; Step S12, forming the buried layer on the upper part of the substrate by implanting second type semiconductor ions; Step S13, growing the epitaxial layer on the upper surface of the buried layer; Step S14, forming an oxide layer on the upper surface of the epitaxial layer, and etching the oxide layer to form the field oxide layer; Step S15 , forming the well region and the drift region respectively by ion implantation, and performing annealing processes on the well region and the drift region respectively.

3. The preparation method according to claim 1, characterized in that: In the step S2, the gate oxide layer is formed by a thermal oxidation process.

4. The preparation method according to claim 1, characterized in that: In the step S3, the polysilicon gate layer is formed by a deposition process.

5. The preparation method according to claim 1, characterized in that: In the step S4, a mask layer is formed by a photolithography process, and the polysilicon gate layer is etched through the mask layer to form the first polysilicon gate layer and the second polysilicon gate layer.

6. The preparation method according to claim 1, characterized in that: Step S5 The following steps are included: Step S51, forming a first sidewall spacer on both sides of the first polysilicon gate layer and the second polysilicon gate layer respectively; Step S52, forming a nitride layer on the upper surface of the epitaxial layer, the outer surface of the first sidewall, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer; Step S53, etching and removing the nitride layer on the upper surface of the epitaxial layer, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer, retaining the nitride layer on the outer surface of the first sidewall to form a second sidewall.

7. The preparation method according to claim 6, characterized in that: The step S6 comprises: Step S611, forming a photoresist layer on the upper surface of the epitaxial layer, the outer surface of the second sidewall, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer; Step S612, patterning the photoresist layer to open process windows corresponding to the source and drain doping regions and the first polysilicon gate layer; Step S613, performing second type semiconductor ion implantation into the source / drain doping region and the first polysilicon gate layer through the photoresist layer; Step S614, removing the photoresist layer, and performing heat treatment on the source / drain doped regions and the first polysilicon gate layer after ion implantation.

8. The preparation method according to claim 6, characterized in that: The step S6 comprises: Step S621, forming a photoresist layer on the upper surface of the epitaxial layer, the outer surface of the second sidewall, the upper surface of the first polysilicon gate layer and the upper surface of the second polysilicon gate layer; Step S622, patterning the photoresist layer to open a process window corresponding to the first-type semiconductor ion heavily doped region and the second polysilicon gate layer; Step S623, performing first-type semiconductor ion implantation into the first-type semiconductor ion heavily doped region and the second polysilicon gate layer through the photoresist layer; Step S624, removing the photoresist layer, and performing heat treatment on the first-type semiconductor ion heavily doped region and the second polysilicon gate layer after ion implantation.

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