semiconductor devices

Abstract

The semiconductor device includes a first semiconductor region, which is arranged on a first electrode, electrically connected to the first electrode, and is of the first conductivity type; a second semiconductor region, which is arranged on a portion of the first semiconductor region, is of the second conductivity type; a third semiconductor region, which is arranged on the second semiconductor region, is of the first conductivity type; a first conductive portion, which has a portion opposite to the side of the second semiconductor region; a second conductive portion, which has a portion opposite to the side of the first semiconductor region; a second electrode, which is arranged on the second semiconductor region and the third semiconductor region, and is electrically connected to the second semiconductor region and the third semiconductor region; a first conductive region, which is arranged on the second conductive portion, and is electrically connected to the second conductive portion; a first electrode region, which is electrically connected to the first conductive region; and a conductive layer, which is electrically connected to at least any one of the first conductive region and the first electrode region and the second electrode.

Description

[0001] This application claims the benefit of priority based on Japanese Patent Application No. 2020-155198 (filing date: September 16, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments relate to a semiconductor device. Background Art

[0003] A semiconductor device having a field plate is known, and there is a demand for improved reliability of such a semiconductor device. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device capable of achieving improved reliability.

[0005] A semiconductor device according to an embodiment includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first conductive portion, a second conductive portion, a second electrode, a first conductive region, a first electrode region, and a conductive layer. The first semiconductor region is provided on the first electrode, electrically connected to the first electrode, and has a first conductivity type. The second semiconductor region is provided on a portion of the first semiconductor region, has a second conductivity type. The third semiconductor region is provided on the second semiconductor region and has the first conductivity type. The first conductive portion has a portion opposing a side surface of the second semiconductor region. The second conductive portion has a portion opposing a side surface of the first semiconductor region. The second electrode is provided on the second semiconductor region and the third semiconductor region, and is electrically connected to the second and third semiconductor regions. The first conductive region is provided on the second conductive portion and is electrically connected to the second conductive portion. The first electrode region is electrically connected to the first conductive region. The conductive layer is electrically connected to at least one of the first conductive region and the first electrode region, and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A and Figure 1B It is a plan view showing the semiconductor device according to the first embodiment.

[0007] Figure 2 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0008] Figure 3 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0009] Figure 4 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0010] Figure 5 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0011] Figure 6 It is a plan view showing the semiconductor device according to the first embodiment.

[0012] Figure 7 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0013] Figure 8 This table explains wafer testing of semiconductor devices.

[0014] Figure 9A and Figure 9B It is a plan view showing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0016] The accompanying drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the ratio of the dimensions between the parts, etc. may not necessarily be the same as the actual situation. Even when showing the same part, the dimensions and ratios may be shown differently depending on the drawing.

[0017] In the present specification and the drawings, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof will be appropriately omitted.

[0018] In the following description and drawings, n + 、n - and p + The expressions "+" and "-" indicate the relative levels of each impurity concentration. Specifically, expressions appended with a "+" indicate a higher impurity concentration than expressions without either a "+" or a "-" sign, while expressions appended with a "-" indicate a lower impurity concentration than expressions without either a "+" or a "-" sign. These expressions indicate the relative levels of net impurity concentration after compensation for both p-type and n-type impurities in each region.

[0019] Each embodiment described below can be implemented by reversing the p-type (an example of the second conductivity type) and the n-type (an example of the first conductivity type) of each semiconductor region.

[0020] (First embodiment)

[0021] Figure 1A and Figure 1B It is a plan view showing the semiconductor device according to the first embodiment.

[0022] The semiconductor device 100 according to the first embodiment is, for example, a MOSFET. Figure 1A As shown, a source electrode 12 , a field plate electrode (FP electrode pad region 13 and FP wiring region 41 ), and a gate electrode (gate electrode pad region 14 and gate wiring region 42 ) are provided on the upper surface of the semiconductor device 100 .

[0023] Figure 1B is Figure 1A A perspective view in which the source electrode 12, the FP electrode pad region 13, the gate electrode pad region 14, the FP wiring region 41, and the gate wiring region 42 are omitted. Figure 1B Indicated by dotted line Figure 1A The positions of the FP electrode pad region 13, the gate electrode pad region 14, the FP wiring region 41, and the gate wiring region 42 are shown. Figure 1A and Figure 1B The illustration of the passivation film described later is omitted.

[0024] Figures 2 to 5 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0025] Figure 2 yes Figure 1A and Figure 1B Section II-II. Figure 3 yes Figure 1A and Figure 1B Section III-III of the diagram. Figure 4 yes Figure 1A and Figure 1B Section IV-IV of the diagram. Figure 5 yes Figure 1A and Figure 1B VV cross-section diagram.

[0026] like Figure 2 As shown, the semiconductor device 100 includes n - type drift region 21 (first semiconductor region), a plurality of p-type base regions 22 (second semiconductor region), n + Multiple source regions 23 (third semiconductor regions) of type n + Type drain region 24, p + The device comprises a plurality of contact regions 25, a drain electrode 11 (first electrode), a plurality of gates 31 (first conductive portion), a plurality of field plates 32 (second conductive portion), an FP wiring region 41 (first conductive region), a gate wiring region 42 (second conductive region), a source electrode 12 (second electrode), an FP electrode pad region 13 (first electrode region) and a gate electrode pad region 14 (second electrode region).

[0027] In addition, Figure 2 1 to 4 show the FP wiring region 41, the gate wiring region 42, the FP electrode pad region 13, and the gate electrode pad region 14. Figure 5 The semiconductor device 100 is shown during, for example, wafer testing. As will be described later, after the wafer testing, package assembly is performed and connectors are connected.

[0028] In the description of the embodiments, a first direction D1, a second direction D2, and a third direction D3 are used. The direction from the drain electrode 11 toward the drift region 21 is referred to as the first direction D1. A direction perpendicular to the first direction D1 is referred to as the second direction D2. The direction perpendicular to the first direction D1 and perpendicular to the second direction D2 is referred to as the third direction D3. Furthermore, for ease of description, the direction from the drain electrode 11 toward the drift region 21 is referred to as "upward," and the opposite direction is referred to as "downward." These directions are based on the relative positional relationship between the drain electrode 11 and the drift region 21 and are independent of the direction of gravity.

[0029] like Figure 2 As shown, a drain electrode 11 is provided on the lower surface of the semiconductor device 100 . A drift region 21 is provided on the drain electrode 11 via a drain region 24 . The drift region 21 is electrically connected to the drain electrode 11 via the drain region 24 .

[0030] A plurality of base regions 22 are respectively disposed on the portion 21a of the drift region 21. A plurality of source regions 23 are respectively disposed on the plurality of base regions 22. A plurality of contact regions 25 are respectively disposed on the plurality of base regions 22. The source regions 23 and the contact regions 25 are arranged side by side in the second direction D2. Two source regions 23 are located on one base region 22, and one contact region 25 is located between the two source regions 23.

[0031] The plurality of gates 31 are respectively provided on the portion 21b of the drift region 21. The gates 31 have portions facing the side surfaces 22s of the base region 22 via the gate insulating film 51. The gates 31 and at least a portion of the base region 22 are arranged in parallel in the second direction D2.

[0032] Multiple field plates 32 are provided on portions 21b of the drift region 21. Each field plate 32 has a portion facing the side surface 21s of the drift region 21, with the FP insulating film 52 (first insulating film) interposed therebetween. The field plates 32 are arranged parallel to a portion of the drift region 21 and at least a portion of the gate 31 in the second direction D2. An intermediate insulating film 54 (second insulating film) is provided between the field plates 32 and the gate 31.

[0033] In this example, a trench 59 is formed on the portion 21b of the drift region 21. An insulating portion 50 is provided in the trench. The gate 31 and the field plate 32 are provided in the insulating portion 50. The gate insulating film 51, the FP insulating film 52, and the intermediate insulating film 54 are part of the insulating portion 50. Figure 2 In the example shown in FIG. 5 , two gates 31 are provided in one insulating portion 50 , and a field plate 32 is provided between the two gates 31 . The field plate 32 extends downwardly relative to the gates 31 . Base regions 22 are selectively provided between adjacent insulating portions 50 .

[0034] The source electrode 12 is provided on the source region 23 , the contact region 25 , the gate 31 , and the field plate 32 . The source electrode 12 is electrically connected to the source region 23 . Furthermore, the source electrode 12 is electrically connected to the base region 22 via the contact region 25 .

[0035] An insulating film 53 is provided between the gate 31 and the source electrode 12, and between the field plate 32 and the source electrode 12. This electrically isolates the gate 31 from the source electrode 12. Furthermore, the field plate 32 and the source electrode 12 are not in direct contact and are electrically isolated during wafer testing.

[0036] like Figure 3 As shown, the FP wiring region 41 is provided on the field plate 32 and is electrically connected to the field plate 32. For example, the FP contact portion 41c is provided in the opening of the insulating film 53. The FP wiring region 41 is connected to the field plate 32 via the FP contact portion 41c.

[0037] A protective film 61 (passivation film) is provided between the FP wiring region 41 and the source electrode 12. A portion of the protective film 61 contacts the FP wiring region 41, while another portion of the protective film 61 contacts the source electrode 12. The FP wiring region 41 and the source electrode 12 are not in direct contact and are electrically isolated during wafer testing.

[0038] In this example, the height of the FP wiring region 41 is the same as the height of the source electrode 12. That is, at least a portion of the FP wiring region 41 overlaps with the source electrode 12 in the third direction D3. For example, the position of the upper surface 41U of the FP wiring region 41 in the first direction D1 is the same as the position of the upper surface 12U of the source electrode 12 in the first direction D1. In this specification, the scope of "same" does not only mean strictly the same, but can also include, for example, variations in the manufacturing process, as long as they are substantially the same. However, the height of the FP wiring region 41 and the height of the source electrode 12 are not limited to the above case and can also be different from each other.

[0039] like Figure 4As shown, the gate wiring region 42 is provided on the gate 31 and is electrically connected to the gate 31. For example, the gate contact portion 42c is provided in the opening of the insulating film 53. The gate wiring region 42 is connected to the gate 31 via the gate contact portion 42c.

[0040] A protective film 62 (passivation film) is provided between the gate wiring region 42 and the source electrode 12. The protective film 62 covers the gate wiring region 42. A portion of the protective film 62 contacts the gate wiring region 42, while another portion of the protective film 62 contacts the source electrode 12. The gate wiring region 42 and the source electrode 12 are electrically isolated.

[0041] In this example, the height of the gate wiring region 42 is the same as the height of the source electrode 12. That is, at least a portion of the gate wiring region 42 overlaps with the source electrode 12 in the third direction D3. For example, the position of the upper surface 42U of the gate wiring region 42 in the first direction D1 is the same as the position of the upper surface 12U of the source electrode 12 in the first direction D1. However, the height of the gate wiring region 42 and the height of the source electrode 12 are not limited to the above and can also be different.

[0042] like Figure 5 As shown in FIG. 1 , the FP electrode pad region 13 is provided on the drift region 21 and the insulating film 53. Figure 5 The position of the FP wiring region 41 is indicated by a dotted line in FIG. The FP electrode pad region 13 is continuous with the FP wiring region 41 and electrically connected to the FP wiring region 41. The FP electrode pad region 13 is parallel to the FP wiring region 41 in the second direction D2. The FP electrode pad region 13 may also be integral with the FP wiring region 41. In this example, the width 13w of the FP electrode pad region 13 (the length along the third direction D3) is wider than the width 41w of the FP wiring region 41. However, the width 13w of the FP electrode pad region 13 may also be the same as the width 41w of the FP wiring region 41.

[0043] A protective film 63 (passivation film) is provided between the FP electrode pad region 13 and the source electrode 12. The protective film 63 may be provided with respect to Figure 3 The protective film 61 is shown as a single piece. A portion of the protective film 63 contacts the FP electrode pad region 13, and another portion of the protective film 63 contacts the source electrode 12. The FP electrode pad region 13 and the source electrode 12 are not in direct contact and are electrically separated during wafer testing.

[0044] In this example, the height of FP electrode pad region 13 is the same as the height of source electrode 12. That is, at least a portion of FP electrode pad region 13 overlaps with source electrode 12 in third direction D3. For example, the position of upper surface 13U of FP electrode pad region 13 in first direction D1 is the same as the position of upper surface 12U of source electrode 12 in first direction D1. However, the height of FP electrode pad region 13 and the height of source electrode 12 are not limited to this and may differ from each other.

[0045] The description will be continued with reference to FIG1 again. Figure 1B As shown, the drift region 21 of the semiconductor device 100 includes a central region 21c and a peripheral region 21e. The central region 21c is where the base region 22, source region 23, insulating portion 50, gate 31, field plate 32, and the like are located. The peripheral region 21e surrounds the central region 21c when viewed from the first direction D1 and includes the outer edge of the semiconductor device 100.

[0046] like Figure 1A As shown, the gate wiring region 42 and the gate electrode pad region 14 are arranged on the peripheral region 21e in a manner that surrounds the source electrode 12. In this example, a portion of the gate wiring region 42 is respectively arranged on both end sides of the third direction D3 and extends along the second direction D2. The gate wiring region 42 is located above the plurality of gates 31 and is respectively connected to the plurality of gates 31. The gate electrode pad region 14 is continuous with the gate wiring region 42 and is electrically connected to the gate wiring region 42. In addition, the gate electrode and the field plate electrode do not directly contact each other and are electrically separated during wafer testing. The gate electrode pad region 14 is electrically separated from the source electrode 12.

[0047] like Figure 1B As shown, the plurality of insulating portions 50 (a plurality of gates 31, a plurality of field plates 32) are arranged in parallel in the second direction D2. The insulating portions 50 (gates 31, field plates 32) extend along the third direction D3. Figure 1B For ease of observation, the insulating portion 50 , the gate 31 , and the field plate 32 are shown together.

[0048] The plurality of base regions 22 (the plurality of source regions 23 and the plurality of contact regions 25) are arranged in parallel in the second direction D2. The base regions 22 (the source regions 23 and the contact regions 25) extend along the third direction D3. Figure 1B For ease of observation, the base region 22 , the source region 23 , and the contact region 25 are shown together.

[0049] The insulating portions 50 and the base regions 22 are alternately arranged in parallel in the second direction D2. That is, one base region 22 is located between one insulating portion 50 and another insulating portion 50. One insulating portion 50 is located between one base region 22 and another base region 22.

[0050] The FP wiring region 41 extends along the second direction D2. Thus, the FP wiring region 41 is located above each of the plurality of field plates 32 and is connected to each of the plurality of field plates 32. For example, the FP wiring region 41 is located above the central portion (e.g., the center) of the field plate 32 in the third direction D3.

[0051] The end portion 12e of the source electrode 12 (see Figure 1A ) is located above the outer peripheral region 21e. Furthermore, in this example, (at least a portion of) the FP electrode pad region 13 is located above the outer peripheral region 21e and is aligned with the end portion 12e of the source electrode 12 in the third direction D3. However, the FP electrode pad region 13 may not be aligned with the end portion 12e of the source electrode 12 in the third direction D3.

[0052] Furthermore, in this example, the source electrode 12 has a first region 12L and a second region 12R (see Figure 1A ). The second region 12R is separated from the first region 12L in the third direction D3. Figure 1A 、 Figure 3 and Figure 5 As shown, the FP wiring region 41 and the FP electrode pad region 13 are provided between the first region 12L and the second region 12R. However, the first region 12L and the second region 12R are not limited to this configuration and may not be separated from each other. For example, a portion of the first region 12L may be connected to a portion of the second region 12R.

[0053] like Figure 1A As shown, in this example, the gate electrode pad region 14 and the FP electrode pad region 13 are located at opposite ends of the semiconductor device 100. For example, the peripheral region 21e includes a first end 21g and a second end 21h separated from each other in the second direction D2 (see FIG. Figure 1B ).exist Figure 1AIn the example shown, the gate electrode pad region 14 is located on the first end portion 21g, and the FP electrode pad region 13 is located on the second end portion 21h. A portion of the source electrode 12 is located between the gate electrode pad region 14 and the FP electrode pad region 13. The FP electrode pad region 13 (and the FP wiring region 41) and the gate electrode pad region 14 (and the gate wiring region 42) are electrically separated during wafer testing. However, the configuration of the gate electrode pad region 14 and the FP electrode pad region 13 is not limited to the configuration described above; the gate electrode pad region 14 and the FP electrode pad region 13 may not be located at opposite ends of the semiconductor device 100.

[0054] Figure 6 It is a plan view showing the semiconductor device according to the first embodiment.

[0055] Figure 7 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0056] Figure 6 and Figure 7 FIG. 1 shows, for example, the semiconductor device 100 after package assembly.

[0057] like Figure 6 As shown, the semiconductor device 100 may further include a source connector 71 (first conductive component) and a gate connector 72 (second conductive component).

[0058] Source connector 71 is provided on source electrode 12 and electrically connected to source electrode 12. Furthermore, source connector 71 is provided on at least a portion of FP wiring region 41 and FP electrode pad region 13 and electrically connected to at least a portion of FP wiring region 41 and FP electrode pad region 13. Thus, the potential of FP wiring region 41, the potential of FP electrode pad region 13, and the potential of source electrode 12 are the same.

[0059] The gate connector 72 is disposed on the gate electrode pad region 14 and is electrically connected to the gate electrode pad region 14 .

[0060] Figure 7 yes Figure 6 VII-VII section diagram. Figure 7As shown, semiconductor device 100 further includes a conductive layer 75 connected to source connector 71. Conductive layer 75 is provided on source electrode 12, FP wiring region 41, protective film 61, and protective film 62. Conductive layer 75 is electrically connected to source electrode 12 and FP wiring region 41. Source connector 71 is provided on conductive layer 75 and electrically connected to conductive layer 75. Thus, source connector 71 is electrically connected to source electrode 12 and FP wiring region 41 via conductive layer 75. Alternatively, conductive layer 75 may be located on FP electrode pad region 13 and connect FP electrode pad region 13 and source connector 71. In an embodiment, conductive layer 75 is provided on at least one of FP wiring region 41 and FP electrode pad region 13 and electrically connected to at least one of FP wiring region 41 and FP electrode pad region 13. Conductive layer 75 is, for example, solder.

[0061] The gate wiring region 42 is covered with a protective film 62. The source connector 71 is electrically connected to the gate wiring region 42 and the gate electrode pad region 14.

[0062] Likewise, in Figure 6 A solder (conductive layer), for example, is also provided below the gate connector 72 shown. Gate connector 72 is electrically connected to gate electrode pad region 14 via the solder. Furthermore, the method for connecting electrodes to each other is not limited to a connector (e.g., part of a semiconductor package); a cable may also be used. Conductive layer 75 may also be, for example, a eutectic alloy.

[0063] An example of materials for each component of the semiconductor device 100 will be described.

[0064] The drift region 21, base region 22, source region 23, drain region 24, and contact region 25 include silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity.

[0065] The gate 31 and the field plate 32 include conductive materials such as polysilicon. Impurities may also be added to the conductive materials.

[0066] The insulating portion 50 , the gate insulating film 51 , the FP insulating film 52 , the insulating film 53 , and the intermediate insulating film 54 include insulating materials such as silicon oxide.

[0067] The protective films 61 , 62 , and 63 are made of insulating materials such as polyimide, silicon oxide, or silicon nitride.

[0068] The drain electrode 11 , the source electrode 12 , the FP electrode pad region 13 , the gate electrode pad region 14 , the FP wiring region 41 , the gate wiring region 42 , the source connector 71 , and the gate connector 72 are conductive portions made of metal such as aluminum or copper.

[0069] The operation of the semiconductor device 100 will be described.

[0070] With a positive voltage applied to the drain electrode 11 relative to the source electrode 12, a voltage above the threshold is applied to the gate 31. This forms a channel (inversion layer) in the base region 22, turning the semiconductor device 100 on. Electrons flow through the channel from the source electrode 12 to the drain electrode 11. Subsequently, when the voltage applied to the gate 31 falls below the threshold, the channel in the base region 22 disappears, turning the semiconductor device 100 off.

[0071] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 relative to the source electrode 12 increases. Due to the increase in positive voltage, the hollow layer expands from the interface between the drift region 21 and the insulating portion 50 toward the drift region 21. Due to the expansion of the hollow layer, the withstand voltage of the semiconductor device 100 can be improved, for example. Furthermore, when the semiconductor device 100 is used after the package is assembled, the potential of the field plate 32 is set to be, for example, the same as the potential of the source electrode 12. By providing the field plate 32, for example, the hollow layer easily expands in the drift region 21, which can alleviate the electric field and improve the withstand voltage of the semiconductor device 100.

[0072] As the void layer expands in the drift region 21, carriers (electrons and holes) generated by impact ionization and the like are accelerated in the void layer, causing avalanche breakdown. During avalanche breakdown, electrons pass through the drain region 24 and are discharged from the drain electrode 11. Holes pass through the contact region 25 and are discharged to the source electrode 12.

[0073] The effects of the first embodiment will be described.

[0074] For example, in the semiconductor device of the reference example, the field plate is connected to the source electrode located directly above it via a contact or other method in a specific region. In this case, the potential of the field plate is the same as that of the source electrode, even during wafer testing. In the reference example, the field plate is not an independent electrode, and a voltage different from that of the source electrode cannot be applied.

[0075] On the other hand, for the semiconductor device 100, as shown in FIG. 1 to FIG. Figure 5As described, in addition to the source electrode 12 (source electrode pad region) and the gate electrode (gate electrode pad region 14 and gate wiring region 42), an FP electrode (FP wiring region 41 and FP electrode pad region 13) electrically connected to the field plate 32 is provided. During wafer testing, the source electrode 12, FP electrode, and gate electrode are electrically insulated and independent from each other. The independence of the source electrode 12, FP electrode, and gate electrode allows different voltages to be applied to each electrode. This increases the degree of freedom in wafer testing and the accuracy of screening for rejecting defective products. Consequently, the reliability of semiconductor devices that pass wafer testing can be improved.

[0076] Figure 8 This table explains wafer testing of semiconductor devices.

[0077] In one example of wafer testing, for example, the terminals of a test probe are brought into contact with the pad regions of each electrode and a voltage is applied. For example, in wafer testing of a semiconductor device in a reference example, gate insulating film screening and withstand voltage verification are performed. In gate insulating film screening, defects in the gate insulating film are detected by applying a voltage between the gate electrode and the source electrode. Furthermore, in withstand voltage verification, withstand voltage defects are detected by applying a voltage between the drain electrode and the source electrode. Based on these tests, for example, screening of the intermediate insulating film 54 and the FP insulating film 52 can be performed for the semiconductor device 100 of the embodiment. In screening of the intermediate insulating film 54, defects in the intermediate insulating film 54 are detected by applying a voltage between the gate electrode pad region 14 and the FP electrode pad region 13. In screening of the FP insulating film 52, defects in the FP insulating film 52 are detected by applying a voltage between the drain electrode 11 and the FP electrode pad region 13. In the embodiment, more detailed wafer testing can be performed, which can improve the reliability of the semiconductor device.

[0078] And, as about Figure 1A and Figure 1B As described above, the FP wiring region 41 is located at the center portion of the field plate 32 in the third direction D3 , thereby suppressing the potential deviation of the field plate 32 in the third direction D3 .

[0079] And, as about Figure 5 As described above, the width of the FP electrode pad region 13 can be wider than the width of the FP wiring region 41, and the height of the FP electrode pad region 13 can be the same as the height of the source electrode 12 and the height of the gate electrode pad region 14. For example, by adjusting the height and width of the FP electrode pad region 13, it is possible to facilitate contact of a probe tip with the FP electrode pad region 13 during wafer testing.

[0080] In package assembly after wafer testing, such as Figure 6 and Figure 7 As described above, source connector 71 is provided, and the potential of FP electrode pad region 13 is the same as that of source electrode 12. Consequently, semiconductor device 100, after being assembled into a package, can be handled as a three-terminal component consisting of drain electrode 11, source electrode 12, and gate electrode pad region 14. This reduces specification changes and reduces costs compared to conventional semiconductor devices.

[0081] Also as about Figure 1A and Figure 1B As described, the FP electrode pad region 13 is located above the outer peripheral region 21e and is aligned with the end portion 12e of the source electrode 12 in the third direction D3. Furthermore, the FP wiring region 41 is located between the first region 12L and the second region 12R of the source electrode 12. Thus, the FP electrode pad region 13 and the FP wiring region 41 are arranged so as to be sandwiched between the source electrode 12 when viewed from above. This facilitates the placement of a single source connector 71 above the source electrode 12, the FP electrode pad region 13, and the FP wiring region 41 for connection. Furthermore, it is easy to arrange the gate connector 72 separately from the source connector 71 connected to the FP electrode pad region 13 and the like.

[0082] In addition, you can also Figure 3 As described above, the height of the FP wiring region 41 is the same as the height of the source electrode 12. For example, by adjusting the height of the FP wiring region 41, it is possible to Figure 7 The source connector 71 can be easily connected with solder.

[0083] In addition, Figure 6 and Figure 7 In the example shown, the source electrode 12 and the FP electrode pad region 13 are set to the same potential. However, the gate electrode pad region 14 and the FP electrode pad region 13 may also be set to the same potential. For example, the gate connector 72 connected to the gate electrode pad region 14 may be electrically connected to at least one of the FP wiring region 41 and the FP electrode pad region 13. Specifically, for example, the conductive layer 75 connected to the FP electrode may not be connected to the source electrode 12, but may be provided on the gate electrode (at least one of the gate electrode pad region 14 and the gate wiring region 42) and electrically connected to the gate electrode. For example, the gate connector 72 may be provided on the conductive layer 75, and the conductive layer 75 and the gate connector 72 may be electrically connected. In this case, for example, the conductive layer 75 is not connected to the source electrode 12 and the source connector 71. The source connector 71 connected to the source electrode 12 is not connected to the FP wiring region 41 and the FP electrode pad region 13, but is electrically separated. Even in this case, for example, it is possible to handle the device as a three-terminal component after package assembly.

[0084] (Second embodiment)

[0085] Figure 9A and Figure 9B It is a plan view showing a semiconductor device according to a second embodiment.

[0086] Figure 9A FIG. 1 shows the wafer test of the semiconductor device 101 according to the second embodiment. Figure 9B FIG. 1 shows the wafer test of the semiconductor device 102 according to the second embodiment.

[0087] like Figure 9A As shown, the semiconductor device 101 includes an element portion 81. The element portion 81 is electrically connected to the source electrode 12. For example, the element portion 81 is in contact with the source electrode 12, or is connected to the source electrode 12 via the conductive portion 91. Furthermore, the element portion 81 is electrically connected to at least one of the FP electrode pad region 13 and the FP wiring region 41. For example, the element portion 81 is in contact with at least one of the FP electrode pad region 13 and the FP wiring region 41, or is connected to at least one of the FP electrode pad region 13 and the FP wiring region 41 via the conductive portion 92. In addition, Figure 9A and Figure 9B Schematic circuit diagrams are used to illustrate the element portion 81 , conductive portions 91 , 92 , and the like.

[0088] exist Figure 9A In the example shown, the element portion 81 includes an insulating material 81a and functions as a capacitor during wafer testing. That is, during wafer testing, the source electrode 12 and the FP electrode pad region 13 (and the FP wiring region 41) are electrically separated (insulated). Therefore, during wafer testing, the field plate 32 (see Figure 2 ) is different from the potential of the source electrode 12. The insulating material 81a includes, for example, silicon oxide or silicon nitride.

[0089] After the wafer test is completed, a voltage is applied between the source electrode 12 and the FP electrode pad area 13, thereby performing insulation breakdown on the capacitor (element portion 81). By the insulation breakdown, the source electrode 12 is electrically connected to at least one of the FP electrode pad area 13 and the FP wiring area 41 (in this example, the insulation breakdown capacitor) via the element portion 81 and is turned on. For example, after the package is assembled, the potential of the source electrode 12 and the potential of the FP electrode pad area 13 are the same as each other. In this case, it is also possible that the FP electrode pad area 13 and the FP wiring area 41 are not connected to the conductive layer 75 (see Figure 7For example, the entire upper surface of the FP wiring region 41 may be in contact with a protective film such as a passivation film. Except for the above description, the same description as that of the semiconductor device 100 can be applied to the semiconductor device 101.

[0090] exist Figure 9B In the example shown, the element portion 81 includes, for example, a semiconductor layer 81b including a pn junction, and functions as a diode (for example, a Zener diode) during wafer testing. Therefore, during wafer testing, the field plate 32 (see FIG. 1 ) can be made Figure 2 ) and the potential of the source electrode 12 are different from each other. The semiconductor layer 81b includes, for example, silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity.

[0091] After wafer testing is complete, a voltage is applied between source electrode 12 and FP electrode pad region 13, causing the diode (element portion 81) to break down. This electrically connects source electrode 12 to at least one of FP electrode pad region 13 and FP wiring region 41 (in this example, the broken-down diode) via element portion 81, causing conduction. Except for the above description, the same description as for semiconductor device 101 applies to semiconductor device 102.

[0092] Different voltages can be applied to the electrodes of both semiconductor devices 101 and 102. This increases the flexibility of wafer testing and the accuracy of rejecting defective products. Consequently, the reliability of semiconductor devices that pass wafer testing can be improved. Furthermore, even if it is difficult to set the source electrode 12 and the FP electrode pad region 13 to the same potential using, for example, the source connector 71, they can be set to the same potential by short-circuiting them through breakdown.

[0093] According to the embodiment, a semiconductor device capable of achieving improved reliability can be provided.

[0094] The relative height of the impurity concentration between each semiconductor region of each embodiment described above can be confirmed using, for example, SCM (scanning electrostatic capacitance microscope). In addition, the carrier concentration of each semiconductor region can be regarded as the same concentration as the impurity concentration activated in each semiconductor region. Therefore, the relative height of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration of each semiconductor region can be measured, for example, by SIMS (secondary ion mass spectrometry).

[0095] While several embodiments of the present invention have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope or spirit of the invention and are included within the invention set forth in the claims and their equivalents. Furthermore, the aforementioned embodiments can be implemented in combination with one another.

Claims

1. A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type, disposed on a portion of the first semiconductor region; a third semiconductor region of the first conductivity type, disposed on the second semiconductor region; a first conductive portion having a portion facing a side surface of the second semiconductor region; a second conductive portion having a portion facing a side surface of the first semiconductor region; a second electrode, disposed on the second semiconductor region and the third semiconductor region, and electrically connected to the second semiconductor region and the third semiconductor region; a first conductive region, disposed on the second conductive portion and electrically connected to the second conductive portion; a first electrode region electrically connected to the first conductive region; as well as a conductive layer electrically connected to at least any one of the first conductive region and the first electrode region and the second electrode, The first conductive region extends in a second direction, the second direction being perpendicular to the first direction from the first electrode toward the first semiconductor region. The second conductive portion extends in a third direction perpendicular to the first direction and the second direction. The first conductive region is located on the central portion of the second conductive portion in the third direction. The second electrode has a first region and a second region separated from the first region in the third direction. The first electrode region is arranged between the first region and the second region.

2. The semiconductor device according to claim 1, wherein The conductive layer includes solder.

3. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: a first insulating film provided between the second conductive portion and the first semiconductor region; and The second insulating film is provided between the first conductive portion and the second conductive portion.

4. A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type, disposed on a portion of the first semiconductor region; a third semiconductor region of the first conductivity type, disposed on the second semiconductor region; a first conductive portion having a portion facing a side surface of the second semiconductor region; a second conductive portion having a portion facing a side surface of the first semiconductor region; a second electrode, disposed on the second semiconductor region and the third semiconductor region, and electrically connected to the second semiconductor region and the third semiconductor region; a first conductive region, disposed on the second conductive portion and electrically connected to the second conductive portion; a first electrode region electrically connected to the first conductive region; as well as a capacitor electrically connected to at least any one of the first conductive region and the first electrode region and the second electrode and having insulation breakdown, or a diode electrically connected to at least any one of the first conductive region and the first electrode region and the second electrode and having insulation breakdown, The first conductive region extends in a second direction, the second direction being perpendicular to the first direction from the first electrode toward the first semiconductor region. The second conductive portion extends in a third direction perpendicular to the first direction and the second direction. The first conductive region is located on the central portion of the second conductive portion in the third direction. The second electrode has a first region and a second region separated from the first region in the third direction. The first electrode region is arranged between the first region and the second region.

5. A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type, disposed on a portion of the first semiconductor region; a third semiconductor region of the first conductivity type, disposed on the second semiconductor region; a first conductive portion having a portion facing a side surface of the second semiconductor region; a second conductive portion having a portion facing a side surface of the first semiconductor region; a second electrode, disposed on the second semiconductor region and the third semiconductor region, and electrically connected to the second semiconductor region and the third semiconductor region; a first conductive region, disposed on the second conductive portion and electrically connected to the second conductive portion; a first electrode region electrically connected to the first conductive region; a second conductive region, disposed on the first conductive portion and electrically connected to the first conductive portion; a second electrode region electrically connected to the second conductive region; as well as a conductive layer electrically connected to at least any one of the first conductive region and the first electrode region and the second electrode region, The first conductive region extends in a second direction, the second direction being perpendicular to the first direction from the first electrode toward the first semiconductor region. The second conductive portion extends in a third direction perpendicular to the first direction and the second direction. The first conductive region is located on the central portion of the second conductive portion in the third direction. The second electrode has a first region and a second region separated from the first region in the third direction. The first electrode region is arranged between the first region and the second region.

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