Secondary controlled active clamp implementation for efficiency improvement

Abstract

Controlling active clamp field effect transistors (FETs) in a secondary controlled active clamp converter is described. In one embodiment, an apparatus includes a primary side FET coupled to a transformer, a secondary side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary side controller is configured to control the active clamp FET across a current isolation barrier.

Description

[0001] Related Applications

[0002] This application is an international application of U.S. Patent Application No. 16 / 582,690, filed September 25, 2019, which claims the benefit of U.S. Provisional Application No. 62 / 890,411, filed August 22, 2019, both of which are incorporated herein by reference in their entirety. BACKGROUND

[0003] Various electronic devices (e.g., such as smartphones, tablets, notebook computers, laptops, hubs, chargers, adapters, etc.) are configured to deliver power through a Universal Serial Bus (USB) connector in accordance with USB Power Delivery (USB-PD) protocols defined in various revisions of the USB-PD specification. For example, in some applications, an electronic device can be configured as a power consumer to receive power through a USB connector (e.g., for battery charging), while in other applications, an electronic device can be configured as a power provider to provide power to another device connected to the electronic device through a USB connector. However, the USB-PD specification enables power providers and power consumers to dynamically negotiate the level of voltage and current provided. Under certain power delivery conditions, the provided voltage / current from a power provider can experience a fault condition, and the provided voltage / current received by a power consumer can experience other fault conditions. BRIEF DESCRIPTION OF DRAWINGS

[0004] The disclosure is illustrated by way of example, and not by way of limitation, in the accompanying drawings.

[0005] Figure 1 is a block diagram of a secondary controlled converter with secondary controlled active clamp control through a current isolation barrier from the secondary side to the primary side, according to one embodiment.

[0006] Figure 2 is a block diagram of a secondary controlled flyback converter with a secondary side controller that controls an active clamp FET on the primary side through a current isolation barrier, according to one embodiment.

[0007] Figure 3 is a block diagram of a circuit of a primary side controller for detecting a signal pattern from a secondary side controller for controlling an active clamp FET, according to one embodiment.

[0008] Figure 4A is a block diagram of a circuit of an active clamp N-channel field effect transistor (NFET), according to one embodiment.

[0009] Figure 4Bis a block diagram of a circuit of an active-clamp P-channel field effect transistor (PFET) according to one embodiment.

[0010] Figure 5 is a schematic diagram of a USB-PD power adapter for sending control signals from a secondary-side controller to control active-clamp FETs on the primary side through a current-isolation barrier according to one embodiment.

[0011] Figure 6 is a block diagram illustrating a system of a USB device with a secondary- controlled active-clamp FET for use in USB power delivery according to some embodiments.

[0012] Figure 7 is a waveform diagram illustrating an output voltage of a secondary- controlled AC-DC flyback converter, a gate voltage of a primary-side FET, and a drain voltage of the primary-side FET according to one embodiment.

[0013] Figure 8 is a flowchart of a method of controlling active-clamp FETs on the primary side by a secondary-side controller across a current-isolation barrier according to one embodiment.

[0014] Figure 9 is a flowchart of a method of controlling active-clamp FETs on the primary side and a primary-side FET with a secondary-side controller across a current- isolation barrier and controlling a secondary-side FET with the secondary-side controller according to another embodiment. DETAILED DESCRIPTION

[0015] The following description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of various embodiments of the technology described herein for controlling active-clamp FETs using a secondary-side controller in a secondary-controlled flyback converter for use in USB power delivery applications. It will be apparent to one skilled in the art, however, that at least some embodiments can be practiced without these specific details. In other instances, well-known components, elements, or methods have not been described in detail or have been presented in simple block diagram format in order to avoid unnecessarily obscuring the technology described herein. Thus, the specific details set forth in the following description are merely exemplary. Particular implementations can vary as a function of the

[0016] References in the description to "an embodiment", "one embodiment", "an example embodiment", "some embodiments" and "various embodiments" mean that a particular feature, structure, step, operation or characteristic being described is included in at least one embodiment of the application. The appearances of the phrases "an embodiment", "one embodiment", "an example embodiment", "some embodiments" and "various embodiments" in various places in the description are not necessarily all referring to the same embodiment.

[0017] The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrations in accordance with example embodiments. These embodiments, which can also be referred to as examples, are described in sufficient detail to enable those skilled in the art to practice embodiments of the claimed subject matter described herein. Other embodiments can be utilized and structural, logical and electrical changes can be made without departing from the scope and spirit of the claimed subject matter. The embodiments described herein are not the only way(s) to implement the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the claimed subject matter but to enable a person skilled in the art to practice, make and / or use the subject matter.

[0018] Various embodiments of techniques for using a secondary-side controller to control an active clamp FET across a pulse transformer in a secondary controlled flyback converter coupled to a power line in an electronic device in USB power delivery (USB-PD) are described herein. Examples of such electronic devices include, but are not limited to, personal computers (e.g., laptops, notebooks, etc.), mobile computing devices (e.g., tablets, tablet computers, e-reader devices, etc.), mobile communication devices (e.g., smartphones, cell phones, personal digital assistants, messaging devices, palmtop computers, etc.), connectivity and charging devices (e.g., hubs, docking stations, adapters, chargers, etc.), audio / video / data recording and / or playback devices (e.g., camcorders, audio recorders, handheld scanners, monitors, etc.), and other similar electronic devices that can communicate using USB connectors (interfaces), battery charging, and / or power delivery. Embodiments described herein can be used for AC-to-DC power adapters, GaN-based power adapters operating at 600 kHz frequency, power adapters with primary-side controllers or secondary-side controllers, power adapters operating in operating modes such as quasi-resonant mode (QR), discontinuous conduction mode (DCM), continuous conduction mode (CCM), etc. Embodiments described herein can be used for power adapter solutions along with C-type PD capability. These embodiments allow for more efficient performance, enabling the use of lower rated and thus less expensive FETs by engaging the active clamp FET by the secondary-side controller, which determines to turn the active clamp FET on / off based on parameters at the secondary side. Active clamping can also help reduce electromagnetic interference (EMI), which helps reduce the filter at the input.

[0019] A USB-enabled electronic device or system can comply with at least one release version of a USB specification. Examples of such USB specifications include, but are not limited to, the USB Specification Revision 2.0, the USB 3.0 specification, the USB 3.1 specification, and / or various supplements thereto (e.g., such as On-The-Go or OTG), versions, and errata. The USB specification generally defines the features (e.g., attributes, protocol definitions, transaction types, bus management, programming interfaces, etc.) of a differential serial bus required to design and build standard communication systems and peripheral devices. For example, a USB-enabled peripheral device is attached to a USB-enabled host device through a USB port of the host device to form a USB-enabled system. A USB 2.0 port includes a power voltage line (denoted as VBUS) at 5V, a differential pair of data lines (denoted as D+ or DP and D- or DN), and a ground line (denoted as GND) for power return. A USB 3.0 port also provides a VBUS line, a D+ line, a D- line, and a GND line for backward compatibility with USB 2.0. In addition, to support a faster differential bus (USB SuperSpeed bus), a USB 3.0 port also provides a differential pair of transmitter data lines (denoted as SSTX+ and SSTX-), a differential pair of receiver data lines (denoted as SSRX+ and SSRX-), a power line (denoted as DPWR) for power supply, and a ground line (denoted as DGND) for power return. A USB 3.1 port provides the same lines as a USB 3.0 port for backward compatibility with USB 2.0 and USB 3.0 communications, but expands the performance of the SuperSpeed bus through a series of features known as Enhanced SuperSpeed.

[0020] The latest technology for USB connectors, referred to as USB Type-C, is defined in various releases and / or versions of the USB Type-C specification, such as Release 1.0 dated August 11, 2014, Release 1.1 dated April 3, 2015, and the like. The USB Type-C specification defines Type-C receptacles, Type-C plugs, and Type-C cables that can support USB communication and power delivery over newer USB power delivery protocols defined in various revisions / versions of the USB-PD specification. Examples of USB Type-C functionality and requirements can include, but are not limited to, data and other communication according to USB 2.0 and USB 3.0 / USB 3.1, mechanical and performance requirements for Type-C cables, mechanical and performance requirements for Type-C receptacles, mechanical and performance requirements for Type-C plugs, requirements for Type-C to legacy cable assemblies and adapters, requirements for C-Type based device detection and interface configuration, requirements for optimized power delivery for Type-C connectors, and the like. According to the USB Type-C specification, a Type-C port provides a VBUS line, a D+ line, a D- line, a GND line, a SSTX+ line, a SSTX- line, a SSRX+ line, and a SSRX- line, among others. In addition, the Type-C port also provides a sideband use (denoted as SBU) line for signaling of sideband functionality, and a configuration channel (denoted as CC) line for discovery, configuration, and management of connections over a Type-C cable. A Type-C port can be associated with a Type-C plug and / or a Type-C receptacle. To facilitate use, Type-C plugs and Type-C receptacles are designed as reversible pairs that can operate regardless of the orientation of the plug to the receptacle. Thus, a standard USB Type-C connector, arranged as a standard Type-C plug or receptacle, provides pins for four VBUS lines, four ground return (GND) lines, two D+ lines (DP1 and DP2), two D- lines (DN1 and DN2), two SSTX+ lines (SSTXP1 and SSTXP2), two SSTX- lines (SSTXN1 and SSTXN2), two SSRX+ lines (SSRXP1 and SSRXP2), two SSRX- lines (SSRXN1 and SSRXN2), two CC lines (CC1 and CC2), and two SBU lines (SBU1 and SBU2), among others.

[0021] Some USB-enabled electronic devices can comply with a particular revision and / or version of the USB-PD specification (e.g., such as Revision 1.0 published on July 5, 2012, Revision 2.0 published on August 11, 2014, etc., or subsequent revisions / versions thereof). The USB-PD specification defines a standard protocol designed to maximize the functionality of USB-enabled devices by providing more flexible power delivery and data communication over a single USB Type-C cable through a USB Type-C port. The USB-PD specification also describes the architecture, protocol, power supply behavior, parameters, and cables necessary to manage power delivery over a USB Type-C cable at up to 100 W of power. According to the USB-PD specification, a device (e.g., such as a USB-enabled device) having a USB Type-C port can negotiate more current and / or higher or lower voltages over a USB Type-C cable than allowed in older USB specifications (e.g., such as the USB 2.0 specification, the USB 3.1 specification, the USB Battery Charging specification Rev. 1.1 / 1.2, etc.). For example, the USB-PD specification defines the requirements of a power delivery contract (PD contract) that can be negotiated between a pair of USB-enabled devices. The PD contract can specify the power level and direction of power transfer that both devices can accommodate, and can be dynamically renegotiated upon request by either device and / or in response to various events and conditions such as power role swap, data role swap, hard reset, power failure, etc. (e.g., without unplugging the devices).

[0022] According to the USB-PD specification, an electronic device is typically configured to deliver power to another device over a power path configured on the USB VBUS line. The device providing power is typically referred to as (or includes) a "provider" (or power source), while the device consuming power is typically referred to as (or includes) a "consumer" (or power sink). The power path typically includes a power switch coupled in series on the VBUS line and configured to turn on and turn off power delivery.

[0023] A USB-PD power source can be configured to draw power from an alternating current (AC) power adapter or another AC source. Thus, as part of an alternating current to direct current (AC-DC) conversion, some implementations can use a bulk capacitor on the power source side of the VBUS line to remove the AC component of the power signal. Turn on and turn off of a power switch (also referred to as a power FET) can allow for further circuit protection based on analysis of current and voltage conditions and detection of faults.

[0024] In a flyback converter, the active clamp FET is driven by the primary side controller. However, the primary side controller in a secondary controlled flyback converter is designed with not much intelligence as any intelligence added to the primary side controller results in: larger chip area due to higher technology node which leads to higher cost; higher mask count due to more fuses or non-volatile memory required for the intelligent logic circuitry which leads to higher cost; and higher power loss due to additional circuitry (current taken at higher voltage). Therefore, to drive the active clamp FET, the primary side controller can use a waveform signal that is 180 degrees out of phase with the waveform signal used to drive the primary side FET. In such a setup, the active clamp FET can be on for longer than necessary, resulting in energy waste and reduced efficiency. Furthermore, the primary side controller does not have access to electrical parameters related to the load requirements of the power output. Therefore, the primary side controller cannot determine whether it can be beneficial to engage the active clamp FET or cannot determine the duration of switching of the active clamp FET (e.g., the duration of the active clamp FET being on and the duration of the active clamp FET being off), which can result in additional losses due to unnecessary gate switching.

[0025] Various embodiments of techniques to improve efficiency by controlling an active clamp FET from a secondary side controller in a secondary controlled converter as compared to a conventional flyback converter are described herein. The secondary controlled active clamp embodiments described herein can address the challenges mentioned above and other challenges by controlling the active clamp FET from a secondary side controller independent of the control of the primary side FET without the additional logic and circuitry and complex protocol described above. In some embodiments, the secondary controlled active clamp described herein can be used in a secondary controlled flyback converter. Alternatively, the secondary controlled active clamp can be used in other secondary controlled converters. In some embodiments, the secondary controlled active clamp can improve efficiency by 3-4% as compared to a conventional flyback converter. In some embodiments, the secondary side controller can provide a control signal for controlling the active clamp FET on the primary side. In some embodiments, the active clamp FET on the primary side can be controlled to follow the synchronous rectification on / off period of the secondary side FET. In some embodiments, the synchronous gate rectifier pulses from the secondary side can be used to switch the active clamp FET using a separate pulse transformer. The pulse transformer can be coupled between the secondary side controller and the active clamp FET to control the active clamp FET. For example, a hardware controlled scheme or a firmware controlled scheme can use multiple consecutive pulses (e.g., +ve pulses or -ve pulses) given across a current isolation barrier such as across a pulse transformer to define the control signal to control the active clamp FET from the secondary side controller. The secondary side controller can engage the active clamp FET only during the secondary side FET on period. In these embodiments, the secondary side controller drives the active clamp FET, the primary side FET, and the secondary side FET. The secondary side control active clamp FET is switched in phase with the secondary side FET. The secondary side controller can also have access to electrical parameters on the secondary side (e.g., line / load information on the secondary side) and can use these parameters to determine whether it is beneficial to turn on the active clamp FET. The secondary side controller can delay the turn on of the active clamp FET to avoid cross conduction or can turn off the active clamp FET early to prevent the active clamp FET from staying on for too long. If the secondary side controller determines that it is beneficial to engage the active clamp FET, it can send a control signal across the pulse transformer to the active clamp FET to turn on the active clamp FET. As described above, the primary side controller cannot determine whether it is possible that it is beneficial to engage the active clamp FET or determine the duration of switching of the active clamp FET (e.g., the duration of the active clamp FET on and the duration of the active clamp FET off) which can result in additional losses due to unnecessary gate switching. However, the secondary side controller can determine whether it is possible that it is beneficial to engage the active clamp FET or determine the duration of switching of the active clamp FET including the duration of the active clamp FET on and the duration of the active clamp FET off.

[0026] The implementations described herein can address the challenges mentioned above and other challenges by providing a power supply device compatible with a serial bus, such as a serial bus power delivery (SBPD) device with a power control analog subsystem having hardware, firmware, or any combination to communicate information including control signals from a secondary side controller to intelligently drive active clamp FETs from the secondary side across a galvanic isolation barrier. In one implementation, the galvanic isolation barrier can be provided by a pulse transformer. In other implementations, the galvanic isolation can be provided by optocouplers, capacitive isolators, etc. The SBPD (also referred to herein as a "source device") can be a USB compatible power supply device. The implementations described herein can also be implemented in other types of power adapters, power converters, power delivery circuits, etc.

[0027] Figure 1is a block diagram of a secondary controlled converter 100 with secondary controlled active clamp control with a current isolation barrier from the secondary side to the primary side according to one embodiment. In some embodiments, the secondary controlled converter 100 can be a secondary controlled flyback converter. The secondary controlled flyback converter 100 can be part of an AC-DC power adapter device. The secondary controlled flyback converter 100 includes a rectifier 102 (e.g., a full bridge rectifier) coupled between AC input terminals 104 and a rectified DC line 106 (VIN), a flyback transformer 108 including a primary winding coupled to the rectified DC line 106, a primary side power switch 110 (e.g., a primary side FET, power FET, or primary FET), a secondary side power switch 112 (e.g., a secondary side FET, power FET, or secondary FET), an active clamp FET 138, a primary side controller 114, and a secondary side controller 116. The rectified DC line 106 is coupled to a first end of the primary winding of the flyback transformer 108. VIN is the voltage on the rectified DC line 106 after the rectifier 102. A second end of the primary winding is coupled to a primary drain of the primary side FET 110 and a source of the active clamp FET 138. A source node of the active clamp FET 138 is coupled to the primary drain of the primary side FET 110. A drain node of the active clamp FET 138 is coupled to a DC blocking capacitor 140. Further, a gate node and the source node of the active clamp FET 138 are coupled to a pulse transformer 136, which is also coupled to the secondary side controller 116. A first end of a secondary winding of the flyback transformer 108 is coupled to a direct current (DC) output line 118 (VBUS IN), and a second end of the secondary winding is coupled to a secondary drain (SR_Drain) of the secondary side FET 112. In alternative embodiments, the DC blocking capacitor can be coupled between a drain node of the primary side FET 110 and a source node of the active clamp FET 138. In this configuration, a drain node of the active clamp FET 138 is directly coupled to the rectified DC line. VBUS IN is the voltage on the DC output of the flyback transformer 108. SR_Drain is a drain node of the secondary side FET 112. The DC output line 118 and the secondary side FET 112 are coupled to a DC output terminal 120.

[0028] The secondary controlled flyback converter 100 is used for AC-DC conversion with galvanic isolation between the input and any output. The secondary controlled flyback converter 100 uses an inductor separate from the flyback transformer 108, which has a galvanic isolation barrier 122 between the primary side and the secondary side. When the primary side power switch 110 (primary side FET) is closed, the primary side of the flyback transformer 108 is connected to the input voltage source. In this embodiment, the primary side of the flyback transformer 108 is coupled to the rectifier 102. As the primary current and magnetic flux in the flyback transformer 108 increase, energy is stored in the transformer core of the flyback transformer 108. The voltage induced in the secondary winding is negative and is blocked by the secondary rectifier 112. When the primary side power switch 110 (primary side FET) is opened, the primary current and magnetic flux decrease. The secondary voltage is positive, enabling current to flow out of the flyback transformer 108. The energy stored in the transformer is transferred to the output load. When the primary switch (e.g., primary side FET) is engaged, an output capacitor can be used to provide energy to the output load. Thus, the flyback transformer 108, based on control of the primary side power switch 110, can store energy and transfer energy to the output of the secondary controlled flyback converter 100. It should also be noted that the secondary controlled flyback converter 100 can include other components in the input stage, output stage, or both. For example, a bulk capacitor can be coupled between the output of the rectifier 102 and a ground node. During operation, the AC input power is rectified and filtered by the rectifier 102 (bridge rectifier) and the bulk capacitor. This results in a DC high voltage bus connected to the primary winding of the flyback transformer 108. Similarly, in the output stage, the secondary winding power is rectified and filtered, such as by diodes, capacitors, output LC filters, etc., to reduce the output voltage ripple. Other output voltages can also be achieved by adjusting the turns ratio of the flyback transformer and the output stage. In some embodiments, other converters, such as switching converters, etc., can be used instead of the flyback transformer.

[0029] The secondary controlled flyback converter 100 operates as an isolated power converter. Two popular control schemes are voltage mode control and current mode control. Both control schemes use a signal related to the output voltage. An optocoupler or a pulse transformer can be coupled to the secondary side controller 116 and can send a signal to the primary side controller 114 to indicate the output voltage, such as described in more detail below. The optocoupler or pulse transformer can be used to achieve tight voltage and current regulation.

[0030] In the depicted embodiment, the secondary-side controller 116 is configured to control the active clamp FET 138 on the primary side, the primary-side FET 110 on the primary side, and the secondary-side FET 112 on the secondary side. In one embodiment, the primary-side controller 114 is configured to receive the signal 126 from the secondary-side controller 116 across the current isolation barrier 124. The primary-side controller 114 applies a pulse signal 128 to the primary-side FET 110 in response to the signal 126 to turn the primary-side FET 110 on and off.

[0031] In one embodiment, the secondary controlled flyback converter 100 includes a pulse transformer 130 coupled between the primary-side controller 114 and the secondary-side controller 116. The primary-side controller 114 is configured to receive the signal 126 from the secondary-side controller 116 as one or more pulses via the pulse transformer 130. The primary-side controller 114 can include a receiver and a pulse generator 132 to receive the pulse signal 128 from the secondary-side controller 116 across the current isolation barrier 124. The receiver and the pulse generator 132 can vary the primary-side on pulse based on an output of the flyback transformer 108 (e.g., an error amplifier (EA) output). The primary-side FET 110 is turned on using the primary-side on pulse. In the case of a higher EA voltage, a wider pulse width modulation (PWM) pulse is sent from the secondary-side controller 116 via the pulse transformer 130, which results in a wider primary on pulse being used. The primary-side controller 114 can also include a gate driver 134 coupled to the receiver and the pulse generator 132 to drive the gate of the primary-side FET 110. As described herein, the on pulse and the off pulse can have a fixed width or a variable width. In one embodiment, the receiver and the pulse generator 132 can include a PWM circuit. Alternatively, the receiver and the pulse generator 132 can use other types of circuits to receive the pulses across the current isolation barrier 124.

[0032] In one embodiment, to apply the pulse signal 128 to the primary-side FET 110, the primary-side controller 114 is configured to receive an on pulse (PTDRV) from the secondary-side controller 116. The primary-side controller 114 applies the on pulse to the gate of the primary-side FET 110 via the gate driver 134. The on pulse makes the primary-side FET 110 primary drain low (e.g., a first voltage level corresponding to a first state or representing a digital value of one). Subsequently, the primary-side controller 114 receives an off pulse from the secondary-side controller 116 and applies the off pulse to the gate of the primary-side FET 110 via the gate driver 134. The off pulse makes the primary-side FET 110 primary drain high (e.g., a second voltage level corresponding to a second state or representing a digital value of zero).

[0033] In one embodiment, the secondary side controller sends control signals to the secondary side FET 112 through the input line 142 and sends the same control signals to the active clamp FET 138 via the pulse transformer 136. The active clamp FET 138 and the secondary side FET 112 turn on in phase in response to receiving a turn-on pulse of the control signal. Subsequently, the active clamp FET 138 and the secondary side FET 112 turn off in response to receiving a turn-off pulse of the control signal. As described herein, the turn-on and turn-off pulses of the control signal can have a fixed width or a variable width.

[0034] In one embodiment, the secondary side controller 116 includes a programmable driver 133 for generating the signal 126 to be sent to the primary side controller 114 through the current isolation barrier 124. Using the programmable driver 133, the secondary side controller is able to send any combination of 0s and Is with a specific pattern (protocol) from the secondary side controller 116 to the primary side controller 114 without the need for clock synchronization. In one embodiment, the secondary side controller 116 includes a state machine for synchronizing each function of the primary side controller 114 to be programmed (e.g., calibrated, trimmed, etc.). The secondary side controller 116 can store other information, such as user-defined settings. For example, user-defined settings related to the primary side functions, such as over-voltage (OV), under-voltage (UV), over-current (OC), short-circuit detection, over-temperature (OT), line voltage, peak current limit, etc. can be stored in a non-volatile memory of the secondary side controller 116. The firmware of the secondary side controller 116 can pass this information to the primary side controller 114 in a similar manner at an appropriate time, such as at start-up or later during operation of the converter at a particular time.

[0035] In one embodiment, the secondary side controller 116 includes a programmable driver 133 for generating the signal 142 to be sent to the active clamp FET 138 through the pulse transformer 136. Using the programmable driver 133, the secondary side controller is able to send any combination of 0s and Is with a specific pattern (protocol) from the secondary side controller 116 to the active clamp FET 138. In one embodiment, the secondary side controller 116 includes a state machine for synchronizing each function of the primary side controller 114 to be programmed (e.g., calibrated, trimmed, etc.). The secondary side controller 116 can store other information, such as user-defined settings. For example, user-defined settings related to controlling the active clamp FET 138 can be stored in a non-volatile memory of the secondary side controller 116. The firmware of the secondary side controller 116 can pass this information to the active clamp FET in a similar manner at an appropriate time, such as at start-up or later during operation of the converter at a particular time.

[0036] like Figure 1 As shown, the secondary-side controller 116 can transmit control signals for controlling all switches (e.g., primary-side FET 110, active clamp FET 138, and secondary-side FET 112). For example, a first control signal is transmitted to the primary-side controller 114 via pulse transformer 130 through current isolation barrier 124. A second control signal is transmitted by the secondary-side controller to the secondary-side FET 112. The same second control signal is transmitted to the active clamp FET 138 via pulse transformer 136. Additional details of the programmable driver 133 are described below regarding... Figure 2 Describe it.

[0037] Figure 2 This is a block diagram of a secondary-controlled flyback converter 200 according to one embodiment, having a secondary-side controller 216 that controls an active clamping FET 238 on the primary side via a current isolation barrier 224. Although not all components of the secondary-controlled flyback converter 200 are shown, the secondary-controlled flyback converter 200 is similar to... Figure 1 The secondary controlled flyback converter 100 is similar, as indicated by similar reference numerals. In one embodiment, in order to control the active clamp FET 238, the secondary-side controller 216 can send pulses, such as via pulse transformer 230 across current isolation barrier 224, to the active clamp FET 238.

[0038] The secondary-side controller 216 includes a signal generator 231 for generating a signal (e.g., a pulse) for controlling at least the active clamp FET 238 via the pulse transformer 230. For example, the signal generator 231 may generate a signal for controlling the primary-side FET (…). Figure 2 A first signal (not shown) and a second signal for controlling the active clamp FET 238. For example, the signal generator 231 may include pull-up transistors and pull-down transistors. The pull-up transistors and pull-down transistors may be controlled by the control logic or firmware of the secondary-side controller 216. During normal mode, the signal generator 231 can generate and output a square wave signal. A capacitor 240 is coupled between the signal generator 231 and the pulse transformer 230. The combination of resistor 241 and capacitor 240 generates a positive pulse at the positive transition (i.e., rising edge) of the square wave signal and a negative pulse at the negative transition (i.e., falling edge) of the square wave signal. The positive and negative edges are transmitted to the primary-side controller 214 via the pulse transformer 230. The primary-side controller 214 receives the positive and negative edges to generate a signal for enabling the primary-side power switch (…). Figure 2 (Not shown in the image) PWM pulses for turning on and off. An example waveform of the square wave generated by signal generator 231 is shown below. Figure 1The example waveforms of the positive and negative pulses generated by the capacitor are shown in FIG. 3B. The example waveforms of the positive and negative pulses generated by the capacitor are shown in FIG. 3B. Figure 1

[0039] The secondary-side controller 216 can generate a square wave signal 232 during normal operation (e.g., in a normal operating mode). In this case, the secondary-side controller 216 can switch the resistor 233 between the pull-up transistor and the capacitor 240. It should be noted that the resistor 233 can be any type of resistive element. Thus, the signal generator 231 generates a sawtooth wave signal 234 having a slow rising edge and a faster falling edge than the slow rising edge. Given the edges of the sawtooth wave signal 234, the capacitor 240 does not generate a positive pulse for each pulse in the sawtooth wave signal 234, resulting in a pulse signal 236 having two or more consecutive negative pulses. The consecutive negative pulses of the pulse signal 236 are communicated to the primary-side controller 214 via the pulse transformer 230. The primary-side controller 214 receives the consecutive negative pulses to detect that the secondary-side controller 216 is communicating information to the primary-side controller 214 to control the active clamp FET 238. Although the pulse signal 336 includes two consecutive negative pulses (i.e., without any intervening positive pulse) - which can represent two consecutive "0" values sent across the current isolation barrier 224, in other embodiments, other specific patterns can be generated by the secondary-side controller 216 and detected by the primary-side controller 214. For example, the secondary-side controller 216 can extend the signal generator 231 to generate two or more consecutive "1" values or even a pattern of 0s and Is to communicate information from the secondary-side controller 216 to the primary-side controller 214 to control the active clamp FET 238. Other information can include a start-up mode, a stop mode, a soft fault requiring a soft start operation, a soft fault requiring transmission of minimum power, etc. Similarly, a resistor in series with a pull-down device can be used to generate consecutive Is. In another embodiment, the secondary-side controller 216 can generate a PWM signal to be transmitted by the secondary-side controller 216. That is, the secondary-side controller 216 can generate a PWM signal to the pulse transformer 230 to be communicated across the current isolation barrier. Alternatively, the PWM signal can be communicated directly to the primary-side controller or the active clamp FET.

[0040] ​In some cases, two consecutive 0s require two "-ve" pulses, thus eliminating the need for any fast clock synchronization on the primary side. In the disclosed implementation, two consecutive 0s can be initiated by firmware after confirming a fault requiring a system shutdown. Pull-up and pull-down transistors can be controlled to perform a programmable slow pull-up at the input of pulse transformer 230, followed by a sudden pull-down, generating a "-ve" edge without a "+ve" edge. Similarly, another programmable slow pull-up followed by a sudden pull-down will generate another "-ve" edge. It should be noted that a slow pull-up can be implemented by switching resistor 233 to the pull-up path. Alternatively, a slow pull-up can be implemented using a current source-based pull-up.

[0041] like Figure 2 As shown, the secondary-side controller 216 sends two consecutive 0s in pulse signal 236, and the primary-side controller 214 receives two consecutive 0s in pulse signal 226. The primary-side controller 214 may include circuitry for detecting two consecutive 0s in pulse signal 226, such as… Figure 3 As shown. Alternatively, the primary-side controller 214 may include circuitry for detecting other modes, such as information transmitted by the secondary-side controller 216.

[0042] Figure 3 This is a block diagram of a primary-side controller circuit 300 for detecting signal patterns from a secondary-side controller for driving an active clamp FET 338, according to one embodiment. Circuit 300 includes a first flip-flop 302, a second flip-flop 304, and an OR gate 306. The first flip-flop 302 receives a first input value 301 (e.g., 1'b1) that initiates programming if propagated through the first flip-flop 302 and the second flip-flop 304. When the first flip-flop 302 is activated by a 0 pulse in the pulse signal received by the primary-side controller (… Figure 2 When the overshoot pulse 307 corresponding to the negative pulse 236 shown is timed, the second trigger 304 receives the second input value 303 from the output of the first trigger 302. The 0 pulse 307 is marked as the fb_off signal, which is the output of the pulse receiver circuit. When the pulse changes from negative to positive, the output of the pulse receiver circuit will be high. Similarly, the fb_on signal (signal 309) is the output of the pulse receiver circuit. When the pulse changes from positive to positive, the output of the pulse receiver circuit will be high. When the second trigger 304 is timed by the 0 pulse 226 (…) in the pulse signal received by the primary-side controller… Figure 2The output value 305 can be output by the second flip-flop 304 when the rising pulse 307 corresponding to the negative pulse in the primary controller input from the pulse transformer 230 is timed. However, if the primary side controller receives a middle rising pulse (positive pulse) at the primary controller input from the pulse transformer 230 between the two pulses 307 corresponding to the high pulse 309, the first flip-flop and the second flip-flop are cleared. For example, when the or gate 306 receives the high pulse 309 or the reset signal 311, the or gate 306 can output a reset (or clear) signal to the clear input of both the first flip-flop 302 and the second flip-flop 304. Although Figure 3 One embodiment of the circuit 300 for detecting two consecutive zeros is shown, but in other embodiments, the circuit 300 can include different logic or circuit components for detecting two consecutive zeros or other specific patterns in the pulse signals received by the primary side controller across the current isolation barrier.

[0043] In this embodiment, the output value 305 can initiate programming of the primary side controller to control the active clamp FET 338. For example, the primary side controller 114 can receive a pulse to switch the active clamp FET 338.

[0044] In another embodiment, an AC-DC power adapter device includes a flyback transformer coupled between AC terminals and DC terminals. The flyback transformer converts AC power on the AC terminals to DC power on the DC terminals with current isolation between the AC terminals and the DC terminals. The AC-DC power adapter device also includes a primary side controller and a secondary side controller, both coupled to the flyback transformer. The flyback transformer is coupled to a primary side power switch (e.g., a primary side FET), a secondary side power switch (e.g., a secondary side FET), and an active clamp FET disposed on a primary side of the flyback transformer. The AC-DC power adapter device also includes a first pulse transformer with a current isolation barrier between the primary side controller and the secondary side controller. The AC-DC power adapter device also includes a second pulse transformer with a current isolation barrier between the secondary side controller and the active clamp FET. The secondary side controller controls the primary side FET via the first pulse transformer and the primary side controller. The secondary side controller controls the secondary side FET and the active clamp FET in phase (e.g., the active clamp FET is turned on when the secondary side FET is turned on). The secondary side controller controls the active clamp FET via the second pulse transformer.

[0045] In another embodiment, the primary side controller includes a pulse receiver and a gate driver, such as those described above. The pulse receiver receives signals from the secondary side controller across a galvanic isolation barrier, and the gate driver drives signals at the gate of the primary side FET to turn the primary side FET on and off. In another embodiment, the AC-DC power adapter device further includes a rectifier coupled between the AC source and the AC line (Vin). The AC line is coupled to a first end of the active clamp FET and the primary winding of the flyback transformer. A second end of the primary winding is coupled to the primary drain of the primary side FET. A first end of the secondary winding of the flyback transformer is coupled to the DC output line (VBUS), and a second end of the secondary winding is coupled to the secondary drain of the secondary side FET. A bulk capacitor is coupled between the AC line and a ground node. To apply pulse signals to the primary side FET, the primary side controller is configured to: receive a turn-on pulse from the secondary side controller; apply the turn-on pulse to the gate of the primary side FET, which turns the primary drain of the primary side FET high; receive a turn-off pulse from the secondary side controller; and apply the turn-off pulse to the gate of the primary side FET, which turns the primary side FET low.

[0046] Figure 4A is a block diagram of active clamp N-channel field effect transistor (NFET) circuitry controlled from the secondary side by the secondary side controller 116, which can send control signals through the pulse transformer 136, described above with reference to Figure 1 In one embodiment, the active clamp FET 404a can be an NFET. The active clamp FET 404a is coupled to the flyback converter 402 and a capacitor 408, which acts as a DC block in the active clamp FET circuitry. In this embodiment, the active clamp NFET 404a has a floating ground (e.g., the source node of the active clamp FET 404a is not connected to a reference voltage). The active clamp NFET 404a turns on with a positive gate-source voltage and this can be implemented in most circuits. The control signals sent from the secondary side controller 116 via the pulse transformer 136 are input to the active clamp NFET 404a through the input line 142. Since the source node of the active clamp NFET 404a is a floating node, the active clamp NFET 404a can be driven by an optocoupler, a capacitive isolator, a pulse transformer, as described herein.

[0047] Figure 4B is a block diagram of active clamp P-channel field effect transistor (PFET) circuitry controlled from the secondary side by the secondary side controller 116, which can send control signals through the pulse transformer 136, described above with reference to Figure 1A description is made. Using the pulse transformer 136, the secondary side controller 116 can send control signals through a galvanic isolation barrier. In other embodiments, the secondary side controller 116 can send control signals directly to the PFET circuitry instead of through a galvanic isolation barrier. The active clamp FET 404b is coupled to the flyback converter 402 and the capacitor 408, which serves as a DC block in the active clamp circuitry. In this embodiment, the active clamp PFET 404b has a reference to ground (e.g., the source node of the active clamp FET is connected to a reference voltage). Since the ground of the active clamp PFET 404b is not floating, this circuitry is less susceptible to electromagnetic interference (EMI) issues.

[0048] In other embodiments, the active clamp can be another type of transistor, such as an insulated gate bipolar transistor (IGBT), etc.

[0049] Figure 5is a schematic diagram of a USB-PD power adapter 500 for sending control signals from a secondary side controller 516 to control active clamp FETs 538 of the primary side through a galvanic isolation barrier according to one embodiment. Instead of opto-isolator feedback, the USB-PD power adapter 500 controls the primary side switch 510 (e.g., primary side FET 510) across the isolation barrier via a first pulse transformer 530, flyback transformer 508, or both. The USB-PD power adapter 500 includes a primary IC controller 514 and a secondary IC controller 516. The secondary IC controller 516 of the USB-PD power adapter 500 also controls active clamp FETs 538 via a second pulse transformer 536. The secondary IC controller 516 can be disposed in a chip package and includes a USB-PD subsystem configured according to the techniques described herein for gate driver control. The secondary IC controller 516 is configured to negotiate a PD contract with a consumer device (not shown) attached to a USB Type-C port 540 and control the required VBUS voltage output from the flyback transformer 508 through an output pin (“PWM_DRV”). The USB Type-C port 540 is typically associated with a Type-C plug, but it should be understood that, in various embodiments, the USB Type-C port can alternatively be associated with a Type-C receptacle. The flyback transformer 508 is coupled to a rectified DC power supply, and the output can be coupled to a secondary side FET 512 (e.g., SR_FET 512). VBUS IN is regulated by an error amplifier connected to a compensation network 550. The compensation network 550 can be a resistor-capacitor (RC) circuit specific to the design of the USB-PD power adapter 500. The compensation network 550 can be coupled to receive a feedback signal from a first output pin (“FB”) of the secondary IC controller 516. The compensation network 550 can also be coupled to a second output pin (“EA_out”) and a third output pin (“CC_Comp”). The flyback transformer 508 can be coupled to a bulk capacitor 533 and an active clamp circuit 538 and a DC blocking capacitor 541. The USB-PD power adapter 500 can also include a pulse transformer 530 (or other feedback control mechanism) for communicating information across the isolation barrier 524.

[0050] The secondary IC controller 516 is coupled to the VBUS line 511 and is configured to control the operation and state of the power switch by providing a control signal to the gate of the power switch, such as the power switch 520, when a fault condition is detected. The VBUS line 511 includes a provider switch 520 configured as an on / off switching device controlled by a signal from an output pin (“VBUS_Control”) in the secondary IC controller 516. The power switch 520 can correspond to the provider FET described herein. On one side of the provider switch 520, the power supply node 505 on the VBUS line 511 is coupled to a second winding of the flyback transformer 508, which is coupled to a bulk capacitor 535 configured to remove the AC component of the power signal. The power supply node 505 is coupled to an input pin (“VBUS_IN”) of the secondary IC controller 516. On the other side of the power switch 520, the output node 507 on the VBUS line 511 is coupled to the USB Type-C port 540. The output node 507 is coupled to another input pin (“VBUS_C”) of the secondary IC controller 516. The GND terminal 542 of the USB Type-C port 540 is coupled to the secondary side FET 512.

[0051] In operation, the direction of power flow on the VBUS line 511 is from the flyback transformer 508 to a consumer device, such as a laptop computer (not shown), attached to the USB Type-C port 540. In the case of a negotiated PD contract with the consumer device, the secondary IC controller 516 turns on the provider switch 520 for providing power to the consumer device at the negotiated voltage level and / or current level. When the PD contract is dynamically renegotiated to lower the VBUS voltage and / or current, for example, when the consumer device finishes charging its battery and now only needs power to operate, a voltage transition from high to low on the VBUS line 511 can be required.

[0052] Upon detection of a fault condition, a control signal can be sent to turn off the provider switch 520, thereby disconnecting the USB Type-C port 540 from the flyback transformer 508. The provider switch 520 is turned off by driving the output of VBUS_Control to zero. This disconnection can be caused by an overvoltage condition, an overcurrent condition, or other conditions that can require the USB Type-C port 540 to be disconnected from the flyback transformer 508 to protect the circuitry coupled to the USB Type-C port 540.

[0053] In another implementation, an auxiliary circuit 570 can be coupled to the primary IC controller 514. An auxiliary output pin ("AUX_IN") and an overvoltage protection auxiliary pin ("OVP_AUX") are coupled to the auxiliary circuit 570. Once start-up is complete, the auxiliary circuit 570 can operate to protect the overvoltage of the VBUS IN 511 and also provide power (AUX IN) to the primary IC controller 514. As described above, the USB-PD power adapter 500 allows for communication across the isolation barrier 524, the isolation barrier 522, the isolation barrier of the pulse transformer 536, or in a manner similar to that described above with respect to Figure 1 In a manner similar to that described with respect to FIG. 4, the secondary IC controller 516 can communicate with the primary IC controller 514. In particular, the PWM driver circuit of the secondary IC controller 516 can output a signal on an output pin ("PWM DRV") to transmit information across the isolation barrier 524 via the pulse transformer 530. As described herein, the PWM driver circuit can be other driver circuits that produce pulses on an output pin to transmit information across the isolation barrier 524. The primary IC controller 514 can include a detection circuit that receives the signal on an input pin ("Pulse In") and detects when the secondary IC controller 516 is transmitting information.

[0054] As described above, the USB-PD power adapter 500 allows for communication across the isolation barrier 524, the isolation barrier of the pulse transformer 536, or in a manner similar to that described above with respect to Figure 1 In a manner similar to that described with respect to FIG. 4, the secondary IC controller 516 can communicate with the primary IC controller 514. In particular, the SR driver circuit of the secondary IC controller 516 can output a signal on an output pin ("SR DRV") to transmit a control signal across the isolation barrier of the pulse transformer 536. As described herein, the SR driver circuit can be other driver circuits that produce pulses on an output pin to transmit information across the isolation barrier of the pulse transformer 536. The control signal transmitted across the pulse transformer 536 can be used to control the active clamp FET 583.

[0055] In another embodiment, the AC-DC power adapter device includes a flyback converter (with a flyback transformer) or an isolated power converter coupled between the AC terminals and the DC terminals. The flyback transformer converts AC power on the AC terminals to DC power on the DC terminals with galvanic isolation between the AC terminals and the DC terminals. The AC-DC power adapter device also includes a primary side controller coupled to the flyback transformer and a secondary side controller coupled to the flyback transformer. A primary side power switch (also referred to as a primary side FET or primary FET) and an active clamp FET are coupled to a primary winding of the flyback transformer and the primary side controller. A secondary side power switch (also referred to as a secondary side FET or secondary FET) is coupled to a secondary winding of the flyback transformer and the secondary side controller. The primary side controller is configured to receive a first signal from the secondary side controller across a galvanic isolation barrier and apply a second signal to the primary side power switch to turn the primary side power switch on and off in response to the first signal. Alternatively, the primary side controller is configured to receive the first signal directly from the secondary side controller, rather than across the galvanic isolation barrier. The secondary side controller is also configured to communicate information to the primary side controller via a first pulse transformer coupled between the primary side controller and the secondary side controller. The secondary side controller is also configured to send a control signal across a second pulse transformer coupled between the secondary side controller and the active clamp FET to control the active clamp FET. The control signal sent by the secondary side controller is the same control signal used to control the secondary side FET. Also, the active clamp FET (ACF) control signal can be an independent signal, where the duration of the active clamp FET can be controlled independent of the control signal sent to the secondary side FET. That is, a first control signal can control the switching of the active clamp FET (e.g., the duration of the active clamp FET being on and the duration of the active clamp FET being off), while a second control signal can control the secondary side FET independently. In another embodiment, all three FETs can be driven by three independent control signals.

[0056] In another embodiment, the primary side controller includes a pulse receiver and a driver. The pulse receiver receives a first signal from the secondary side controller across a galvanic isolation barrier. The first signal includes a first turn-on pulse to turn the primary side power switch on and a first turn-off pulse to turn the primary side power switch off. In response, the driver coupled to the pulse receiver and the primary side power switch (e.g., the primary side FET) applies the first turn-on pulse and the first turn-off pulse to the primary side power switch.

[0057] In another implementation, an AC-DC power adapter device includes a first pulse transformer coupled between a primary side controller and a secondary side controller. The primary side controller is configured to receive a first signal from the secondary side controller as one or more pulses via the first pulse transformer. As described herein, the primary side controller can detect when the secondary side controller is transmitting information via the first pulse transformer. The AC-DC power adapter device also includes a second pulse transformer coupled between the secondary side controller and an active clamp FET. The secondary side controller sends a second signal across the second pulse transformer to control the active clamp FET. The secondary side controller sends the same second signal to control the secondary side FET and the active clamp FET to switch in phase.

[0058] The implementations described herein can be implemented in a power delivery system such as a serial bus compatible power supply device. Examples of serial bus compatible power supply devices can include serial bus power delivery (SBPD) devices, USB compatible power supply devices, and the like. In some implementations, a SBPD device is a USB-PD device that is compatible with the USB-PD standard or more generally with the USB standard. For example, a SBPD device can be used to provide an output voltage (e.g., Vbus c, supply voltage) based on an input voltage (e.g., Vbus in, supply voltage). A SBPD device can include various implementations described herein to facilitate communication between a primary side controller and a secondary side controller. A SBPD device can include a power converter (e.g., an AC-DC converter) and a power control analog subsystem (e.g., a USB-PD controller). The power control analog subsystem can include circuitry, functionality, or both for transmitting information across a galvanic isolation barrier as described herein. The information can include information for different functions such as OV, UV, OCP, SCP, PFC, SR, and the like. The information can include fault information for any of these different functions.

[0059] In other implementations, a SBPD device is connected to a power source such as a wall outlet power source that provides AC power. In other implementations, the power source can be a different power source such as a battery and can provide DC power to the SBPD device. A power converter can convert power received from the power source (e.g., convert received power to Vbus in). For example, a power converter can be an AC-DC converter and convert AC power from the power source to DC power. In some implementations, a power converter is a flyback converter that provides galvanic isolation between an input (e.g., primary side) and an output (e.g., secondary side) such as a secondary controlled flyback converter.

[0060] In some implementations, the SBPD device provides Vbus c to the dissipator device (e.g., via a communication channel (CC) that specifies a particular output voltage and possibly output current). The SBPD device can also provide the dissipator device with access to a ground potential (e.g., ground). In some implementations, the provision of Vbus c is compatible with the USB-PD standard. The power control analog subsystem can receive Vbus in from the power converter. The power control analog subsystem can output Vbus in. In some implementations, the power control analog subsystem is a USB Type-C controller that is compatible with the USB Type-C standard. The power control analog subsystem can provide a system interrupt in response to Vbus in and Vbus c. TM

[0061] In some implementations, any of the components of the SBPD device can be part of an IC, or alternatively, any of the components of the SBPD device can be implemented in its own IC. For example, the power converter and the power control analog subsystem can each be a discrete IC with separate packaging and pin configurations.

[0062] In some implementations, the SBPD device can provide a complete USB Type-C and USB Power Delivery port control solution for laptops, dongles, monitors, docking stations, power adapters, vehicle chargers, power banks, mobile adapters, and the like. TM

[0063] Implementations using isolation or level shifters can require some driver circuitry. The driver circuitry can be as simple as driving a capacitor coupled controller or optocoupler using the PWM output from the secondary side controller 516. When driving a pulse transformer, the driver circuitry can be a complex structure.

[0064] In some implementations, the secondary controlled flyback converter can be a single-ended forward converter. In some implementations, the feed forward information on the secondary side can be used to limit the maximum duty cycle that can be passed to the primary side FET 510 and active clamp FET 538. The maximum duty cycle can vary with line voltage. The line voltage is sourced from the transformer winding 508. In another implementation, the line voltage can also be obtained from the SR_Drain node on the source pin of 512.

[0065] Figure 6 ​​is a block diagram illustrating a system 700 for a USB device with secondary controlled active clamp FET for use in USB power delivery according to some embodiments. The system 700 can include a peripheral subsystem 710 that includes several components for use in USB power delivery (USB-PD). The peripheral subsystem 710 can include a peripheral interconnect 711 that includes a clock module, a peripheral clock (PCLK) 712 for providing clock signals to various components of the peripheral subsystem 710. The peripheral interconnect 711 can be a peripheral bus such as a single or multi-level advanced high-performance bus (AHB), and can provide a data and control interface between the peripheral subsystem 710, the CPU subsystem 730, and system resources 740. The peripheral interconnect 711 can include controller circuitry such as a direct memory access (DMA) controller that can be programmed to transfer data between peripheral blocks without input, control, or loading of the CPU subsystem 730.

[0066] The peripheral interconnect 711 can be used to couple components of the peripheral subsystem 710 to other components of the system 700. Coupled to the peripheral interconnect 711 can be a plurality of general purpose input / outputs (GPIOs) 715 for sending and receiving signals. The GPIOs 715 can include circuitry configured to implement various functions such as pull-up, pull-down, input threshold selection, input and output buffer enable / disable, single multiplexing, etc. Other functions can still be implemented by the GPIOs 715. One or more timers / counters / pulse width modulators (TCPWMs) 717 can also be coupled to the peripheral interconnect and include circuitry for implementing timing circuitry (timers), counters, pulse width modulators (PWM) decoders, and other digital functions that can operate on I / O signals and provide digital signals to system components of the system 700. The peripheral subsystem 710 can also include one or more serial communication blocks (SCBs) 719 for implementing a serial communication interface such as I2C, serial peripheral interface (SPI), universal asynchronous receiver / transmitter (UART), controller area network (CAN), clock extension peripheral interface (CXPI), etc.

[0067] For USB power delivery applications, the peripheral subsystem 710 can include a USB power delivery subsystem 720 coupled to the peripheral interconnect and including a set of USB-PD modules 721 for use in USB power delivery. The USB-PD modules 721 can be coupled to the peripheral interconnect 711 through the USB-PD interconnect 623. The USB-PD modules 721 can include: an analog-to-digital conversion (ADC) module for converting various analog signals to digital signals; an error amplifier (AMP) for regulating the output voltage on the VBUS line according to a PD contract; a high voltage (HV) regulator for converting a supply voltage to a precise voltage (such as 3.5V to 5V) to the power system 700; a low-side current sense amplifier (LSCSA) for accurately measuring load current; an over-voltage protection (OVP) module and an over-current protection (OCP) module for providing over-current and over-voltage protection on the VBUS line with configurable thresholds and response times; one or more gate drivers for external power field effect transistors (FETs) for use in USB power delivery in provider and consumer configurations; and a communication channel PHY (CC BB PHY) module for supporting communication on the C-type communication channel (CC) line. The USB-PD modules 721 can also include: a charger detection module for determining the presence of a charging circuit and coupling it to the system 700; and a VBUS discharge module for controlling discharge of voltage on the VBUS. The discharge control module can be configured to couple to a supply node on the VBUS line or an output (power dissipater) node on the VBUS line and discharge the voltage on the VBUS line to a desired voltage level (i.e., a voltage level negotiated in a PD contract). The USB power delivery subsystem 720 can also include pads 727 for external connections and electrostatic discharge (ESD) protection circuitry 729 that can be required on the C-type port. The USB-PD modules 721 can also include a communication module for retrieving and communicating information, such as control signals from a secondary side controller to a primary side controller. In one implementation, the USB-PD modules 721 include an active clamp control module in the secondary side controller to control an active clamp FET disposed on the primary side (e.g., the primary side of an AC-DC flyback converter).

[0068] The GPIO 715, TCPWM 717, and SCB 719 can be coupled to an input / output (I / O) subsystem 750, which can include a high-speed (HS) I / O matrix 751 coupled to a plurality of GPIOs 753. The GPIO 715, TCPWM 717, and SCB 719 can be coupled to the GPIOs 753 through the HS I / O matrix 751.

[0069] The system 700 can also include a central processing unit (CPU) subsystem 730 for processing commands, storing program information and data. The CPU subsystem 730 can include one or more processing units 731 for executing instructions and reading from and writing to memory locations in a plurality of memories. The processing units 731 can be processors suitable for operation in an integrated circuit (IC) or system on a chip (SOC) device. In some embodiments, the processing units 731 can be optimized for low power operation with a large number of gated clocks. In this embodiment, various internal control circuits can be implemented for operation of the processing units in various power states. For example, the processing units 731 can include a wake-up interrupt controller (WIC) configured to wake up the processing units from a sleep state, allowing power to be disconnected while the IC or SOC is in a sleep state. The CPU subsystem 730 can include one or more memories including a flash memory 733 and a static random access memory (SRAM) 735, as well as a read only memory (ROM) 737. The flash memory 733 can be a non-volatile memory (NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. The flash memory 733 can include a read accelerator and can improve access times through integration within the CPU subsystem 730. The SRAM 735 can be a volatile memory configured to store data and firmware instructions accessible by the processing units 731. The ROM 737 can be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during operation of the system 700. The SRAM 735 and the ROM 737 can have associated control circuits. The processing units 731 and the memories can be coupled to a system interconnect 739 to route signals to and from the various components of the CPU subsystem 730 to other blocks or modules of the system 700. The system interconnect 639 can be implemented as a system bus, such as a single or multi-level AHB. The system interconnect 739 can be configured to interface to couple the various components of the CPU subsystem 730 to one another. The system interconnect 739 can be coupled to the peripheral interconnect 711 to provide a signal path between components of the CPU subsystem 730 and components of the peripheral subsystem 710.

[0070] The system 700 can also include a plurality of system resources 740, including a power module 741, a clock module 743, a reset module 745, and a test module 747. The power module 741 can include a sleep control module, a wake interrupt control (WIC) module, a power-on reset (POR) module, a plurality of voltage references (REFs), and a PWRSYS module. In some embodiments, the power module 741 can include circuitry that allows the system 700 to draw power from and / or provide power to external sources and support the controller operating in different power states, such as active, low power, or sleep, at different voltage and / or current levels. In various embodiments, more power states can be implemented as the system 700 throttles back operation to achieve a desired power consumption or output. For example, the secondary side controller can have access to secondary electrical parameters on the secondary side. At low line and light loads, the secondary side controller can determine that it is not beneficial to turn on the active clamp FET. The clock module 743 can include a clock control module, a watchdog timer (WDT), an internal low-speed oscillator (ILO), and an internal master oscillator (IMO). The reset module 745 can include a reset control module and an external reset (XRES) module. The test module 747 can include modules for controlling and entering test modes, as well as test control modules for analog and digital functionality (digital test and analog DFT).

[0071] The system 700 can be implemented in a monolithic (e.g., single) semiconductor die. In other embodiments, various portions or modules of the system 700 can be implemented on different semiconductor dies. For example, the memory module of the CPU subsystem 730 can be on-die or separate. In other embodiments, separate die circuitry can be packaged into a single “chip,” or remain separate and arranged on a circuit board (or in a USB cable connector) as separate components.

[0072] The system 700 can be implemented in a number of application environments to provide USB-PD functionality thereto. In each application environment, an IC controller or SOC implementing the system 700 can be arranged and configured in an electronic device (e.g., a USB-enabled device) to perform operations in accordance with the techniques described herein. In one example implementation, the system 700 can be arranged and configured in a personal computer (PC) power adapter for a laptop computer, notebook computer, or the like. In another example implementation, the system 700 can be arranged and configured in a power adapter (e.g., a wall charger) for a mobile electronic device (e.g., a smartphone, tablet, or the like). In another example implementation, the system 700 can be arranged and configured in a wall outlet configured to provide power through a USB A- and / or C-type port. In another example implementation, the system 700 can be arranged and configured in a car charger configured to provide power through a USB A- and / or C-type port. In yet another example implementation, the system 700 can be arranged and configured in a power bank that can charge and then provide power to another electronic device through a USB A- or C-type port. In other implementations, systems like the system 700 can be configured with the power switch gate control circuitry described herein and can be arranged in various other USB-enabled electronic or electromechanical devices.

[0073] It should be appreciated that systems like the system 700, as implemented on an IC controller or as an IC controller, can be arranged in different applications, which can vary with respect to the type of power source being used and the direction of power transfer. For example, in the case of a car charger, the power source is a car battery that provides DC power, while in the case of a mobile power adapter, the power source is an AC wall outlet. Further, in the case of a PC power adapter, the flow of power transfer is from a provider device to a consumer device, while in the case of a power bank, the flow of power transfer can be bidirectional, depending on whether the power bank is operating as a power provider (e.g., powering another device) or as a power consumer (e.g., charging itself). For these reasons, the various applications of the system 700 should be considered illustrative and not limiting in nature.

[0074] Figure 7 is a waveform chart 800 illustrating the output voltages 802, 808, and 818, the gate voltages 804, 810, and 816 of the primary side FET, and the drain voltages 806, 812, and 818 of the primary side FET as a function of time in various cases in a secondary controlled AC-DC flyback converter, according to one embodiment. The waveform chart 802 illustrates the output voltage of the secondary controlled AC-DC flyback converter. According to one embodiment, during an initial power-up phase (at time t0), the output voltage is at a low voltage level (e.g., 0 V) and the primary side FET is off. At time t1, the primary side FET is turned on and the output voltage begins to increase. At time t2, the output voltage reaches a steady state voltage level (e.g., 5 V) and the primary side FET is turned off. At time t3, the primary side FET is turned on again and the output voltage begins to decrease. At time t4, the output voltage reaches 0 V and the primary side FET is turned off. The waveform chart 804 illustrates the gate voltage of the primary side FET. According to one embodiment, during the initial power-up phase (at time t0), the gate voltage is at a low voltage level (e.g., 0 V) and the primary side FET is off. At time t1, the gate voltage begins to increase and the primary side FET is turned on. At time t2, the gate voltage reaches a steady state voltage level (e.g., 5 V) and the primary side FET is turned off. At time t3, the gate voltage begins to decrease and the primary side FET is turned on again. At time t4, the gate voltage reaches 0 V and the primary side FET is turned off. Figure 7After the initial power-up phase (not visible), the output voltage is constant. The waveform plot 804 shows the gate voltage of the primary side FET. The waveform plot 806 shows the drain voltage of the primary side FET. The next set of waveforms corresponds to voltages of a secondary controlled AC-DC flyback converter operating in continuous conduction mode (CCM). Specifically, the waveform 808 is the output voltage of the secondary controlled AC-DC flyback converter operating in CCM. The waveform 810 shows the gate voltage of the primary side FET, and the waveform 812 shows the drain voltage of the primary side FET operating in CCM. The last set of waveforms corresponds to voltages of a secondary controlled AC-DC flyback converter operating in discontinuous conduction mode (DCM). Specifically, the waveform 814 is the output voltage of the secondary controlled AC-DC flyback converter operating in DCM. The waveform 816 shows the gate voltage of the primary side FET, and the waveform 818 shows the drain voltage of the primary side FET operating in DCM. Referring back to Figure 5 The secondary side controller 516 controls the active clamp FET 538 to turn on synchronously with the secondary side FET 512. The secondary controlled AC-DC flyback converter takes in an AC power source at the AC terminals and outputs a DC power source at the DC terminals. The corresponding output voltages 802, 808, and 814 are constant after the initial power-up phase. The control signal, also referred to as the driver signal or the primary switch pulse width modulation (e.g., based on the variation of the on pulse based on the error amplifier (EA) output), is applied to the gate of the primary side FET. For example, a higher EA voltage results in a wider on pulse. Since the active clamp FET 538, which is also driven by the secondary side controller, utilizes the same control signal used to control the secondary side FET, the leakage energy is recovered by the active clamp FET 538 and recycled onto the DC bus. As shown by the voltages 806, 812, and 818 of the primary side FET drain node, the active clamp FET mitigates the leading edge spike that occurs at every switching cycle when the primary side FET is on. Mitigating the voltage spike helps reduce electromagnetic interference (EMI) in the system and allows a lower rated FET to be used as the main switch FET (primary side FET). In other implementations, the active clamp principle can be used in single-ended forward converters.

[0075] Figure 8 is a flowchart of a method 900 of controlling an active clamp FET of a primary side by a secondary side controller across a galvanic isolation barrier according to one implementation. The method 900 can be performed by processing logic that comprises hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software, firmware, or a combination thereof. In one implementation, a secondary side controller in a secondary controlled AC-DC flyback converter performs the method 900. In another implementation, Figure 1 the secondary side controller 116 of the secondary controlled AC-DC flyback converter 100 performs the method 900. In another implementation,Figure 2 The secondary side controller 216 of FIG. 1 performs the method 900. In another embodiment, Figure 5 The secondary IC controller 516 of FIG. 5 performs the method 900. In another embodiment, Figure 6 The peripheral subsystem 710 of FIG. 7 performs the method 900.

[0076] Referring to Figure 8 The method 900 begins with processing logic generating first and second control signals from a secondary side controller across a galvanic isolation barrier (block 902). The processing logic sends the first control signal to a primary side FET (e.g., a primary side power switch) coupled to a flyback transformer in a secondary controlled AC-DC flyback converter via a first pulse transformer coupled to the secondary side controller and the primary side controller to turn the primary side power switch on and off (block 904). The processing logic sends the second control signal to drive a secondary side FET via a gate driver of the secondary side controller (block 906). The processing logic then sends the same second control signal to turn an active clamp FET on and off via a second pulse transformer coupled to the secondary side controller and the active clamp FET, which is coupled to the flyback transformer and disposed on a primary side of the flyback transformer (block 908).

[0077] In another implementation, the processing logic sends the first control signal and the second control signal across the galvanic isolation barrier as a pulse signal. The first control signal includes pulse information for turning on and off the primary side FET. The second control signal includes pulse information for turning on and off the active clamp FET. The processing logic also sends the same second control signal to the secondary side FET to control the secondary side FET in phase with the active clamp FET. In some cases, the pulse receiver generates the pulse signal with one or more pulses with a first pulse width in response to the signal received from the secondary side controller across the galvanic isolation barrier. The processing logic can change the first pulse width of the pulse signal to a second pulse width by generating the pulse signal with one or more additional pulses with the second pulse width. In another implementation, to send the first control signal to the primary side FET, the processing logic generates a first PWM pulse signal and applies the first PWM pulse signal to a secondary side of a first pulse transformer. Applying the first PWM pulse signal to the secondary side of the first pulse transformer causes a signal to be induced at a primary side of the first transformer to send the first PWM pulse signal to the primary side controller. A pulse receiver of the primary side controller can receive the signal at the primary side of the first pulse transformer and output a control signal to a gate of the primary side FET via a first gate driver of the primary side controller. The first control signal turns on and off the primary side FET to control a flyback transformer of the power converter. In another implementation, to send the second control signal to the active clamp FET, the processing logic generates a second PWM pulse signal and applies the second PWM pulse signal to a secondary side of a secondary pulse transformer. Applying the second PWM pulse signal to the secondary side of the second pulse transformer causes a signal to be induced at a primary side of the second transformer to send the second PWM pulse signal to the active clamp FET to drive the active clamp FET.

[0078] In another implementation, because the secondary side controller is on the secondary side, the secondary side controller can have access to secondary electrical parameters that can be calculated, including line and load information on the secondary side. For example, at low line and light load, the secondary side controller can determine that it is not beneficial to turn on (e.g., engage) the active clamp FET. This can improve efficiency by minimizing unnecessary gate switching losses. Additionally or alternatively, the secondary side controller can determine the duration of the active clamp FET based on the output power and the input voltage.

[0079] In another implementation, the processing logic of the secondary-side controller uses the same control signal to control both the active clamp FET on the primary side and the secondary-side FET on the secondary side. In this case, the active clamp FET and the secondary-side FET are phase-cut simultaneously, thereby allowing the active clamp FET to remain on for the duration that the secondary-side FET is on, and no longer. The processing logic uses a different control signal to control the primary-side FET. Since the active clamp FET does not need to remain on for the entire duration that the primary-side FET is off, there is no artificial dead-time between the active clamp FET and the primary-side FET.

[0080] Figure 9 is a flowchart of a method 1000 of controlling an active clamp FET on the primary side and a primary-side FET on the primary side with a secondary-side controller and controlling a secondary-side FET with the secondary-side controller across a galvanic isolation barrier according to another implementation. The method 1000 can be performed by processing logic that comprises hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software, firmware, or a combination thereof. In one implementation, the secondary-side controller in a secondary-controlled AC-DC flyback converter performs the method 1000. In another implementation, Figure 1 the secondary-side controller 116 of the secondary-controlled AC-DC flyback converter 100 performs the method 1000. In another implementation, Figure 2 the secondary-side controller 216 of the secondary-controlled AC-DC flyback converter 200 performs the method 1000. In another implementation, Figure 5 the secondary IC controller 516 of the secondary-controlled AC-DC flyback converter 500 performs the method 1000. In another implementation, Figure 6 the peripheral subsystem 710 of the secondary-controlled AC-DC flyback converter 700 performs the method 1000.

[0081] Referring to Figure 9The method 1000 begins with processing logic sending a first control signal to a primary side FET (block 1002) and sending a second control signal from a secondary side controller via a gate driver of the secondary side controller to control a secondary side FET (block 1004). The processing logic sends the first control signal to a primary side FET (e.g., a primary side power switch) coupled to a flyback transformer in a secondary controlled AC-DC flyback converter via a first pulse transformer coupled to the secondary side controller and the primary side controller to turn the primary side power switch on and off. The processing logic accesses secondary electrical parameters including line and load information of the secondary side (block 1006). The processing logic determines whether to engage an active clamp based on the secondary electrical parameters (block 1008). For example, at low line and light load, the processing logic can determine that it is not beneficial to switch an active clamp FET and does not engage the active clamp FET (e.g., the processing logic does not send the second control signal across a second pulse transformer to the active clamp FET). Additionally or alternatively, at high line and heavy load, the processing logic can determine that it is beneficial to turn on the active clamp FET. In this case, the processing logic then sends the same second control signal via a second pulse transformer coupled to the secondary side controller and the active clamp FET to turn the active clamp FET on and off, the active clamp FET being coupled to the flyback transformer and disposed on a primary side of the flyback transformer (block 1010).

[0082] In the description above, some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. Here, the algorithms are presented in terms of a sequence of steps that are performed by a computer, but the steps only represent a portion of the means for providing the desired technical result. The steps in the sequences are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0083] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as "receiving", "adjusting", or the like, refer to the actions and processes of a computing system, or similar electronic computing device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and memories into other data similarly represented as physical quantities within the computing system memories or registers or other such information storage, transmission or display devices.

[0084] The terms “example” or “exemplary” are used herein to indicate that they are used as examples, instances, or illustrations. Any aspect or design described herein as an “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present the concept in a specific manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X comprises A or B” is intended to mean any natural inclusive arrangement. That is, if X comprises A; X comprises B; or X comprises both A and B, then “X comprises A or B” is satisfied in any of the foregoing cases. Additionally, unless otherwise specified or clearly indicated from the context to the singular form, the articles “a” and “an” as used herein and in the appended claims should generally be construed as meaning “one or more”. Furthermore, unless otherwise stated, the use of the terms "an embodiment," "one embodiment," or "an embodiment" or "one embodiment" throughout the text is not intended to refer to the same embodiment or implementation method.

[0085] The embodiments described herein may also relate to means for performing the operations described herein. Such means may be specifically constructed for a desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk including: floppy disk, optical disk, CD-ROM, magneto-optical disk, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be considered as including a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable medium" should also be considered as including any medium capable of storing, encoding, or carrying a set of instructions that are executed by a machine and cause the machine to perform any one or more of the methods of this embodiment. The term "computer-readable storage medium" should therefore be considered as including, but not limited to, solid-state memory, optical media, magnetic media, and any medium capable of storing a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of this embodiment.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description to follow. In addition, the present embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the embodiments as described herein.

[0087] The above description sets forth numerous specific details such as examples of specific systems, components, methods and so forth, in order to provide a good understanding of several embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that the above-described embodiments are not limited to these specific details. The description is intended to be illustrative, rather than limiting. Further, numerous other embodiments will be apparent to those of ordinary skill in the art having the benefit of this description. Therefore, it is contemplated to be within the scope of the present disclosure to claim the following:

Claims

1. A secondary-side controlled alternating current to direct current (AC-DC) converter, comprising: a primary-side FET; a secondary-side FET; a transformer of the AC-DC converter, wherein the transformer is coupled to the primary-side FET and the secondary-side FET; an active clamp FET coupled to the primary-side FET, wherein the active clamp FET is disposed on a primary side of the transformer; and a secondary-side controller coupled to the transformer, wherein the secondary-side controller is configured to generate a first control signal and a second control signal, the first control signal to control the primary-side FET via a primary-side controller across a first pulse transformer coupled between the primary-side controller and the secondary-side controller, and the second control signal to control the active clamp FET across a galvanic isolation barrier provided by a second pulse transformer, wherein a gate of the active clamp FET is directly coupled to a primary winding of the second pulse transformer.

2. The AC-DC converter of claim 1, wherein, the secondary-side controller to transmit the second control signal to the active clamp FET via the second pulse transformer.

3. The AC-DC converter of claim 2, wherein, the secondary-side controller comprises: a first driver coupled to a secondary side of the first pulse transformer; a second driver coupled to a gate of the secondary-side FET; and circuitry to generate the second control signal.

4. The AC-DC converter of claim 2, wherein, the second pulse transformer is coupled to a synchronous rectifier gate driver, wherein the synchronous rectifier gate driver is to drive the active clamp FET via the second pulse transformer.

5. The AC-DC converter of claim 1, wherein, the secondary-side controller to control the secondary-side FET using a third control signal, the third control signal based on the second control signal.

6. The AC-DC converter of claim 1, wherein, the primary-side controller is coupled to the primary-side FET.

7. The AC-DC converter of claim 1, wherein, the active clamp FET is an n-type FET including a floating ground.

8. The AC-DC converter of claim 1, wherein, the active clamp FET is a p-type FET including a reference ground.

9. The AC-DC converter of claim 1, further comprising a capacitor coupled between the active clamp FET and a rectified DC line.

10. The AC-DC converter of claim 1, wherein, a source of the secondary-side FET is coupled to a GND terminal of a USB-C connector.

11. A method of controlling a FET, the method comprising: generating, by a secondary-side controller in a secondary-side controlled alternating current to direct current (AC-DC) flyback converter, a first control signal, a second control signal, and a third control signal; controlling, by the secondary-side controller, a secondary-side FET coupled to a flyback transformer using the third control signal, wherein the third control signal is based on the second control signal; controlling, by the secondary-side controller, a primary-side FET via a primary-side controller using the first control signal across a first pulse transformer coupled between the primary-side controller and the secondary-side controller; and controlling, by the secondary-side controller, the active clamp FET using the second control signal across a galvanic isolation barrier provided by a second pulse transformer, wherein a gate of the active clamp FET is directly coupled to a primary winding of the second pulse transformer. controlling, by the secondary-side controller, an active clamp FET disposed on a primary side of the flyback transformer using the second control signal, wherein the second control signal is sent across a galvanic isolation barrier provided by a second pulse transformer, wherein a gate of the active clamp FET is directly coupled to a primary winding of the second pulse transformer.

12. The method of claim 11, further comprising: determining, by the secondary-side controller, an output power on a direct current (DC) output line; in response to determining that the output power is above a threshold, activating the secondary-side FET and the active clamp FET for a first duration; and in response to determining that the output power is below the threshold, deactivating the secondary-side FET and the active clamp FET for a second duration.

13. An alternating current to direct current (AC-DC) power adapter device, comprising: a USB-C connector; a power converter coupled between an AC terminal and a DC terminal, the power converter including a transformer and a rectifier, the rectifier to convert AC power on the AC terminal to DC power on the DC terminal, and the transformer to provide galvanic isolation between the AC terminal and the DC terminal; a primary-side FET; a secondary-side FET; an active clamp FET coupled to the primary-side FET, wherein the active clamp FET is disposed on a primary side of the transformer; and a secondary-side controller coupled to the transformer, wherein the secondary-side controller is configured to generate a first control signal and a second control signal, the first control signal to control the primary-side FET via a primary-side controller across a first pulse transformer coupled between the primary-side controller and the secondary-side controller, and the second control signal to control the active clamp FET across a galvanic isolation barrier provided by a second pulse transformer, wherein a gate of the active clamp FET is directly coupled to a primary winding of the second pulse transformer.

14. The AC-DC power adapter device of claim 13, wherein, the secondary-side controller to control the secondary-side FET using a third control signal, the third control signal based on the second control signal.

15. The AC-DC power adapter device of claim 13, wherein, the secondary-side controller comprising: a first driver coupled to a secondary side of the first pulse transformer; a second driver coupled to a gate of the secondary-side FET; and circuitry to generate the second control signal.

16. The AC-DC power adapter device of claim 13, wherein, the second pulse transformer coupled to a synchronous rectifier gate driver, wherein the synchronous rectifier gate driver is to drive the active clamp FET via the second pulse transformer.

17. The AC-DC power adapter device of claim 13, wherein the primary-side controller coupled to the primary-side FET.

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