A testing method, system, device and equipment for I2C signal integrity

Abstract

The present application discloses a test method, system, device, equipment and computer-readable storage medium for I2C signal integrity. Based on a test host connected to an oscilloscope, the oscilloscope is pre-controlled to be in a trigger mode in which the trigger source is a clock signal; after determining that the I2C link to be tested of the tested mainboard transmits the I2C signal to be tested, a test waveform obtained by the oscilloscope from a clock signal test point of the I2C link to be tested and a data signal test point of the I2C link to be tested and waveform parameters of the test waveform are read; the waveform parameters are analyzed to obtain a test result of the I2C link to be tested, and a test report of the I2C waveform to be tested is generated according to the test result and the test waveform; the oscilloscope is automatically configured by running an automated test tool on the test host and the test waveform and the waveform parameters are read from the oscilloscope, thereby greatly improving the automation level of the I2C signal quality test process, reducing the work pressure of testers and improving test efficiency.

Description

Technical Field

[0001] This application relates to the technical field of server testing, and particularly to a method, system, device, equipment, and computer-readable storage medium for testing the integrity of I2C signals. Background Art

[0002] I2C (Inter-Integrated Circuit) communication is one of the most common device communication protocols. It only requires two signal lines, namely the clock signal (SCL) and the data signal (SDA), to enable operations such as temperature detection, presence detection, and parameter modification of slave devices by the master device. In addition, since each slave device has a unique device ID, a master device can control multiple slave devices, so I2C communication is widely used.

[0003] On devices with a large number of peripheral devices such as servers or memories, there are numerous I2C links, and testing the quality of I2C signals is a heavy task.

[0004] Existing methods for testing the quality of I2C signals mainly include: after a tester finds the test points of the clock signal and the data signal of the I2C link to be tested on the printed circuit board, connect the two test points to the two probes of the oscilloscope respectively; set the oscilloscope to the trigger mode with the clock signal of the I2C link to be tested as the trigger source; use the serial port tool to send read and write commands to the I2C link to be tested, and at the same time obtain the I2C waveform of the I2C link to be tested from the oscilloscope; select the waveform parameters required for analysis on the oscilloscope, read the waveform parameters of the I2C waveform of the I2C link to be tested, and save the I2C waveform; the tester sorts out the test report based on the waveform parameters and the I2C waveform, and analyzes to obtain the test result of the I2C signal quality.

[0005] It can be seen that a large amount of manual participation is required in the current process of testing the quality of I2C signals. In the context of testing numerous I2C links, not only is the testing efficiency extremely low, but it also brings heavy work to the testers. Summary of the Invention

[0006] The purpose of this application is to provide a method, system, device, equipment, and computer-readable storage medium for testing the integrity of I2C signals, which is used to reduce the manual work of testing the quality of I2C signals and improve the efficiency of testing the quality of I2C signals.

[0007] To solve the above technical problems, this application provides a method for testing the integrity of I2C signals, based on a test host, including:

[0008] Pre-control the oscilloscope connected to the test host to be in the trigger mode with the clock signal as the trigger source;

[0009] After determining that the I2C link under test on the mainboard under test transmits the I2C signal under test, read the test waveforms obtained by the oscilloscope from the clock signal test point of the I2C link under test and the data signal test point of the I2C link under test, as well as the waveform parameters of the test waveforms.

[0010] Analyze the waveform parameters to obtain the test result of the I2C link under test, and generate a test report for the I2C waveform under test based on the test result and the test waveforms.

[0011] Optionally, the test host is also connected to the master device and the slave device at both ends of the I2C link under test on the mainboard under test;

[0012] The determination that the I2C link under test on the mainboard under test transmits the I2C signal under test is specifically as follows:

[0013] After using the serial port tool to control the master device to send I2C read and write instructions to the slave device of the I2C link under test, determine that the I2C link under test transmits the I2C signal under test.

[0014] Optionally, the reading of the test waveforms obtained by the oscilloscope from the clock signal test point of the I2C link under test and the data signal test point of the I2C link under test, as well as the waveform parameters of the test waveforms, is specifically as follows:

[0015] Call the I2C test tool created based on the Laboratory Virtual Instrument Engineering Workbench to read the test waveforms and the waveform parameters from the oscilloscope.

[0016] Optionally, the reading of the test waveforms obtained by the oscilloscope from the clock signal test point of the I2C link under test and the data signal test point of the I2C link under test, as well as the waveform parameters of the test waveforms, specifically includes:

[0017] Receive the type of the target waveform parameters input;

[0018] Read the test waveforms and the target waveform parameters from the oscilloscope.

[0019] Optionally, the waveform parameters specifically include at least one of the slave device address, signal rise time, signal fall time, signal high level, signal low level, clock signal high level hold time, clock signal low level hold time, data signal setup time, and data signal hold time.

[0020] Optionally, the analysis of the waveform parameters to obtain the test result of the I2C link under test, and the generation of a test report for the I2C waveform under test based on the test result and the test waveforms, specifically includes:

[0021] Calling a preset test template, comparing each of the waveform parameters with a corresponding reference range in the preset test template, and obtaining a comparison result;

[0022] Summarizing the comparison results of the waveform parameters, and obtaining the test result according to the number of qualified items and the number of unqualified items;

[0023] The waveform parameters, the comparison results of the waveform parameters and the test results are written into the preset test template to obtain the test report.

[0024] In order to solve the above technical problems, the present application also provides an I2C signal integrity test system, including a test host and an oscilloscope connected to the test host;

[0025] Among them, the test host is used to pre-control the oscilloscope to be in a trigger mode in which the trigger source is a clock signal; after determining that the I2C link to be tested of the tested mainboard transmits the I2C signal to be tested, read the test waveform obtained by the oscilloscope from the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested and the waveform parameters of the test waveform; analyze the waveform parameters to obtain the test result of the I2C link to be tested, and generate a test report of the I2C waveform to be tested according to the test result and the test waveform.

[0026] In order to solve the above technical problems, the present application also provides an I2C signal integrity test device, based on a test host, including:

[0027] A configuration unit, used for pre-controlling an oscilloscope connected to the test host to be in a trigger mode in which the trigger source is a clock signal;

[0028] A reading unit, configured to read the test waveform obtained by the oscilloscope from the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested and the waveform parameters of the test waveform after determining that the I2C link to be tested of the tested mainboard transmits the I2C signal to be tested;

[0029] An analyzing unit is used to analyze the waveform parameters to obtain a test result of the I2C link to be tested, and generate a test report of the I2C waveform to be tested according to the test result and the test waveform.

[0030] In order to solve the above technical problems, the present application also provides an I2C signal integrity test device, including:

[0031] A memory, used to store instructions, wherein the instructions include any one of the steps of the above-mentioned I2C signal integrity testing method;

[0032] A processor is used to execute the instructions.

[0033] In order to solve the above technical problems, the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the I2C signal integrity testing method as described in any one of the above items are implemented.

[0034] The test method for I2C signal integrity provided by the present application is based on a test host connected to an oscilloscope, and includes: pre-controlling the oscilloscope to be in a trigger mode in which the trigger source is a clock signal; after determining that the I2C link to be tested of the tested mainboard transmits the I2C signal to be tested, reading the test waveform obtained by the oscilloscope from the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested and the waveform parameters of the test waveform; analyzing the waveform parameters to obtain the test result of the I2C link to be tested, and generating a test report of the I2C waveform to be tested according to the test result and the test waveform, and automatically configuring the oscilloscope by running an automated test tool on the test host and reading the test waveform and the waveform parameters from the oscilloscope, thereby greatly improving the automation level of the I2C signal quality test process, reducing the work pressure of testers, and improving test efficiency.

[0035] The present application also provides an I2C signal integrity testing system, device, equipment and computer-readable storage medium, which have the above-mentioned beneficial effects and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 A flowchart of a method for testing I2C signal integrity provided in an embodiment of the present application;

[0038] Figure 2 A standard I2C protocol timing diagram and waveform parameter schematic diagram provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of the structure of an I2C signal integrity test system provided in an embodiment of the present application;

[0040] Figure 4 A schematic diagram of the structure of an I2C signal integrity test device provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of the structure of an I2C signal integrity test device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The core of the present application is to provide a test method, system, device, equipment and computer-readable storage medium for I2C signal integrity, which are used to reduce the manual work of I2C signal quality testing and improve the efficiency of I2C signal quality testing.

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] Embodiment 1

[0045] Figure 1 A flowchart of a method for testing I2C signal integrity provided in an embodiment of the present application; Figure 2 A standard I2C protocol timing diagram and waveform parameter diagram provided in an embodiment of the present application.

[0046] like Figure 1 As shown, based on the test host, the I2C signal integrity test method provided by the embodiment of the present application includes:

[0047] S101: pre-controlling an oscilloscope connected to the test host to be in a trigger mode in which the trigger source is a clock signal.

[0048] S102: After determining that the I2C link to be tested of the tested mainboard transmits the I2C signal to be tested, reading the test waveform and waveform parameters of the test waveform obtained by the oscilloscope from the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested.

[0049] S103: Analyze the waveform parameters to obtain the test result of the I2C link to be tested, and generate a test report of the I2C waveform to be tested according to the test result and the test waveform.

[0050] In view of the problem in the prior art that when performing I2C signal quality testing, the test personnel need to configure the oscilloscope, connect the oscilloscope probe to the test point, call out the test waveform from the oscilloscope, read the waveform parameters, analyze the test results, and form a test report, the I2C signal integrity testing method provided in the embodiment of the present application develops an I2C test tool. After the test host is connected to the oscilloscope, the test host runs the I2C test tool, which can achieve one-click acquisition of the test waveform on the oscilloscope, import the template, analyze the waveform parameters and form a test report, thereby improving the automation level of the I2C signal quality test.

[0051] In a specific implementation, an I2C test tool can be developed based on the Laboratory Virtual Instrument Engineering Workbench (LabVIEW). Use a Cable cable to connect the oscilloscope and the test host. After the test host runs the I2C test tool, import the test waveform and the test report template to be analyzed with one key, write the test results and the test waveform into the test report template with one key, and automatically analyze the test data according to the design requirement values in the template.

[0052] For step S101, the test host can specifically connect to the USB3.0 interface of the oscilloscope through the USB3.0 interface, and then control the oscilloscope to be in the trigger mode, with the trigger source being the clock signal, so that the oscilloscope can capture instantaneous signals.

[0053] For step S102, connect the two probes of the oscilloscope to the test points of the clock signal and the data signal of the I2C link to be tested respectively. Use a serial port tool to control the master device of the I2C link to be tested to send read and write instructions to the slave device, which can specifically be read instructions or write instructions, so as to generate an I2C signal on the I2C link to be tested. At this time, the oscilloscope captures the test waveform of the I2C signal of the I2C link to be tested. At this time, the test host reads the test waveform and the waveform parameters of the test waveform obtained from the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested. Specifically, it can: call the I2C test tool created based on the Laboratory Virtual Instrument Engineering Workbench, and read the test waveform and the waveform parameters from the oscilloscope.

[0054] The waveform parameters involved can specifically include at least one of the following: slave device address, signal rise time, signal fall time, signal high level, signal low level, clock signal high level hold time, clock signal low level hold time, data signal setup time, and data signal hold time.

[0055] As Figure 2 shown, according to the standard I2C protocol, the communication packet format is as follows: start identifier + 8-bit slave device address + read / write flag bit (0 indicates write operation, 1 indicates read operation) + slave device acknowledgment signal (ACK) + read / write data + stop identifier. During the high level of the clock signal (SCK), the data signal (SDA) changing from high to low is the start flag bit, and conversely, during the high level of the clock signal (SCK), the data signal (SDA) changing from low to high is the stop flag bit. The I2C test tool identifies whether it is a read operation test or a write operation test by identifying the identifier bits in the communication packet. The key parameter test reference levels of the clock signal (SCK) and the data signal (SDA) are specified in the device chip manual of the slave device as VIH (0.7VCC) and VIL (0.3VCC). Design the I2C test tool to automatically identify after connecting to the oscilloscope Figure 2The VIH and VIL of the clock signal (SCK) and data signal (SDA) are obtained, and dotted lines are automatically displayed on the test waveforms of the oscilloscope. The parameters to be tested for read and write operations are sequentially obtained based on the intersections of the dotted lines and the test waveforms. The specific tests include the maximum value (VH), minimum value (VL), rise time (tR), fall time (tF), start signal setup time (Tsu; sta), start signal hold time (Thd; sta), stop signal hold time (Tsu; sto), SDA signal setup time (Tsu; dat), and SDA signal hold time (Thd; dat).

[0056] Optionally, the tester can also configure the required waveform parameters by themselves. Then, in step S102, the test waveforms and waveform parameters obtained by reading the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested from the oscilloscope specifically can include:

[0057] Receive the type of the target waveform parameters input;

[0058] Read the test waveform and target waveform parameters from the oscilloscope.

[0059] For step S103, specifically, an I2C test tool created based on the Laboratory Virtual Instrument Engineering Workbench or other template tools can analyze each waveform parameter according to a preset standard to obtain a test result and form a test report according to a preset template.

[0060] Then, in step S103, analyze the waveform parameters to obtain the test result of the I2C link to be tested, and generate a test report for the I2C waveform to be tested based on the test result and the test waveform. Specifically, it can include:

[0061] Call a preset test template, compare each waveform parameter with the corresponding reference range in the preset test template to obtain a comparison result;

[0062] Summarize the comparison results of each waveform parameter, and obtain the test result based on the number of qualified items and the number of unqualified items;

[0063] Write the waveform parameters, the comparison results of the waveform parameters, and the test process into the preset test template to obtain a test report.

[0064] In addition, a human-machine interaction interface can be developed to provide test items, configuration parameters, test procedures, etc. for viewing and selection. For example, the test host can control the display window on the human-machine interaction interface that shows the oscilloscope test waveform, and is equipped with buttons such as "Connect Oscilloscope", "Import Oscilloscope Waveform", "Generate Test Report", "Analyze Test Report", "Import Test Report Template", "Read / Write Test Selection", etc. for testers to choose. Among them, the "Connect Oscilloscope" button is used to control the connection between the I2C test tool and the oscilloscope; the "Import Oscilloscope Waveform" button is used to import the test waveform to be analyzed in the oscilloscope into the I2C test tool; the "Import Test Report Template" button is used to import the I2C test case template on the test host into the I2C test tool; the "Read / Write Test Selection" button is used to receive the tester's selection of read test or write test. The master device communicates with the slave device through the I2C protocol. This process is divided into two parts: write operation and read operation. The test point for the write operation needs to select the slave side, and the test point for the read operation needs to select the master side. Therefore, before the test, it is necessary to click the "Read / Write Selection" button according to the type of I2C signal transmitted on the I2C link to be tested to select read test or write test; the "Generate Test Report" button is used to automatically analyze and obtain waveform parameters as shown in Figure 2 after receiving the click of the tester, and save the waveform parameters and the test waveform to the corresponding positions in the test case template to generate a test report; the "Analyze Test Report" button is used to analyze the generated test report above, determine the qualified items (PASS items) and unqualified items (FAIL items) according to the spec values (reference ranges specified in the chip manual) of each test parameter in the test template, and summarize and output the test results to obtain the final test report for the tester to view.

[0065] The I2C signal integrity test method provided by the embodiment of the present application, based on a test host connected to an oscilloscope, includes: pre-controlling the oscilloscope to be in a trigger mode with the trigger source being a clock signal; when it is determined that the I2C link to be tested on the main board under test transmits the I2C signal to be tested, reading the test waveform and the waveform parameters of the test waveform obtained from the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested by the oscilloscope; analyzing the waveform parameters to obtain the test result of the I2C link to be tested, and generating a test report for the I2C waveform to be tested according to the test result and the test waveform. By running an automated test tool on the test host to automatically configure the oscilloscope and read the test waveform and waveform parameters from the oscilloscope, the automation level of the I2C signal quality test process is greatly improved, the work pressure of the testers is reduced, and the test efficiency is improved.

[0066] Embodiment 2

[0067] Based on the above embodiments, in order to further improve the automation level of I2C signal quality testing, in the I2C signal integrity testing method provided in the embodiments of the present application, the test host is connected to the master device and the slave device at both ends of the I2C link to be tested on the main board under test.

[0068] Then, in the I2C signal integrity testing method provided in the embodiments of the present application, in step S102, determining that the I2C link to be tested on the main board under test transmits the I2C signal to be tested specifically includes:

[0069] After using the serial port tool to control the master device to send I2C read and write instructions to the slave device of the I2C link to be tested, it is determined that the I2C link to be tested transmits the I2C signal to be tested.

[0070] In specific implementation, the script for controlling the master device to send I2C read and write instructions to the slave device of the I2C link to be tested is written into the I2C test tool, or a control script is developed separately. Specifically, it can be set to call the serial port tool to make the master device send I2C read and write instructions to the slave device of the I2C link to be tested after detecting the connection between the test host and the master device and the slave device at both ends of the I2C link to be tested. At the same time, it is configured to read the test waveform of the I2C link to be tested and the waveform parameters of the test waveform from the oscilloscope within a preset time after using the serial port tool to control the master device to send I2C read and write instructions to the slave device of the I2C link to be tested.

[0071] Applying the I2C signal integrity testing method provided in the embodiments of the present application, after connecting the test host to the oscilloscope and the main board under test respectively, after the tester connects the two probes of the oscilloscope to the clock signal test point and the data signal test point of the I2C link to be tested, it can automatically trigger the I2C link to be tested to transmit the I2C signal. The oscilloscope captures the I2C signal, the test host reads the test waveform and waveform parameters on the oscilloscope, automatically analyzes to obtain the test result and forms a test report, greatly reducing the working pressure of the tester for testing the I2C signal quality.

[0072] The above details each embodiment corresponding to the I2C signal integrity testing method. On this basis, the present application also discloses an I2C signal integrity testing system, device, equipment and computer-readable storage medium corresponding to the above method.

[0073] Embodiment III

[0074] Figure 3 It is a schematic structural diagram of an I2C signal integrity testing system provided in the embodiments of the present application.

[0075] As Figure 3 shown, the I2C signal integrity testing system provided in the embodiments of the present application includes a test host 301 and an oscilloscope 302 connected to the test host 301;

[0076] Among them, the test host 301 is used to pre-control the oscilloscope 302 to be in a trigger mode with the clock signal as the trigger source; when it is determined that the to-be-tested I2C link of the to-be-tested main board transmits the to-be-tested I2C signal, the test waveforms and waveform parameters obtained by the oscilloscope 302 from the clock signal test point and the data signal test point of the to-be-tested I2C link are read; the waveform parameters are analyzed to obtain the test result of the to-be-tested I2C link, and a test report of the to-be-tested I2C waveform is generated according to the test result and the test waveforms.

[0077] Since the embodiments in the system part correspond to the embodiments in the method part, for the embodiments in the system part, please refer to the description of the embodiments in the method part, which will not be elaborated here for the time being.

[0078] Embodiment 4

[0079] Figure 4 It is a schematic structural diagram of a test device for I2C signal integrity provided by an embodiment of the present application.

[0080] As Figure 4 shown, based on the test host, the test device for I2C signal integrity provided by an embodiment of the present application includes:

[0081] A configuration unit 401, configured to pre-control an oscilloscope connected to the test host to be in a trigger mode with the clock signal as the trigger source;

[0082] A reading unit 402, configured to, when it is determined that the to-be-tested I2C link of the to-be-tested main board transmits the to-be-tested I2C signal, read the test waveforms and waveform parameters obtained by the oscilloscope from the clock signal test point and the data signal test point of the to-be-tested I2C link;

[0083] An analysis unit 403, configured to analyze the waveform parameters to obtain the test result of the to-be-tested I2C link, and generate a test report of the to-be-tested I2C waveform according to the test result and the test waveforms.

[0084] Since the embodiments in the device part correspond to the embodiments in the method part, for the embodiments in the device part, please refer to the description of the embodiments in the method part, which will not be elaborated here for the time being.

[0085] Embodiment 5

[0086] Figure 5 It is a schematic structural diagram of a test device for I2C signal integrity provided by an embodiment of the present application.

[0087] As Figure 5 shown, the test device for I2C signal integrity provided by an embodiment of the present application includes:

[0088] A memory 510 for storing instructions, the instructions including the steps of the I2C signal integrity test method described in any of the above embodiments;

[0089] A processor 520 for executing the instructions.

[0090] Among them, the processor 520 may include one or more processing cores, such as a 3-core processor, an 8-core processor, etc. The processor 520 may be implemented in at least one of the following hardware forms: digital signal processing DSP (Digital Signal Processing), field programmable gate array FPGA (Field-Programmable Gate Array), and programmable logic array PLA (Programmable Logic Array). The processor 520 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the central processing unit CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 520 may be integrated with a graphics processing unit GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 520 may further include an artificial intelligence AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0091] The memory 510 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 510 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 510 is at least used to store the following computer program 511. After the computer program 511 is loaded and executed by the processor 520, it can implement the relevant steps in the I2C signal integrity test method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 510 may further include an operating system 512 and data 513, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 512 may be Windows. The data 513 may include, but is not limited to, the data involved in the above method.

[0092] In some embodiments, the I2C signal integrity test device may further include a display screen 530, a power supply 540, a communication interface 550, an input / output interface 560, a sensor 570, and a communication bus 580.

[0093] Those skilled in the art can understand that Figure 5 the structure shown in Figure 5 does not constitute a limitation on the test device for I2C signal integrity, and may include more or fewer components than those shown in the figure.

[0094] The test device for I2C signal integrity provided by the embodiments of the present application includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the above-mentioned I2C signal integrity test method, and the effect is the same.

[0095] Embodiment Six

[0096] It should be noted that the system, device, and equipment embodiments described above are only illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other can be through some interfaces, and the indirect couplings or communication connections of devices or modules can be in electrical, mechanical, or other forms. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they can be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0097] In addition, in each embodiment of the present application, the functional modules can be integrated in a processing module, or each module can exist physically alone, or two or more modules can be integrated in one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0098] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application.

[0099] Therefore, the embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the I2C signal integrity test method.

[0100] The computer-readable storage medium may include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0101] The computer program included in the computer-readable storage medium provided in this embodiment can, when executed by a processor, implement the steps of the I2C signal integrity test method described above, and the effect is the same.

[0102] The above has introduced in detail a method, system, device, equipment, and computer-readable storage medium for testing I2C signal integrity provided by this application. Each embodiment in the specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the system, device, equipment, and computer-readable storage medium disclosed in the embodiments, since they correspond to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0103] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article, or device including the said element.

Claims

1. A test method for I2C signal integrity, characterized in that, A test host connected to the master device and the slave device at both ends of the I2C link to be tested on the main board to be tested, including: Pre - control the oscilloscope connected to the test host to be in a trigger mode with the trigger source being the clock signal; After using the serial port tool to control the master device to send I2C read - write instructions to the slave device, read the test waveforms and the waveform parameters obtained from the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested by the oscilloscope, including: calling the I2C test tool created based on the Laboratory Virtual Instrument Engineering Workbench, reading the test waveforms from the oscilloscope, identifying the identification bits in the communication packets between the master device and the slave device to determine whether it is a read - operation test or a write - operation test, selecting the host side for the read - operation test and the slave side for the write - operation test; determining the test reference level of the I2C link to be tested from the device chip manual and displaying the corresponding dotted line on the test waveforms of the oscilloscope, and successively reading the parameters to be tested for the read operation and the write operation according to the intersection points of the dotted line and the test waveforms to obtain the waveform parameters; Analyze the waveform parameters to obtain the test results of the I2C link to be tested, and generate a test report for the I2C waveform to be tested based on the test results and the test waveforms, including: calling a preset test template, comparing each of the waveform parameters with the corresponding reference range in the preset test template to obtain a comparison result; summarizing the comparison results of each of the waveform parameters, and obtaining the test results according to the number of qualified items and the number of unqualified items; writing the waveform parameters, the comparison results of the waveform parameters, and the test results into the preset test template to obtain the test report; the preset test template is the I2C test case template on the test host.

2. The test method according to claim 1, characterized in that, The reading of the test waveforms and the waveform parameters obtained from the clock signal test point of the I2C link to be tested and the data signal test point of the I2C link to be tested by the oscilloscope specifically includes: Receiving the type of the target waveform parameters input; Reading the test waveforms and the target waveform parameters from the oscilloscope.

3. The testing method according to claim 1, characterized in that The waveform parameters specifically include at least one of the slave device address, signal rise time, signal fall time, signal high level, signal low level, clock signal high - level hold time, clock signal low - level hold time, data signal setup time, and data signal hold time.

4. A test system for I2C signal integrity, characterized in that, It includes a test host connected to the master device and the slave device at both ends of the I2C link to be tested on the main board to be tested and an oscilloscope connected to the test host; Among them, the test host is used to pre-control the oscilloscope to be in a trigger mode with a clock signal as the trigger source; after using a serial port tool to control the master device to send I2C read and write instructions to the slave device, call the I2C test tool created based on the laboratory virtual instrument engineering platform, read the test waveform from the oscilloscope, identify the identification bits in the communication packet between the master device and the slave device to determine whether it is a read operation test or a write operation test, the read operation test corresponds to selecting the host side, and the write operation test corresponds to selecting the slave side; determine the test reference level of the to-be-tested I2C link from the device device chip manual and display the corresponding dotted line on the test waveform of the oscilloscope, and sequentially read the parameters to be tested for the read operation and the write operation according to the intersection points of the dotted line and the test waveform to obtain waveform parameters; call a preset test template, compare each of the waveform parameters with the corresponding reference range in the preset test template to obtain a comparison result; summarize the comparison results of each of the waveform parameters, and obtain the test result according to the number of qualified items and the number of unqualified items; write the waveform parameters, the comparison results of the waveform parameters, and the test process into the preset test template to obtain the test report; the preset test template is the I2C test case template on the test host.

5. A test device for I2C signal integrity, characterized in that Based on a test host connected to the master device and the slave device at both ends of the to-be-tested I2C link on the to-be-tested main board, it includes: A configuration unit, used to pre-control the oscilloscope connected to the test host to be in a trigger mode with a clock signal as the trigger source; A reading unit, used to control the master device to send I2C read and write instructions to the slave device using a serial port tool, then call the I2C test tool created based on the laboratory virtual instrument engineering platform, read the test waveform from the oscilloscope, identify the identification bits in the communication packet between the master device and the slave device to determine whether it is a read operation test or a write operation test, the read operation test corresponds to selecting the host side, and the write operation test corresponds to selecting the slave side; determine the test reference level of the to-be-tested I2C link from the device device chip manual and display the corresponding dotted line on the test waveform of the oscilloscope, and sequentially read the parameters to be tested for the read operation and the write operation according to the intersection points of the dotted line and the test waveform to obtain waveform parameters; An analysis unit, used to call a preset test template, compare each of the waveform parameters with the corresponding reference range in the preset test template to obtain a comparison result; summarize the comparison results of each of the waveform parameters, and obtain the test result according to the number of qualified items and the number of unqualified items; write the waveform parameters, the comparison results of the waveform parameters, and the test process into the preset test template to obtain the test report; the preset test template is the I2C test case template on the test host.

6. A test device for I2C signal integrity, characterized in that, It includes: A memory, used to store instructions, and the instructions include the steps of the I2C signal integrity test method according to any one of claims 1 to 3; A processor, used to execute the instructions.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the I2C signal integrity test method according to any one of claims 1 to 3.

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