Matrix conversion circuit, method, integrated circuit chip, computing device and board

Abstract

The present disclosure relates to a matrix conversion circuit, method, integrated circuit chip, computing device and board, wherein the computing device may be included in a combined processing device, and the combined processing device may also include a universal interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operation specified by the user. The combined processing device may also include a storage device, which is respectively connected to the computing device and other processing devices and is used to store data of the computing device and other processing devices. The scheme of the present disclosure can be widely used in various matrix conversions.

Description

Technical Field

[0001] The present disclosure generally relates to the field of matrix switching. More specifically, the present disclosure relates to matrix switching circuits, methods, integrated circuit chips, computing devices and boards. Background Art

[0002] It is known that matrix conversion operations include transposition, rotation and mirroring, etc. Currently, dedicated matrix operation custom circuits are generally used to implement these conversion operations. However, these matrix operation custom circuits are complex in design, have fixed interfaces and functions, and can only process matrices of fixed sizes. Moreover, one type of matrix operation circuit can only process matrix conversions of the corresponding type, and cannot perform multiple matrix conversions according to actual needs. Therefore, how to obtain a matrix conversion circuit that can perform different conversion operations on matrices of various sizes has become a problem that needs to be solved in the prior art. Summary of the invention

[0003] In order to at least partially solve the technical problems mentioned in the background technology, the solution of the present disclosure provides a matrix conversion circuit and method thereof, an integrated circuit chip including the matrix conversion circuit, a computing device and a board.

[0004] In one aspect, the present disclosure provides a matrix conversion circuit, comprising: a storage array determination circuit, which is used to determine the size of a cache storage array according to matrix size information of a matrix to be converted; and a conversion processing circuit, which is used to store and read the matrix to be converted in the cache storage array according to an access method corresponding to a matrix conversion mode, so as to convert the matrix to be converted.

[0005] In another aspect, the present disclosure provides a matrix conversion method, the method comprising: determining the size of a cache storage array according to matrix size information of a matrix to be converted; storing and reading the matrix to be converted in the cache storage array according to an access method corresponding to a matrix conversion mode, so as to convert the matrix to be converted.

[0006] In another aspect, the present disclosure provides an integrated circuit chip, comprising the matrix conversion circuit. In one or more embodiments, the matrix conversion circuit of the present disclosure can constitute an independent integrated circuit chip or be arranged on an integrated circuit chip or a computing device to implement various conversion operations on matrices of different sizes.

[0007] In yet another aspect, the present disclosure provides a board comprising the computing device as described above.

[0008] By using the matrix conversion circuit, the corresponding conversion method, the integrated circuit chip, the computing device and the board of the present disclosure, various conversion operations can be performed on matrices of different sizes, without providing multiple dedicated custom circuits for different matrix sizes and different matrix conversion operations. Therefore, the matrix conversion circuit of the present disclosure is flexible and can be widely used in various conversion operations of matrices of different sizes. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0010] Figure 1 is a schematic block diagram showing a matrix conversion circuit according to an embodiment of the present disclosure;

[0011] Figure 2 is a schematic block diagram showing a matrix conversion circuit according to another embodiment of the present disclosure;

[0012] Figure 3 is a schematic block diagram showing a matrix conversion circuit according to yet another embodiment of the present disclosure;

[0013] Figure 4 is a flow chart showing a matrix conversion method according to one embodiment of the present disclosure;

[0014] Figure 5 is a flow chart showing a matrix conversion method according to another embodiment of the present disclosure;

[0015] Figure 6 is a flow chart showing a matrix conversion method according to yet another embodiment of the present disclosure;

[0016] Figure 7 is a structural diagram showing a combined processing device according to an embodiment of the present disclosure; and

[0017] Figure 8 It is a schematic diagram showing the structure of a board according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0019] The technical solution disclosed in the present invention provides a matrix conversion circuit, method, integrated circuit chip, computing device and board as a whole. Different from the matrix conversion circuit of the prior art, the present invention provides a matrix conversion circuit capable of performing different conversion operations on matrices of various sizes, thereby overcoming the defects that the existing matrix conversion circuit needs to be specially customized and can only process one type of conversion of a fixed-size matrix. In particular, the present invention can perform different matrix conversion operations according to different matrix conversion modes, such as matrix transposition, rotation, mirroring, etc. Therefore, the matrix conversion circuit disclosed in the present invention has high flexibility.

[0020] Figure 1 1 is a schematic block diagram showing a matrix conversion circuit 100 according to an embodiment of the present disclosure. Figure 1 As shown in , the matrix conversion circuit 100 includes a storage array determination circuit 101 and a conversion processing circuit 102. The storage array determination circuit 101 is used to determine the size of the cache storage array according to the matrix size information of the matrix to be converted. The conversion processing circuit 102 is used to store and read the matrix to be converted in the cache storage array according to the access mode corresponding to the matrix conversion mode, so as to convert the matrix to be converted.

[0021] According to this embodiment, when a conversion operation such as transposition, rotation or mirroring is required for a matrix, the storage array determination circuit 101 in the matrix conversion circuit 100 sets a cache storage array matching the size of the matrix to be converted according to the size information of the matrix to be converted, for use in the matrix conversion. The conversion mode indicates the conversion (transposition, rotation or mirroring) required for the matrix, and the access mode of the matrix corresponding to the conversion mode in the cache storage array is preset. The conversion processing circuit 102 calls the preset access mode according to the matrix conversion mode, and stores and reads the matrix to be converted in the cache storage array according to the preset access mode, so that the matrix read out is the matrix converted according to the matrix conversion mode.

[0022] Further, the storage array determination circuit 101 is used to determine the size of the cache storage array according to the number of rows X, the number of columns Y and the storage space K occupied by the basic elements of the matrix to be converted, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, and the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y.

[0023] Specifically, according to the number of rows X, the number of columns Y and the storage space K occupied by the basic elements of the matrix to be converted, the storage array determination circuit 101 sets a cache storage array that matches the size of the matrix to be converted, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, and the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y. The above setting of the size of the cache storage array is to meet the requirement that the matrix to be converted can be stored in the cache storage array according to the preset access mode. For example, when X is not equal to Y, in the transposition mode, the number of rows and the number of columns are interchanged, and the number of rows and the number of columns of the cache storage array formed by the above setting can support such changes in the number of rows and the number of columns during the matrix conversion process. Of course, when X is equal to Y, the number of rows of the cache storage array is greater than or equal to any one of X and Y and the number of columns of the cache storage array is greater than or equal to any one of X and Y to achieve the above operation.

[0024] Examples of matrix conversion in five conversion modes are described in detail below. In each matrix conversion mode, the matrix to be converted is converted by storing and reading in the cache storage array according to a corresponding preset access method.

[0025] According to the first example, when the matrix conversion mode is the matrix transposition mode, the conversion processing circuit 102 is used to store each row of the matrix to be converted in the corresponding row in the cache storage array according to the intra-row order to form an intermediate matrix, and read each column of the intermediate matrix in the cache storage array in the order from the first column to the last column of the intermediate matrix and according to the intra-column order, and output them as the first row to the last row of the matrix in sequence to form the transposed matrix of the matrix to be converted.

[0026] In this example, for example, the matrix to be converted is an X*Y matrix, and X may be equal to Y or not equal to Y. The conversion processing circuit 102 stores the first row of the X*Y matrix in the order from the first basic element to the Yth basic element in the first row of the cache storage array, and performs such a cyclic operation in the order from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the first basic element to the Yth basic element in the Xth row of the cache storage array, to form an X*Y intermediate matrix, which can be understood as the matrix to be converted being copied to the cache storage array. Then, the conversion processing circuit 102 reads the first basic element of the 1st row to the Xth row of the X*Y intermediate matrix in sequence, and splices the X basic elements read out in this sequence into one row as the first row of the transposed matrix, and repeats the operation in this way from the 1st basic element to the Yth basic element until the Yth basic element of the 1st row to the Xth row of the X*Y intermediate matrix is ​​read out in sequence, and splices the X basic elements read out in this sequence into one row as the Yth row of the transposed matrix, thereby forming a transposed matrix.

[0027] According to the second example, when the matrix conversion mode is a matrix rotation of 270°, the conversion processing circuit 102 is used to store each row of the matrix to be converted in the corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and in the cache storage array, each column of the intermediate matrix is ​​read in order from the first column to the last column of the intermediate matrix and in order within the column, and is output as the first row to the last row of the matrix in sequence to form a matrix of the matrix to be converted rotated 270°.

[0028] In this example, for example, the matrix to be converted is an X*Y matrix, and X may be equal to Y or not equal to Y. The conversion processing circuit 102 stores the first row of the X*Y matrix in the order from the Yth basic element to the first basic element in the first row of the cache storage array, and performs such a cyclic operation in the order from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the Yth basic element to the first basic element in the Xth row of the cache storage array, to form an X*Y intermediate matrix, which can be understood as being formed by mirroring each row of the matrix to be converted in a row. Then, the conversion processing circuit 102 reads the first basic element of the 1st row to the Xth row of the X*Y intermediate matrix in sequence, and splices the X basic elements read out in this sequence into one row as the first row of the rotated matrix, and repeats the operation in this way from the 1st basic element to the Yth basic element until the Yth basic element of the 1st row to the Xth row of the X*Y intermediate matrix is ​​read out in sequence, and splices the X basic elements read out in this sequence into one row as the Yth row of the rotated matrix, thereby forming a matrix rotated by 270°.

[0029] According to the third example, when the matrix conversion mode is a matrix rotation of 90°, the conversion processing circuit 102 is used to store each row of the matrix to be converted in the corresponding row in the cache storage array according to the order within the row to form an intermediate matrix, and in the cache storage array, each column of the intermediate matrix is ​​read in order from the first column to the last column of the intermediate matrix and in reverse order within the column, and is output as the first row to the last row of the matrix in sequence to form a matrix of the matrix to be converted rotated 90°.

[0030] In this example, for example, the matrix to be converted is an X*Y matrix, and X may be equal to Y or not equal to Y. The conversion processing circuit 102 stores the first row of the X*Y matrix in the order from the first basic element to the Yth basic element in the first row of the cache storage array, and performs such a cyclic operation in the order from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the first basic element to the Yth basic element in the Xth row of the cache storage array, to form an X*Y intermediate matrix, which can be understood as the matrix to be converted being copied to the cache storage array. Then the conversion processing circuit 102 reads out the first row of the X*Y intermediate matrix in the order from the Yth basic element to the first basic element as the first row of the rotated matrix, and repeats the operation in this way from the first row to the Xth row of the X*Y intermediate matrix until the Xth row of the X*Y intermediate matrix is ​​read out in the order from the Yth basic element to the first basic element as the Xth row of the rotated matrix, thereby forming a matrix rotated 90°.

[0031] According to the fourth example, when the matrix conversion mode is a matrix rotation of 180°, the conversion processing circuit 102 is used to store each row of the matrix to be converted in the corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and read each row of the intermediate matrix in the cache storage array in order from the last row to the first row of the intermediate matrix and in order within the row, and output them as the first row to the last row of the matrix in sequence to form a matrix of the matrix to be converted rotated 180°.

[0032] In this example, for example, the matrix to be converted is an X*Y matrix, and X may be equal to Y or not equal to Y. The conversion processing circuit 102 stores the first row of the X*Y matrix in the order from the Yth basic element to the first basic element in the first row of the cache storage array, and performs such a cyclic operation in the order from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the Yth basic element to the first basic element in the Xth row of the cache storage array, to form an X*Y intermediate matrix, which can be understood as being formed by mirroring each row of the matrix to be converted in a row. Then the conversion processing circuit 102 reads the Xth row of the X*Y intermediate matrix in the order from the 1st basic element to the Yth basic element as the first row of the rotated matrix, and repeats the operation in this way from the Xth row to the 1st row of the intermediate matrix until the first row of the X*Y intermediate matrix is ​​read in the order from the 1st basic element to the Yth basic element as the Xth row of the rotated matrix, thereby forming a matrix rotated 180°.

[0033] According to the fifth example, when the matrix conversion mode is set to the mirror mode, the conversion processing circuit 102 is used to store each row of the matrix to be converted in the corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and read each row of the intermediate matrix in the cache storage array in the order from the last row to the first row of the intermediate matrix and in reverse order within the row, and output them as the first row to the last row of the matrix in sequence to form a mirror matrix of the matrix to be converted.

[0034] In this example, for example, the matrix to be converted is an X*Y matrix, and X may be equal to Y or not equal to Y. The conversion processing circuit 102 stores the first row of the X*Y matrix in the order from the Yth basic element to the first basic element in the first row of the cache storage array, and performs such a cyclic operation in the order from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the Yth basic element to the first basic element in the Xth row of the cache storage array, to form an X*Y intermediate matrix, which can be understood as being formed by mirroring each row of the matrix to be converted in a row. Then the conversion processing circuit 102 reads the Xth row of the X*Y intermediate matrix in the order from the Yth basic element to the 1st basic element as the 1st row of the mirrored matrix, and repeats the operation in this way from the Xth row to the 1st row of the intermediate matrix until the 1st row of the X*Y intermediate matrix is ​​read in the order from the Yth basic element to the 1st basic element as the Xth row of the mirrored matrix, thereby forming a mirrored matrix.

[0035] According to the above five examples, after the matrix to be converted is stored in the cache storage array in a preset manner, an intermediate matrix is ​​formed, and then a read operation is performed on the intermediate matrix. It should be understood that when the space occupied by the cache storage array is larger than the matrix to be converted (intermediate matrix), the operation on the intermediate matrix can also be regarded as an operation on the valid basic elements in the cache storage array.

[0036] It should be noted that the above description of five examples of matrix conversion modes implemented by the matrix conversion circuit 100 is only for illustrative and non-restrictive purposes. The matrix conversion circuit of the present disclosure can also implement other matrix conversions according to a preset access method, and the above-mentioned preset access method can also be other access methods that can implement corresponding conversions.

[0037] Reference Figure 2 , Figure 2 is a schematic block diagram showing a matrix conversion circuit 200 according to another embodiment of the present disclosure. Figure 2 The matrix conversion circuit 200 shown in FIG. Figure 1 The only difference between the matrix conversion circuit 100 shown in FIG. 2 is that the matrix conversion circuit 200 further includes a first acquisition circuit 201, and the first acquisition circuit 201 is used to acquire matrix size information of the matrix to be converted.

[0038] In this embodiment, the first acquisition circuit 201 is used to acquire the size information of the matrix to be converted, such as the number of rows X, the number of columns Y, and the storage space occupied by the basic elements K. The size information may be manually input into the first acquisition circuit, or may be transmitted to the first acquisition circuit by other circuits or components, or may be acquired by the first acquisition circuit in any other manner.

[0039] Reference Figure 3 , Figure 3 is a schematic block diagram showing a matrix conversion circuit 300 according to yet another embodiment of the present disclosure. Figure 3 The matrix conversion circuit 300 shown in FIG. Figure 1 The only difference between the matrix conversion circuit 100 shown in FIG. 3 is that the matrix conversion circuit 300 further includes a second acquisition circuit 301, and the second acquisition circuit 301 is used to acquire the matrix conversion mode.

[0040] In this embodiment, the second acquisition circuit 301 is used to acquire the matrix conversion mode of the matrix to be converted, such as transposition, rotation and mirroring, etc. The matrix conversion mode can be manually input into the second acquisition circuit, or can be transmitted to the second acquisition circuit by other circuits or components, or can be acquired by the second acquisition circuit in any other way.

[0041] In addition, the above Figure 2 and Figure 3 The first acquisition circuit 201 and the second acquisition circuit 301 can be used in combination, that is, the matrix conversion circuit can include the first acquisition circuit 201 and the second acquisition circuit 301 at the same time. In this case, the working mode of the first acquisition circuit 201 and the second acquisition circuit 301 is the same as above.

[0042] The present disclosure also provides a matrix conversion method. Figure 4 , which is a flow chart showing a matrix conversion method according to an embodiment of the present disclosure. Figure 4 As shown in FIG. 1 , it can be understood that the matrix conversion circuit used in the matrix conversion method here is the same as the one previously described in conjunction with Figure 1-Figure 3 The matrix conversion circuit is described in detail, so the previous description about the matrix conversion circuit and its internal composition, function and operation is also applicable to the description here.

[0043] like Figure 4 As shown in , the matrix conversion method of the present disclosure includes the following steps S101-S102.

[0044] In step S101, the size of the cache storage array is determined according to the matrix size information of the matrix to be converted;

[0045] In step S102, the matrix to be converted is stored in and read from the cache storage array according to an access method corresponding to the matrix conversion mode, so as to convert the matrix to be converted.

[0046] According to an embodiment of the present disclosure, determining the size of the cache storage array according to the matrix size information of the matrix to be converted includes:

[0047] The size of the cache storage array is determined according to the number of rows X, the number of columns Y and the storage space K occupied by the basic elements of the matrix to be converted, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, and the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y.

[0048] Examples of matrix conversion methods in five conversion modes will be described below.

[0049] When the matrix conversion mode is a matrix transposition mode, the method includes: storing each row of the matrix to be converted in a corresponding row in the cache storage array according to the intra-row order to form an intermediate matrix, and reading each column of the intermediate matrix in the cache storage array in the order from the first column to the last column of the intermediate matrix and according to the intra-column order, and outputting them in sequence as the first row to the last row of the matrix, so as to form a transposed matrix of the matrix to be converted.

[0050] When the matrix conversion mode is a matrix rotation of 270°, the method includes: storing each row of the matrix to be converted in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and reading each column of the intermediate matrix in the cache storage array in order from the first column to the last column of the intermediate matrix and in order within the column, and outputting them in sequence as the first row to the last row of the matrix, so as to form a matrix of the matrix to be converted rotated 270°.

[0051] When the matrix conversion mode is a matrix rotation of 90°, the method includes: storing each row of the matrix to be converted in a corresponding row in the cache storage array according to the order within the row to form an intermediate matrix, and reading each column of the intermediate matrix in the cache storage array in order from the first column to the last column of the intermediate matrix and in reverse order within the column, and outputting them as the first row to the last row of the matrix in sequence, so as to form a matrix of the matrix to be converted rotated 90°.

[0052] When the matrix conversion mode is a matrix rotation of 180°, the method includes: storing each row of the matrix to be converted in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and reading each row of the intermediate matrix in the cache storage array in order from the last row to the first row of the intermediate matrix and in order within the row, and outputting them as the first row to the last row of the matrix in sequence, so as to form a matrix of the matrix to be converted rotated 180°.

[0053] When the matrix conversion mode is a mirror mode, the method includes: storing each row of the matrix to be converted in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and reading each row of the intermediate matrix in the cache storage array in an order from the last row to the first row of the intermediate matrix and in reverse order within the row, and outputting them in sequence as the first row to the last row of the matrix, so as to form a mirror matrix of the matrix to be converted.

[0054] Reference Figure 5 , Figure 5 FIG. 4 is a flow chart showing a matrix conversion method according to another embodiment of the present disclosure. Figure 5 As shown, the method further includes the following step S201 before the step S101.

[0055] In step S201, the matrix size information of the matrix to be converted is obtained.

[0056] Reference Figure 6 , Figure 6 FIG. 4 is a flow chart showing a matrix conversion method according to another embodiment of the present disclosure. Figure 6 As shown, the method further includes the following step S301 before the step S101.

[0057] In step S301, a matrix conversion mode is obtained.

[0058] In this embodiment, step S301 is before step S101 , but step S301 may also be after step S101 and before step S102 .

[0059] In addition, the above Figure 5 and Figure 6 The two steps S201 and S301 in the method can be used in combination, that is, the matrix conversion method can include the two steps S201 and S301 at the same time.

[0060] In the above embodiments of the present disclosure, the description of each embodiment has its own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] Figure 7 is a structural diagram showing a combined processing device 700 according to an embodiment of the present disclosure. Figure 7 As shown in FIG. 7 , the combined processing device 700 includes a computing processing device 702, an interface device 704, other processing devices 706, and a storage device 708. According to different application scenarios, the computing processing device may include one or more computing devices 710, which may be configured to execute the Figure 1-6 The operation described.

[0062] In different embodiments, the computing and processing device of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing and processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, with respect to the computing and processing device of the present disclosure, it may be regarded as having a single-core structure or a homogeneous multi-core structure.

[0063] In an exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through an interface device to jointly complete the operation specified by the user. Depending on the implementation, other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, etc. These processors may include, but are not limited to, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0064] In one or more embodiments, the other processing device can serve as an interface between the computing processing device of the present disclosure and external data and control, and perform basic control including but not limited to data transfer, starting and / or stopping the computing device, etc. In other embodiments, the other processing device can also cooperate with the computing processing device to jointly complete the computing task.

[0065] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it into a storage device (or memory) on the computing and processing device chip. Further, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them into a control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0066] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0067] In some embodiments, the present disclosure further discloses a chip (eg Figure 8 In one implementation, the chip is a system on chip (SoC) and integrates one or more Figure 7 The chip can be connected to an external interface device (such as Figure 8 The external interface device 806 shown in the figure is connected to other related components. The related components may be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as a video codec) and / or interface modules (such as a DRAM interface) may be integrated on the chip. In some embodiments, the present disclosure further discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure further discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 8 The board is described in detail.

[0068] Figure 8 FIG. 8 is a schematic diagram showing the structure of a board 800 according to an embodiment of the present disclosure. Figure 8 As shown in , the board includes a storage device 804 for storing data, which includes one or more storage units 810. The storage device can be connected and data can be transmitted with the control device 808 and the chip 802 described above by means of, for example, a bus. Further, the board also includes an external interface device 806, which is configured for data relay or switching between the chip (or the chip in the chip packaging structure) and an external device 812 (such as a server or computer, etc.). For example, the data to be processed can be transmitted to the chip by the external device through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0069] In one or more embodiments, the control device in the disclosed board may be configured to regulate the state of the chip. To this end, in an application scenario, the control device may include a microcontroller unit (MCU) for regulating the working state of the chip.

[0070] According to the above combination Figure 7 and Figure 8 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0071] According to different application scenarios, the electronic equipment or device disclosed in the present invention may include a server, a cloud server, a server cluster, a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, an Internet of Things terminal, a mobile terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a visual terminal, an automatic driving terminal, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric light, a gas stove, and a range hood; the medical device includes a nuclear magnetic resonance instrument, a B-ultrasound instrument, and / or an electrocardiograph. The electronic equipment or device disclosed in the present invention can also be applied to the Internet, the Internet of Things, a data center, energy, transportation, public administration, manufacturing, education, power grid, telecommunications, finance, retail, construction sites, medical treatment and other fields. Further, the electronic equipment or device disclosed in the present invention can also be used in the cloud, edge end, terminal and other application scenarios related to artificial intelligence, big data and / or cloud computing. In one or more embodiments, electronic devices or devices with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or devices with low power consumption can be applied to terminal devices and / or edge devices (such as smart phones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0072] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teaching of the present disclosure, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present disclosure may be regarded as optional embodiments, i.e., the actions or modules involved therein may not necessarily be necessary for the implementation of one or some of the schemes of the present disclosure. In addition, depending on the different schemes, the present disclosure also has different focuses on the description of some embodiments. In view of this, those skilled in the art will appreciate that the parts that are not described in detail in a certain embodiment of the present disclosure may also refer to the relevant descriptions of other embodiments.

[0073] In terms of specific implementation, based on the disclosure and teachings of the present disclosure, those skilled in the art can understand that several embodiments disclosed in the present disclosure can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article divides them on the basis of considering logical functions, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. In terms of the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0074] In the present disclosure, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located at the same location or distributed to multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

[0075] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0076] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPU, GPU, FPGA, DSP and ASIC, etc. Further, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), which can be, for example, a variable resistive memory (Resistive Random Access Memory, RRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), an enhanced dynamic random access memory (Enhanced Dynamic Random Access Memory, EDRAM), a high bandwidth memory (High Bandwidth Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

[0077] Although multiple embodiments of the present disclosure have been shown and described herein, it is apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the ideas and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

[0078] The foregoing content can be better understood in accordance with the following terms:

[0079] Item A1, a matrix conversion circuit comprising:

[0080] A storage array determination circuit, which is used to determine the size of the cache storage array according to the matrix size information of the matrix to be converted; and

[0081] The conversion processing circuit is used for storing and reading the matrix to be converted in the cache storage array according to an access method corresponding to the matrix conversion mode, so as to convert the matrix to be converted.

[0082] Item A2, according to the matrix conversion circuit described in Item A1, the matrix conversion circuit also includes a first acquisition circuit, which is used to obtain matrix size information of the matrix to be converted.

[0083] Item A3, a matrix conversion circuit according to Item A1 or Item A2, wherein the storage array determination circuit is used to determine the size of the cache storage array based on the number of rows X, the number of columns Y and the storage space K occupied by the basic elements of the matrix to be converted, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, and the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y.

[0084] Item A4, a matrix conversion circuit according to any one of items A1-A3, wherein the matrix conversion circuit further includes a second acquisition circuit for acquiring the matrix conversion mode.

[0085] Item A5, a matrix conversion circuit according to any one of items A1-A4, wherein when the matrix conversion mode is a matrix transposition mode, the conversion processing circuit is used to store each row of the matrix to be converted in a corresponding row in the cache storage array in order within the row to form an intermediate matrix, and in the cache storage array, each column of the intermediate matrix is ​​read in order from the first column to the last column of the intermediate matrix and in order within the column and output in sequence as the first row to the last row of the matrix to form a transposed matrix of the matrix to be converted.

[0086] Item A6, a matrix conversion circuit according to any one of items A1-A5, wherein when the matrix conversion mode is a matrix rotation of 270°, the conversion processing circuit is used to store each row of the matrix to be converted in the corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and in the cache storage array, each column of the intermediate matrix is ​​read in order from the first column to the last column of the intermediate matrix and in order within the column, and output as the first row to the last row of the matrix in sequence to form a matrix of the matrix to be converted rotated 270°.

[0087] Item A7, a matrix conversion circuit according to any one of items A1-A6, wherein when the matrix conversion mode is a matrix rotation of 90°, the conversion processing circuit is used to store each row of the matrix to be converted in the corresponding row in the cache storage array in order within the row to form an intermediate matrix, and in the cache storage array, each column of the intermediate matrix is ​​read in order from the first column to the last column of the intermediate matrix and in reverse order within the column and output as the first row to the last row of the matrix in sequence to form a matrix of the matrix to be converted rotated 90°.

[0088] Item A8, a matrix conversion circuit according to any one of items A1-A7, wherein when the matrix conversion mode is a matrix rotation of 180°, the conversion processing circuit is used to store each row of the matrix to be converted in the corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and in the cache storage array, each row of the intermediate matrix is ​​read in order from the last row to the first row of the intermediate matrix and in order within the row, and is output as the first row to the last row of the matrix in sequence to form a matrix of the matrix to be converted rotated 180°.

[0089] Item A9, a matrix conversion circuit according to any one of items A1-A8, wherein when the matrix conversion mode is set to a mirror mode, the conversion processing circuit is used to store each row of the matrix to be converted in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and in the cache storage array, each row of the intermediate matrix is ​​read in order from the last row to the first row of the intermediate matrix and in reverse order within the row and output in sequence as the first row to the last row of the matrix to form a mirror matrix of the matrix to be converted.

[0090] Item A10, a matrix conversion method, comprising:

[0091] Determine the size of the cache storage array according to the matrix size information of the matrix to be converted;

[0092] According to the access method corresponding to the matrix conversion mode, the matrix to be converted is stored in and read from the cache storage array to convert the matrix to be converted.

[0093] Clause A11, according to the matrix conversion method of clause A10, before determining the size of the cache storage array according to the matrix size information of the matrix to be converted, the matrix conversion method further includes:

[0094] Obtain the matrix size information of the matrix to be converted.

[0095] Clause A12, according to the matrix conversion method of clause A10 or clause A11, wherein determining the size of the cache storage array according to the matrix size information of the matrix to be converted comprises:

[0096] The size of the cache storage array is determined according to the number of rows X, the number of columns Y and the storage space K occupied by the basic elements of the matrix to be converted, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, and the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y.

[0097] Item A13, a matrix conversion method according to any one of Items A10-A12, wherein before storing and reading the matrix to be converted in the cache storage array, the matrix conversion method also includes obtaining a matrix conversion mode.

[0098] Clause A14, a matrix conversion method according to any one of clauses A10-A13, wherein when the matrix conversion mode is a matrix transposition mode, the method comprises:

[0099] Each row of the matrix to be converted is stored in a corresponding row in the cache storage array according to an intra-row order to form an intermediate matrix, and each column of the intermediate matrix is ​​read in the cache storage array in an order from the first column to the last column of the intermediate matrix and in an intra-column order, and is sequentially output as the first row to the last row of the matrix to form a transposed matrix of the matrix to be converted.

[0100] Clause A15, a matrix conversion method according to any one of clauses A10-A14, wherein when the matrix conversion mode is a matrix rotation of 270°, the method comprises:

[0101] Each row of the matrix to be converted is stored in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and each column of the intermediate matrix is ​​read in the cache storage array in an order from the first column to the last column of the intermediate matrix and in an order within the column, and is output in sequence as the first row to the last row of the matrix to form a matrix rotated 270° of the matrix to be converted.

[0102] Clause A16, a matrix conversion method according to any one of clauses A10-A15, wherein when the matrix conversion mode is a matrix rotation of 90°, the method comprises:

[0103] Each row of the matrix to be converted is stored in a corresponding row in the cache storage array according to the order within the row to form an intermediate matrix, and each column of the intermediate matrix is ​​read in the cache storage array in the order from the first column to the last column of the intermediate matrix and in reverse order within the column, and is output as the first row to the last row of the matrix in sequence to form a matrix rotated 90° of the matrix to be converted.

[0104] Clause A17, a matrix conversion method according to any one of clauses A10-A16, wherein when the matrix conversion mode is a matrix rotation of 180°, the method comprises:

[0105] Each row of the matrix to be converted is stored in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and each row of the intermediate matrix is ​​read in the cache storage array in an order from the last row to the first row of the intermediate matrix and in order within the row, and is output in sequence as the first row to the last row of the matrix to form a matrix rotated 180° of the matrix to be converted.

[0106] Clause A18, a matrix conversion method according to any one of clauses A10-A17, wherein when the matrix conversion mode is a mirror mode, the method comprises:

[0107] Each row of the matrix to be converted is stored in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and each row of the intermediate matrix is ​​read in the cache storage array in an order from the last row to the first row of the intermediate matrix and in reverse order within the row and outputted in sequence as the first row to the last row of the matrix to form a mirror matrix of the matrix to be converted.

[0108] Item A19, an integrated circuit chip, comprising a matrix conversion circuit according to any one of items A1-A9.

[0109] Item A20, a computing device comprising a matrix conversion circuit according to any one of Items A1-A9 or an integrated circuit chip according to Item A19.

[0110] Item A21, a board comprising a computing device according to Item A20.

[0111] The embodiments of the present disclosure are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present disclosure, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

[0112] It should be understood that the terms "first", "second", "third", "fourth", etc. in the claims, specifications and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections.

[0113] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0114] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0115] The embodiments of the present disclosure are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present disclosure. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present disclosure, the specific implementation methods and the scope of application of the present disclosure, all belong to the scope of protection of the present disclosure. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A matrix conversion circuit, include: A storage array determination circuit, which is used to determine the size of the cache storage array according to the matrix size information of the matrix to be converted, wherein the storage array determination circuit is used to determine the size of the cache storage array according to the number of rows X, the number of columns Y and the storage space K occupied by the basic elements of the matrix to be converted, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, and the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y; as well as A conversion processing circuit is used for storing and reading the matrix to be converted in the cache storage array according to an access method corresponding to a matrix conversion mode, so as to convert the matrix to be converted, wherein the matrix conversion mode includes a matrix transposition mode, a matrix rotation of 270°, a matrix rotation of 90°, a matrix rotation of 180° and a mirror mode. 2 . The matrix conversion circuit according to claim 1 , wherein the matrix conversion circuit further comprises a first acquisition circuit, which is used to acquire matrix size information of the matrix to be converted. 3 . The matrix conversion circuit according to claim 1 , wherein the matrix conversion circuit further comprises a second acquisition circuit for acquiring the matrix conversion mode.

4. The matrix conversion circuit according to claim 1, wherein when the matrix conversion mode is a matrix transposition mode, the conversion processing circuit is used to store each row of the matrix to be converted in a corresponding row in the cache storage array according to the intra-row order to form an intermediate matrix, and read each column of the intermediate matrix in the cache storage array in the order from the first column to the last column of the intermediate matrix and in the intra-column order, and output them as the first row to the last row of the matrix in sequence to form a transposed matrix of the matrix to be converted.

5. The matrix conversion circuit according to claim 1, wherein when the matrix conversion mode is a matrix rotation of 270°, the conversion processing circuit is used to store each row of the matrix to be converted in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and read each column of the intermediate matrix in the cache storage array in order from the first column to the last column of the intermediate matrix and in order within the column, and output them as the first row to the last row of the matrix in sequence to form a matrix of the matrix to be converted rotated 270°.

6. The matrix conversion circuit according to claim 1, wherein when the matrix conversion mode is a matrix rotation of 90°, the conversion processing circuit is used to store each row of the matrix to be converted in a corresponding row in the cache storage array according to the order within the row to form an intermediate matrix, and read each column of the intermediate matrix in the cache storage array in the order from the first column to the last column of the intermediate matrix and in reverse order within the column, and output them as the first row to the last row of the matrix in sequence, so as to form a matrix of the matrix to be converted rotated by 90°.

7. The matrix conversion circuit according to claim 1, wherein when the matrix conversion mode is a matrix rotation of 180°, the conversion processing circuit is used to store each row of the matrix to be converted in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and read each row of the intermediate matrix in the cache storage array in the order from the last row to the first row of the intermediate matrix and in the order within the row, and output them as the first row to the last row of the matrix in sequence, so as to form a matrix of the matrix to be converted rotated 180°.

8. The matrix conversion circuit according to claim 1, wherein when the matrix conversion mode is set to a mirror mode, the conversion processing circuit is used to store each row of the matrix to be converted in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and read each row of the intermediate matrix in the cache storage array in the order from the last row to the first row of the intermediate matrix and in reverse order within the row and output them in sequence as the first row to the last row of the matrix to form a mirror matrix of the matrix to be converted.

9. A matrix conversion method, include: Determine the size of the cache storage array according to the matrix size information of the matrix to be converted, wherein the size of the cache storage array is determined according to the number of rows X, the number of columns Y and the storage space K occupied by the basic elements of the matrix to be converted, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, and the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y; According to the access method corresponding to the matrix conversion mode, the matrix to be converted is stored and read in the cache storage array to convert the matrix to be converted, wherein the matrix conversion mode includes a matrix transposition mode, a matrix rotation of 270°, a matrix rotation of 90°, a matrix rotation of 180° and a mirror mode.

10. The matrix conversion method according to claim 9, wherein before determining the size of the cache storage array according to the matrix size information of the matrix to be converted, the matrix conversion method further include: Obtain the matrix size information of the matrix to be converted.

11. The matrix conversion method according to claim 9, wherein before storing and reading the matrix to be converted in the cache storage array, the matrix conversion method further comprises obtaining a matrix conversion mode.

12. The matrix conversion method according to claim 9, wherein when the matrix conversion mode is a matrix transposition mode, the method include: Each row of the matrix to be converted is stored in a corresponding row in the cache storage array according to an intra-row order to form an intermediate matrix, and each column of the intermediate matrix is ​​read in the cache storage array in an order from the first column to the last column of the intermediate matrix and in an intra-column order, and is sequentially output as the first row to the last row of the matrix to form a transposed matrix of the matrix to be converted.

13. The matrix conversion method according to claim 9, wherein when the matrix conversion mode is a matrix rotation of 270°, the method include: Each row of the matrix to be converted is stored in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and each column of the intermediate matrix is ​​read in the cache storage array in an order from the first column to the last column of the intermediate matrix and in an order within the column, and is output in sequence as the first row to the last row of the matrix to form a matrix rotated 270° of the matrix to be converted.

14. The matrix conversion method according to claim 9, wherein when the matrix conversion mode is a matrix rotation of 90°, the method include: Each row of the matrix to be converted is stored in a corresponding row in the cache storage array according to the order within the row to form an intermediate matrix, and each column of the intermediate matrix is ​​read in the cache storage array in the order from the first column to the last column of the intermediate matrix and in reverse order within the column, and is output as the first row to the last row of the matrix in sequence to form a matrix rotated 90° of the matrix to be converted.

15. The matrix conversion method according to claim 9, wherein when the matrix conversion mode is a matrix rotation of 180°, the method include: Each row of the matrix to be converted is stored in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and each row of the intermediate matrix is ​​read in the cache storage array in an order from the last row to the first row of the intermediate matrix and in order within the row, and is output in sequence as the first row to the last row of the matrix to form a matrix rotated 180° of the matrix to be converted.

16. The matrix conversion method according to claim 9, wherein when the matrix conversion mode is a mirror mode, the method include: Each row of the matrix to be converted is stored in a corresponding row in the cache storage array in reverse order within the row to form an intermediate matrix, and each row of the intermediate matrix is ​​read in the cache storage array in an order from the last row to the first row of the intermediate matrix and in reverse order within the row and outputted in sequence as the first row to the last row of the matrix to form a mirror matrix of the matrix to be converted.

17. An integrated circuit chip comprising the matrix conversion circuit according to any one of claims 1-8.

18. A computing device, comprising the matrix conversion circuit according to any one of claims 1 to 8 or the integrated circuit chip according to claim 17.

19. A board comprising the computing device according to claim 18.

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