Numerical statistics system and numerical statistics method

Abstract

This application provides a numerical statistics method and a numerical statistics system for executing the method. The numerical statistics system transmits the statistical data to be collected to a first arithmetic unit, which includes multiple arithmetic circuits and an addition circuit. The multiple comparison circuits simultaneously receive the statistical data and output comparison results. The comparison results are transmitted to the multiple addition circuits, which output sum data. The sum data is transmitted to a second arithmetic unit for accumulation, and the accumulation result is stored in a memory, completing the statistical analysis.

Description

Technical Field

[0001] This disclosure relates to the field of data processing, and in particular to a statistical system and method for numerical data. Background Technology

[0002] Big data refers to data sets that cannot be captured, managed, and processed within a certain timeframe using conventional software tools. It represents massive, rapidly growing, and diverse information assets that require new processing models to achieve stronger decision-making, insightful discovery, and process optimization capabilities. Data mining and processing are receiving increasing attention from companies.

[0003] Data can be carried in various ways, such as images, text, video, and audio. A crucial step in data processing is statistical analysis. For example, when processing image data, grayscale value calculation is a vital step in image data analysis. Creating a histogram of pixel values ​​for an image reflects the distribution of pixel values, i.e., counting the frequency of different pixel values. Generally, this statistical process requires traversing all possible pixel values ​​or pixel ranges, and each time a pixel value is counted, the entire image needs to be traversed. Therefore, this process often requires sequentially counting each pixel value or value range, resulting in significant time overhead; furthermore, it requires multiple image reads, leading to substantial memory access and energy consumption. Similarly, the same issues arise when processing text and numerical information.

[0004] Therefore, it is necessary to develop a new numerical statistical system and method that can more quickly calculate image grayscale values ​​and text information while reducing energy consumption. Summary of the Invention

[0005] To address the issues of high energy consumption and low efficiency in the analysis and statistical processing of image, video, text, and audio data, this disclosure provides a numerical statistical method and a system for executing the method. This system can read multiple target data sets in parallel and simultaneously count the frequency of occurrences of a specific data value within those sets. Furthermore, the system can reuse the multiple target data sets and simultaneously count the frequency of occurrences of multiple data values. The numerical statistical system provided in this disclosure effectively reduces the time-consuming, memory-intensive, and energy-intensive problems associated with the analysis of image, video, text, and audio data.

[0006] This disclosure provides a numerical statistics system. The numerical statistics system includes a first arithmetic unit, which comprises at least N arithmetic circuits, where N is a positive integer. Each arithmetic circuit includes: n comparators that receive n input data during operation, where n is an integer greater than 1; each comparator, during operation, receives a corresponding input data and at least one corresponding reference data; when the corresponding input data and the corresponding reference data satisfy a preset condition, the output data of the comparator is a first value; otherwise, the output data is a second value; and an addition circuit that, during operation, adds the n output data of the n comparators to sum the sum data and outputs the sum.

[0007] According to some embodiments of this disclosure, the n comparators receive the n input data and / or the at least one reference data in parallel during operation.

[0008] According to some embodiments of this disclosure, when the first arithmetic unit is running, the n comparators output their respective output data to the adder circuit.

[0009] According to some embodiments of this disclosure, the n comparators are connected to the addition circuit in parallel; the addition circuit includes multiple adders connected in a tree structure; the tree structure includes m leaf node adders and a root node adder, where m is a positive integer; the output of each of the n comparators is connected to one input of each of the m leaf node adders; and the output of the root node adder outputs the sum data.

[0010] According to some embodiments of this disclosure, the n comparators are connected in parallel to the addition circuit; the addition circuit includes at least n adders connected in series; and the output data of each of the n comparators is input to the input terminal of one of the n adders.

[0011] According to some embodiments of this disclosure, the numerical statistics system further includes a second arithmetic unit connected to the first arithmetic unit. When the second arithmetic unit operates, it receives the sum data output by the N arithmetic circuits respectively, and adds the sum data output by the N arithmetic circuits respectively to the corresponding accumulated data.

[0012] According to some embodiments of this disclosure, the second arithmetic unit, during operation, adds the sum data output by the N arithmetic circuits to the accumulated data in parallel.

[0013] According to some embodiments of this disclosure, the second arithmetic unit includes at least K accumulator circuits corresponding to the N arithmetic circuits, where K is a natural number. Each accumulator circuit includes at least: an adder, including: a first input terminal for receiving the sum data, a second input terminal for receiving the accumulated data, and an output terminal for outputting updated accumulated data, wherein the updated accumulated data is the sum of the sum data and the accumulated data; and a memory for storing the updated accumulated data.

[0014] According to some embodiments of this disclosure, the second arithmetic unit includes at least one vector accumulation circuit, which includes: N adders corresponding to the N arithmetic circuits, each adder including: a first input terminal for receiving the sum data of the corresponding arithmetic circuit, a second input terminal for receiving the corresponding accumulation data, and an output terminal for outputting updated accumulation data, the updated accumulation data being the sum of the sum data and the corresponding accumulation data; a vector synthesis circuit that receives the N updated accumulation data output by the N adders in parallel and synthesizes the N updated accumulation data into an accumulation vector; and a memory including: an input terminal for receiving the accumulation vector and an output terminal for inputting the N updated accumulation data in the accumulation vector into the second input terminal of the corresponding adder.

[0015] According to some embodiments of this disclosure, the vector accumulation circuit includes: a vector synthesis circuit that receives N sum data output from the N arithmetic circuits and synthesizes the N sum data into a sum vector; an adder including: a first input terminal for receiving the sum vector, a second input terminal for receiving an accumulation vector, the accumulation vector including the corresponding accumulation data, and an output terminal for outputting an updated accumulation vector, the updated accumulation vector being the sum of the sum vector and the accumulation vector; and a memory including: an input terminal for receiving the accumulation vector and an output terminal for inputting the accumulation vector into the second input terminal of the adder.

[0016] According to some embodiments of this disclosure, the numerical statistics system further includes: a memory connected to the first arithmetic unit, which stores target data and sends the target data to the N arithmetic circuits during operation, the target data including the n input data; and / or the memory connected to the second arithmetic unit, which stores target data and transmits the target data to the second arithmetic unit during operation, wherein the second arithmetic unit transmits the calculation result to the memory during operation.

[0017] According to some embodiments of this disclosure, the numerical statistics system further includes interconnect circuits connected to the second arithmetic unit and the first arithmetic unit. During operation: it receives target data from the second arithmetic unit and transmits the target data to the first arithmetic unit; it receives N sum data output by the N arithmetic circuits in parallel and transmits the N sum data to the second arithmetic unit; and it concatenates the N sum data into a sum data vector and transmits the sum data vector to the second arithmetic unit.

[0018] According to some embodiments of this disclosure, when the second arithmetic unit runs, it sends corresponding N reference data to the N arithmetic circuits respectively, and the N reference data have the same value.

[0019] According to some embodiments of this disclosure, when the second arithmetic unit is running, it sends corresponding N reference data to the N arithmetic circuits respectively, and the values ​​of the N reference data are different.

[0020] According to some embodiments of this disclosure, the n input data include data for which histogram statistics need to be performed.

[0021] According to some embodiments of this disclosure, the n input data include one or more of the pixel data, vector data, and matrix data of the target image.

[0022] Another aspect of this disclosure provides a numerical statistical method applied to a chip circuit. The chip circuit includes N arithmetic circuits in a first arithmetic unit, each arithmetic circuit including an adder circuit and n comparators, where N is a positive integer and n is an integer greater than 1. The numerical statistical method comprises: receiving n input data and at least one reference data through the n comparators, each input data corresponding to one of the at least one reference data; when each of the n input data and its corresponding reference data satisfies a preset condition, outputting a first value through the n comparators, otherwise outputting a second value; summing the n output data through the adder circuit to obtain a sum data; and outputting the sum data.

[0023] According to some embodiments of this disclosure, receiving n input data and at least one reference data includes: receiving the n input data in parallel and / or receiving the at least one reference data in parallel.

[0024] According to some embodiments of this disclosure, the chip circuit further includes a second arithmetic unit, and the numerical statistics method further includes, through the second arithmetic unit: receiving the N sum data; and adding the sum data output by the N arithmetic circuits respectively to the corresponding accumulated data.

[0025] According to some embodiments of this disclosure, adding the sum data output by the N arithmetic circuits to the corresponding accumulated data includes: adding the sum data output by the N arithmetic circuits to the accumulated data in parallel.

[0026] According to some embodiments of this disclosure, the numerical statistics method further includes: receiving N sum data output by the N arithmetic circuits and combining the N sum data into a sum vector; wherein adding the sum data output by the N arithmetic circuits to the corresponding accumulated data includes: performing vector addition on the sum data output by the N arithmetic circuits to the corresponding accumulated data.

[0027] According to some embodiments of this disclosure, the numerical statistics method further includes: sending corresponding N reference data to the N arithmetic circuits through the second arithmetic unit, wherein the N reference data have the same value.

[0028] According to some embodiments of this disclosure, the numerical statistics method further includes sending corresponding N reference data to the N arithmetic circuits through the second arithmetic unit, wherein the N reference data values ​​are different.

[0029] According to some embodiments of this disclosure, the n input data include data for which histogram statistics need to be performed.

[0030] According to some embodiments of this disclosure, the n input data include one or more of the pixel data, vector data, and matrix data of the target image.

[0031] In summary, the numerical statistics system and method disclosed herein, on the one hand, reduces memory access and energy consumption by reusing read data through multiple arithmetic units; on the other hand, it reduces the time spent analyzing data and improves the efficiency of numerical statistics of data such as images, videos, text, and audio by using comparison circuits to perform parallel calculations and output multiple numerical statistics results at once, thereby reducing the time spent analyzing data and reducing energy consumption. Attached Figure Description

[0032] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this disclosure. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of this disclosure. Other embodiments may similarly fulfill the inventive intent of this disclosure. It should be understood that the drawings are not drawn to scale. Wherein:

[0033] Figure 1 This is a circuit diagram of a numerical statistics system provided according to some embodiments of this disclosure;

[0034] Figure 2 This is a schematic diagram of a first arithmetic unit of a tree-structured adder circuit provided according to some embodiments of this disclosure;

[0035] Figure 3 This is a schematic diagram of the first arithmetic unit of a multi-stage pipelined adder circuit provided according to some embodiments of this disclosure;

[0036] Figure 4 This is a schematic diagram of an accumulator provided according to some embodiments of this disclosure;

[0037] Figure 5 This is a schematic diagram of a vector accumulation circuit provided according to some embodiments of this disclosure;

[0038] Figure 6 This is a schematic diagram of another vector accumulation circuit provided according to some embodiments of this disclosure;

[0039] Figure 7 This is a structural diagram illustrating a combined processing apparatus 700 according to an embodiment of the present disclosure;

[0040] Figure 8 This is a schematic diagram illustrating the structure of a board 800 according to an embodiment of this disclosure; and

[0041] Figure 9 A numerical statistical method according to some embodiments of this disclosure is illustrated. Detailed Implementation

[0042] The following description provides specific application scenarios and requirements for this disclosure, intended to enable those skilled in the art to make and use the content of this disclosure. Various partial modifications to the embodiments of this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0043] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not restrictive. For example, unless the context clearly indicates otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. When used in this specification, the terms “comprising,” “including,” and / or “containing” mean the presence of the associated integers, steps, operations, elements, and / or components, but do not exclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups, or the possibility of adding other features, integers, steps, operations, elements, components, and / or to the system / method. When used in this specification, the term “A on B” can mean that A is directly adjacent to B (above or below) or that A and B are indirectly adjacent (i.e., there is some substance between A and B); the term “A within B” can mean that A is entirely inside B or that A is partially inside B.

[0044] In view of the following description, these and other features of this disclosure, as well as the operation and function of the related components of the structure, and the economy of assembly and manufacture of the parts, can be significantly improved. All of these form part of this disclosure, with reference to the accompanying drawings. However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of this disclosure.

[0045] Furthermore, certain terms in this disclosure have been used to describe embodiments of this disclosure. For example, "an embodiment," "an embodiment," and / or "some embodiments" mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least one embodiment of this disclosure. Therefore, it is to be emphasized and understood that two or more references to "an embodiment" or "an embodiment" or "alternative embodiment" in various parts of this specification do not necessarily refer to the same embodiment. Moreover, specific features, structures, or characteristics may be appropriately combined in one or more embodiments of this disclosure.

[0046] In some embodiments, figures used to describe and claim certain embodiments of this disclosure, expressing quantities or properties, should be understood to be modified in certain circumstances by the terms “about,” “approximately,” or “substantially.” For example, unless otherwise stated, “about,” “approximately,” or “substantially” may represent a common understanding in the art of the art covered by this disclosure, such as a variation of ±10% of the value described. Therefore, in some embodiments, the numerical parameters listed in the written description and appended claims are approximate values ​​that may vary depending on the desired properties sought to be obtained in a particular embodiment. In some embodiments, numerical parameters should be interpreted based on the number of significant figures reported and by applying common rounding techniques. Although some embodiments of this disclosure set forth a wide range of numerical ranges and parameters that are approximate, specific embodiments have listed numerical values ​​that are as accurate as possible.

[0047] The technical solution of the present invention will be described in detail below with reference to embodiments and accompanying drawings. This specification will use the statistical analysis of grayscale values ​​of image pixels as an example to illustrate the technical solution of the present invention. Those skilled in the art will understand that the numerical statistical system disclosed in this specification, in addition to grayscale images, can also perform statistical analysis on any data that requires and can be histogram-based, such as video, audio, text, and matrix data.

[0048] A histogram, also known as a quality distribution chart, is a statistical reporting graph that uses a series of vertical bars or lines of varying heights to represent the distribution of data. Generally, the horizontal axis represents the data type, and the vertical axis represents the distribution. Pixel value statistics are a type of image data analysis. Histograms can be applied to pixel value statistics. For example, a histogram of pixel value distribution can be created for an image. That is, the frequency of different pixel values ​​or ranges of pixel values ​​can be counted. Then, the horizontal axis represents the different pixel values ​​and / or ranges of pixel values, and the vertical axis represents the frequency of the corresponding pixel values ​​and / or ranges of pixel values ​​in the image. This results in a rectangular chart, namely the pixel statistical histogram of the image. This histogram can be used to reflect the distribution of pixel values ​​in the image.

[0049] Grayscale images have wide applications in medicine and image recognition. Therefore, the statistical analysis of grayscale image values ​​is very common. A grayscale image is an image where pixels are represented by black as the base color, using different saturations of black. 0% black saturation is white, and 100% black saturation is black. White and black are separated into several levels according to a logarithmic relationship, called grayscale levels, typically ranging from 0 to 255.

[0050] Figure 1This is a circuit diagram of a numerical statistics system 100 provided according to some embodiments of the present disclosure. The numerical statistics system 100 includes at least a first arithmetic unit 110 and a second arithmetic unit 140. Furthermore, the numerical statistics system 100 may also include interconnect circuitry 150, a controller 160, and a memory 170.

[0051] The first arithmetic unit 110 includes at least N arithmetic circuits 110-1, 110-2...110-N, where N is a positive integer. For example, N = 16, 32, 64, or 128, etc. The N arithmetic circuits can receive data and perform operations serially or in parallel.

[0052] Figure 2 A schematic diagram of an arithmetic circuit 200 according to some embodiments of this disclosure is shown. In some embodiments, the arithmetic circuit 200 can be applied to at least one of the N arithmetic circuits 110-1, 110-2, ..., 110-(N-1), 110-N. The arithmetic circuit 200 may include at least one adder circuit 220 and n comparators 210. Here, n is an integer greater than 1, such as n = 4, 8, 16, 32, 64, or 128, etc.

[0053] Each of the n comparators 210 (210-1, 210-2, 210-3...210-n) includes at least one input terminal i to receive at least one input data, at least one reference terminal r to receive at least one reference data, and an output terminal O. During operation, the n comparators 210 can receive n input data in parallel at their respective input terminals, or receive the n input data separately, or receive the n input data in any preset interrelated manner. During operation, the n comparators 210 can also receive n reference data in parallel at their respective reference terminals, or in any preset manner. Each comparator (210-1, 210-2, 210-3...210-n) can set its own reference data value for its reference terminal, or the reference data values ​​for the reference terminals of all n comparators 210 can be set uniformly. During operation, the comparator receives input data from input terminal i and reference data from reference terminal r. When the corresponding input data and the corresponding reference data satisfy a preset condition, the comparator outputs a first value; otherwise, the output data is a second value. The preset condition can be the relationship between the input data and the reference data. For example, when the comparator has only one reference terminal, the preset condition can be whether the input data and the reference data are equal; when the comparator includes multiple reference terminals receiving multiple reference data, the preset condition can be that the input data falls within the interval defined by the multiple reference data. The first value can be 1 (e.g., high level), and the second value can be 0 (e.g., low level); the first and second values ​​can also be any other pre-set numbers. For example, for comparator 210-1, its input terminal is i1, its reference terminal is r1, and its output terminal is O1. When the reference data input to the reference terminal r1 is 10 and the input data input to the input terminal i1 is 9, the input data 9 is not equal to the reference data 10, so the comparator outputs 0. When the input data to the input terminal i1 is 10, the input data is equal to the reference data 10, so the comparator outputs 1 to 1. Since the comparator output is the comparison result between the input terminal and the reference terminal, its output can be understood as either the comparison result of the input terminal relative to the reference terminal or the comparison result of the reference terminal relative to the input terminal.

[0054] When the first arithmetic unit 110 is running, the n comparators 210 output their respective data to the adder circuit 220. The adder circuit 220 may include multiple adders. Each adder consists of at least two input terminals and one output terminal. When data is input to the two input terminals, the output of the adder terminal is the sum of the data from the two input terminals. For example, adder 224-1 has two input terminals, which are respectively connected to the output terminal O1 of comparator 210-1 and the output terminal O2 of comparator 210-2. Adder 224-1 also has an output terminal P1, where P1 = O1 + O2. If the output data of output terminal O1 is 1 and the output data of output terminal O2 is also 1, then the output of adder 224-1 is 2.

[0055] The multiple adders can be connected in a tree structure. The tree structure can be a binary tree, a tribranch tree, a multibranch tree, or a tree structure with arbitrary branching. The tree structure includes m leaf node adders and one root node adder, where m is a positive integer. For example, Figure 2 The illustrated adder circuit is a three-layer binary branching tree structure. Adder 221 is the root node adder, and adder 224 (including adders 224-1, 224-2, 224-3, 224-4...224-(m-1), 224-m, etc., on the same layer) are leaf node adders. Adder 223 (including adders 223-1, 223-2, 223-3, 223-4, etc., on the same layer) and adder 222 (including adders 222-1, 222-2, etc., on the same layer) are intermediate node adders between the leaf node adders and the root node adder. Those skilled in the art will understand that the tree structure ascends from the leaf node to the root node. Therefore, the output of any intermediate node adder is connected to the input of the adder on the previous layer, and its input is connected to the output of at least one adder on the next lower layer.

[0056] Furthermore, the n comparators 210 are connected to the adder circuit in parallel. Specifically, the n comparators are connected in parallel to the m leaf node adders of the adder circuit. Each comparator is connected to at least one leaf node adder. For example... Figure 2In this configuration, except for the leaf node adder 224-m, whose input is connected to only one comparator 210-n, the inputs of the other leaf node adders 224-1, 224-2, 224-3, 224-4…224-(m-1) are each connected to two comparators 210-1…210-(n-1). Alternatively, all leaf node adders could be connected to two comparators. From this perspective, the n comparators 210 correspond to the leaf nodes of the tree-connected multiple adder circuits 220. Default values ​​can be preset for unused inputs. For example, an unused input can be preset to 0, or it can be preset to 1.

[0057] In this structure, the output data of the n comparators 210 are respectively fed into the input of a leaf node adder for addition. The output data of each leaf node adder is then used as input data to the input of the intermediate node adder in the next layer for addition. The output data of the next layer adder is fed into the input of the previous layer adder, and the sum obtained after addition by the previous layer adder is fed into the adder in the next layer, and so on until the root node adder. The output of the root node adder is the sum of the output data of all comparators, i.e., the sum data, P. n =O1+O2+O3+…+O n .

[0058] Since the comparator's output is the comparison result between the input terminal and the reference terminal, its output can be interpreted as either the comparison result of the input terminal relative to the reference terminal or the comparison result of the reference terminal relative to the input terminal. Therefore, the sum data P n This can be either the statistical result of the reference data relative to the input data at the comparator input terminal and the reference data at the reference terminal, or the statistical result of the reference data relative to the input data.

[0059] Figure 3 A schematic diagram of the structure of an arithmetic circuit 300 according to some embodiments of this disclosure is shown. In some embodiments, the arithmetic circuit 300 can be applied to at least one of the N arithmetic circuits 110-1, 110-2, ..., 110-(N-1), 110-N. The arithmetic circuit 300 may include at least one adder circuit 320 and n comparators 310. Here, n is an integer greater than 1, such as n = 4, 8, 16, 32, 62, or 128, etc.

[0060] The adder circuit 320 includes at least n adders 320-1, 320-2...320-n connected in series. For example, except for the first adder 320-1 (which has no input or an initial value input) and the last adder 320-n (which serves as the total output), the output of each adder is connected to an input of a neighboring adder. The n comparators 310 are connected to the adder circuit 320 in parallel, meaning that the output data of each comparator 310 is input to the input of one of the n adders 320. The outputs of the adders are connected in series to the inputs of neighboring adders. During operation, the n comparators 310 can receive n input data in parallel at their respective inputs, or they can receive the n input data individually or in conjunction. Furthermore, each comparator 310 (310-1, 310-2, 310-3...310-n) can have its own reference terminal value set, or the reference terminal values ​​of all n comparators 310 can be set uniformly. When the first arithmetic unit 110 is running, the n comparators 310 output their respective output data to the adder circuit 320.

[0061] For example, in Figure 3 In this configuration, adder 320-1 is connected in series with adder 320-2, meaning the input terminal P1 of adder 320-1 is connected in series with adder 320-2. The output terminal P2 of adder 320-2 is connected in series with adder 320-3, and so on, connected in series to the nth adder 320-n. Simultaneously, the other input terminal of each adder is connected to the output terminal of a comparator. For example, in... Figure 3 In this circuit, one input terminal of adder 320-1 is connected to the output terminal O1 of comparator 310-1; one input terminal of adder 320-2 is connected to the output terminal of comparator 310-2, and so on. Thus, the addition circuit is composed of n adders connected in series, and the output terminal of each of the n comparators 310 is connected to one of the adders in the addition circuit 320. Of course, those skilled in the art will understand that the output terminals of each or some of the n comparators 310 can also be connected to multiple adders in the addition circuit 320, or the input terminal of each or some of the adders in the addition circuit 320 can be connected to the outputs of one or more comparators. Figure 3 The connection between the adder and comparator can be configured as needed to control the use of certain components.

[0062] When the arithmetic circuit 300 operates, each of the n adders 320 adds the output data of the previous stage adder to the output data of the comparator connected to its other input terminal, and inputs the sum to the next stage adder. For example, the input P1 of adder 320-1 is O0 + O1. Figure 3 In this circuit, terminal O0 is an unused terminal, with the input data being 0, therefore P1 = O1. Of course, terminal O0 can also be connected to other circuits (such as a comparator) to receive input data. Adder 320-1 inputs the data from terminal P1 to one input of the next-stage adder 320-2. The other input of adder 320-2 receives the input data O2 from comparator 310-2, then sums the data from its two inputs to obtain P2 = P1 + O2 = O1 + O2, and then inputs P2 as the output data to one input of the next-stage adder 320-3. This process continues, allowing the arithmetic circuit 300 to sum the outputs of all n comparators and output the sum at the output of the last adder 320-n. n Output the data, P n =O1+O2+O3+…+O n .

[0063] Figure 2 The operational circuit 200 and Figure 3The computational circuit 300 can perform statistical analysis on any digitized target data. Furthermore, the computational circuits 200 and 300 can perform statistical analysis on the target data in parallel. For example, the computational circuit 200 can be used to count the grayscale values ​​of a batch of pixels in a grayscale image. In this case, the reference terminal r of each comparator in the computational circuit 200 can be set to the reference grayscale value of the pixel to be counted, and then the corresponding grayscale values ​​of the batch of pixels are input into each comparator in the computational circuit 200. For example, assuming there are 16 comparators in the computational circuit 200, i.e., n = 16, then the computational circuit 200 can count the grayscale values ​​of 16 pixels individually or in parallel. For a 256-level grayscale image, the grayscale value of each pixel can be any value between 0 and 255. Assuming a batch of 16 pixels has grayscale values ​​of (0, 1, 3, 4, 6, 8, 2, 19, 8, 5, 7, 2, 2, 4, 6, 2), the arithmetic circuit 200 can simultaneously receive these 16 pixel grayscale values. That is, each comparator in the arithmetic circuit 200 can simultaneously (in parallel) receive one of the 16 pixel grayscale values. Each comparator in the arithmetic circuit 200 can set its own reference grayscale value, or the reference grayscale value for all comparators can be uniformly set. For ease of explanation, it is assumed that the reference grayscale value for all comparators is uniformly set to 2. After receiving its respective pixel grayscale value, each comparator compares its received pixel value with the number 2. When the received pixel value equals 2, the output is 1; when the received pixel value is not equal to 2, the output is 0. Thus, only the comparators at bits 7, 12, 13, and 16 output 1, while the outputs of the remaining comparators are 0. Each comparator in the arithmetic circuit 200 inputs its own output data into the adder circuit 220 for summation. Finally, the output of the root node adder 221 is 4, which means that among this batch of pixels, there are 4 pixels with a gray value of 2, so the sum data is 4.

[0064] Of course, besides counting pixel values ​​in grayscale images, those skilled in the art will readily recognize that arithmetic circuits 200 and 300 can also be used to perform other statistical tasks. For example, counting pixel values ​​in color images, numerical values ​​in vectors or matrices, and / or numerical values ​​in other arrays.

[0065] The first arithmetic unit 110 contains N arithmetic circuits. In some embodiments, the reference values ​​of all N arithmetic circuits can be set to the same value, allowing the first arithmetic unit 110 to perform statistical analysis on N×n data points at once. The first arithmetic unit 110 can also reuse input data. For example, the arithmetic circuits can set different reference values ​​for each of the N arithmetic circuits and then input the same n data points to each circuit. In this way, using a set of n data points, the first arithmetic unit 110 can simultaneously perform statistical analysis on N reference values.

[0066] The second arithmetic unit 140 is connected to the first arithmetic unit 110. In this disclosure, the connection includes any form of connection capable of directly or indirectly receiving information. This disclosure does not limit the data transmission method or transmission topology. For example, the second arithmetic unit 140 can be directly connected to the first arithmetic unit 110 via an electrical connection to transmit data and / or signals; the second arithmetic unit 140 can also establish an indirect connection with the first arithmetic unit 110 by directly connecting to other circuits via an electrical connection, thereby realizing the transmission of data and / or signals. For example, in... Figure 1 In this configuration, the second arithmetic unit 140 can be indirectly connected to the first arithmetic unit 110 via the memory 170 and the interconnect circuit 150, thereby enabling data transfer. Alternatively, the second arithmetic unit 140 can directly connect to a data bus and acquire data, or it can be connected via a FatTree structure or by extending different topologies. The connection can perform one-to-one data transfer, such as the second arithmetic unit 140 transmitting specific target data to a specific arithmetic circuit in the first arithmetic unit 110; the connection can also perform data transfer in a broadcast manner, such as the second arithmetic unit 140 broadcasting specific target data to each arithmetic circuit in the first arithmetic unit 110.

[0067] Specifically, when the second arithmetic unit 140 is running, it can receive the sum data output by the N arithmetic circuits 110-1, 110-2, ..., 110-N, respectively, or in parallel, and add the sum data output by the N arithmetic circuits 110-1, 110-2, ..., 110-N to the corresponding accumulated data. Further, when the second arithmetic unit 140 is running, it can add the sum data output by the N arithmetic circuits 110-1, 110-2, ..., 110-N to the accumulated data, respectively, or in parallel.

[0068] Figure 4 This is a schematic diagram of an accumulator 400 provided according to some embodiments of the present disclosure. In some embodiments, the accumulator 400 may be applied to the second arithmetic unit 140 to become at least a part of the second arithmetic unit 140.

[0069] The accumulator 400 may include multiple accumulation circuits. For example, the accumulator 400 may include at least K accumulation circuits 410-1, 410-2... 410-N, where K is a natural number. K may be the same natural number as N or a different natural number from N. In some embodiments, each accumulation circuit may be connected to a corresponding operation circuit in the first arithmetic unit 110. For example, (1) when K = N, each of the accumulation circuits may be connected to the operation circuits in a one-to-one correspondence; (2) when K < N, each of the accumulation circuits may be connected to the operation circuits in a one-to-many manner; or (3) each of the accumulation circuits may be connected to the operation circuits in a many-to-many manner. For example, the accumulation circuit 410-1 may be connected to the operation circuit 110-1. Of course, each of the accumulation circuits may also be connected to multiple operation circuits, and each of the operation circuits may also be connected to multiple accumulation circuits. In the following description, the present disclosure describes the invention disclosed in the present disclosure by taking the case described in (1) above as an example.

[0070] Each of the accumulation circuits includes at least one adder and one memory. The output of the adder is connected to the input / output terminal of the memory, and the input / output terminal of the memory is simultaneously connected to one input terminal of the adder to feed back the stored data to the adder.

[0071] Taking the accumulation circuit 410-1 as an example, it may at least include an adder 430-1 and a memory 450-1. The adder 430-1 may at least include one output terminal C1 and two input terminals, namely a first input terminal A1 and a second input terminal B1. When the first input terminal A1 is connected to an operation circuit 110-1 of the first arithmetic unit, the first input terminal A1 receives the sum data 420-1 output therefrom. The second input terminal B1 may be connected to the memory 450-1 to receive the feedback data 460-1 transmitted from the memory 450-1. When the data stored in the memory 450-1 is the historical accumulation data obtained in the previous operation cycle, the feedback data 460-1 is the historical accumulation data. At this time, the adder 430-1 adds the sum data 420-1 to the historical accumulation data 460-1 to obtain the current accumulation data 440-1 of the current operation cycle, that is, the updated accumulation data. And the current accumulation data 440-1 is output from the output terminal C1. The output terminal C1 may be connected to the memory 450-1 and may input the output data 440-1 (i.e., the current accumulation data) of the adder 430-1 into the memory 450-1 to update the historical accumulation data to the current accumulation data.

[0072] Memory 450-1 can be any form of storage medium. For example, memory 450-1 may include registers, mass storage, volatile read-write memory, read-only memory (ROM), or similar content, or any combination thereof. Exemplary mass storage may include non-transitory storage medium such as a hard disk or solid-state drive. Typical volatile read-write memory may include random access memory (RAM). Example RAM may include dynamic RAM (DRAM), double-data-rate synchronous dynamic RAM (DDR SDRAM), static RAM (SRAM), thyristor RAM (T-RAM), and zero-capacitance RAM (Z-RAM), etc. Exemplary ROM may include mask ROM (MROM), programmable ROM (PROM), programmable erasable ROM (PEROM), electrically erasable programmable ROM (EEPROM), and digital multifunction disk ROM, etc.

[0073] The above description uses the accumulator circuit 410-1 as an example to illustrate the case where the memory 450-1 stores historical accumulated data. Of course, the memory 450-1 can also store any data, and the other accumulator circuits 410-2, ... 410-N can also have the same circuit structure as the accumulator short circuit 410-1, which will not be described in detail here.

[0074] The N accumulator circuits 410-1, 410-2, ... 410-N in the accumulator 400 perform scalar accumulation operations on the outputs and data of the corresponding N arithmetic circuits 110-1, 110-2, ... 110-N. According to some embodiments of this disclosure, the arithmetic unit can also perform vector accumulation operations on the outputs and data of the N arithmetic circuits 110-1, 110-2, ... 110-N.

[0075] Figure 5 This is a schematic diagram of a vector accumulation circuit 500 provided according to some embodiments of this disclosure. The accumulation circuit 500 can be applied to the second arithmetic unit 140 and become at least a part of the second arithmetic unit 140.

[0076] The accumulation circuit 500 may include at least N adders 430-1, 430-2...430-N, at least one vector synthesis circuit 540, and at least one storage circuit 550.

[0077] In some embodiments, each adder can be connected to a corresponding arithmetic circuit in the first arithmetic unit 110 (e.g., a one-to-one connection, a one-to-many connection, or a many-to-many connection). For example, adder 430-1 can be connected to arithmetic circuit 110-1 to receive the sum data 420-1 output by arithmetic circuit 110-1. Of course, each adder can also be connected to multiple arithmetic circuits, and each arithmetic circuit can also be connected to multiple accumulator circuits.

[0078] Each adder may include at least one output terminal and two input terminals, namely a first input terminal and a second input terminal. For example, adder 430-1 may include at least one output terminal C1 and two input terminals, namely a first input terminal A1 and a second input terminal B1. When the first input terminal A1 is connected to an arithmetic circuit 110-1 of the first arithmetic unit, the first input terminal A1 receives the sum data 420-1 output by the arithmetic circuit 110-1. The second input terminal B1 may be connected to a memory 550 to receive feedback data 460-1 from the memory 550. When the memory 550 stores historical accumulated data obtained in the previous operation cycle, the feedback data 460-1 is the historical accumulated data. At this time, adder 430-1 adds the sum data 420-1 to the historical accumulated data 460-1 to obtain the current accumulated data 440-1 of the current operation cycle, i.e., the updated accumulated data. The updated accumulated data 440-1 is then output from the output terminal C1.

[0079] The vector synthesis circuit 540 can be any circuit capable of synthesizing or concatenating the N sum data into a single vector. For example, the vector synthesis circuit 540 may include N input terminals, each of which can be the output terminal C1, C2, ... C of an adder. N The N adders 430-1, 430-2, ..., 430-N can then input their updated accumulated data 440-1, 440-2, ..., 440-N in parallel into the vector synthesis circuit 540. The vector synthesis circuit 540 combines the N updated accumulated data into a single updated accumulated vector and inputs it into the storage circuit 550. The updated accumulated vector 542 can have the following form: {440-1, 440-2, ..., 440-N}.

[0080] The memory 550 may include one or more input / output terminals. For ease of description, the input / output terminals are described as including an input terminal E and an output terminal F. The input terminal E can receive the updated accumulation vector 542 and then replace the previously stored historical accumulation vector with the updated accumulation vector. The memory 550 can also feed back specific data 560 to the second input terminals B1, B2, ..., B of the adders 430-1, 430-2, ..., 430-N respectively via the output terminal F. N .

[0081] In some embodiments, the specific data 560 may be the updated accumulation vector 542. In this case, the memory 550 can feed back each updated accumulated data in the updated accumulation vector 542 to the second input of the corresponding adder via its output terminal F. For example, the memory circuit 550 can feed back the updated accumulated data 440-1 in the updated accumulation vector 542 to the second input terminal B1 of the adder circuit 430-1, the updated accumulated data 440-2 to the second input terminal B2 of the adder circuit 430-2, and so on, feeding back the updated accumulated data 440-N to the second input terminal B1 of the adder circuit 430-N. N .

[0082] Memory 550 can be any form of storage medium. For example, memory 550 may include registers, mass storage, volatile read-write memory, read-only memory (ROM), or similar content, or any combination thereof. Exemplary mass storage may include non-transitory storage media such as disks and solid-state drives. Typical volatile read-write memory may include random access memory (RAM). Example RAM may include dynamic RAM (DRAM), double-data-rate synchronous dynamic RAM (DDR SDRAM), static RAM (SRAM), thyristor RAM (T-RAM), and zero-capacitance RAM (Z-RAM), etc. Exemplary ROM may include mask ROM (MROM), programmable ROM (PROM), programmable erasable ROM (PEROM), electrically erasable programmable ROM (EEPROM), and digital multifunction disk ROM, etc.

[0083] Figure 6 This is a schematic diagram of another vector accumulation circuit 600 provided according to some embodiments of this disclosure. The accumulation circuit 600 can be applied to the second arithmetic unit 140 and become at least a part of the second arithmetic unit 140.

[0084] The accumulator circuit 600 may include at least one adder 630, at least one vector synthesis circuit 620, and at least one memory 650.

[0085] The vector synthesis circuit 620 can be any circuit capable of synthesizing or concatenating the N sum data into a single vector. For example, the vector synthesis circuit 620 can have N input terminals D1, D2, ... D N It has one output terminal, and is connected to adder 630 through said output terminal. Each input terminal D1, D2, ... D N All of them can be connected to the corresponding arithmetic circuits in the first arithmetic unit 110 (e.g., one-to-one connection, one-to-many connection, or many-to-many connection). For example, input terminal D1 can be connected to arithmetic circuit 110-1 to receive the sum data 420-1 output by arithmetic circuit 110-1. Of course, each adder can also be connected to multiple arithmetic circuits, and each arithmetic circuit can also be connected to multiple accumulation circuits. Vector synthesis circuit 620 can receive N sum data output by N arithmetic circuits in the first arithmetic unit in parallel, and synthesize the N sum data into a sum vector {420-1, 420-2, ..., 420-N}.

[0086] In some embodiments, the adder 630 may include at least one output terminal C and two input terminals, namely a first input terminal A and a second input terminal B. The vector synthesis circuit 620 can be connected to the first input terminal A of the adder 630 through its output terminal and transmit the sum vector {420-1, 420-2, ..., 420-N} to the adder 630. The second input terminal B of the adder 630 can be connected to the memory 650 to receive feedback data 560 from the memory 650.

[0087] When memory 650 stores the historical accumulation of the sum vector {420-1, 420-2, ..., 420-N} obtained in the previous operation cycle, the feedback data 660 is the historical accumulation vector {420-1, 420-2, ..., 420-N}. At this time, adder 630 adds the sum vector {420-1, 420-2, ..., 420-N} obtained in the current operation cycle to the historical accumulation vector to obtain the current accumulation vector 640 of the current operation cycle, i.e., the updated accumulation vector. The updated accumulation vector 640 is then output from output terminal C. In this disclosure, one operation cycle can be one clock cycle or multiple clock cycles. It is not limited to any particular cycle.

[0088] The memory 650 may include one or more input / output terminals. For ease of description, the input / output terminals are described as including an input terminal E and an output terminal F. The input terminal E can receive the updated accumulation vector 640, then replace the previously stored historical accumulation vector with the updated accumulation vector, and feed the updated accumulation vector 640 as feedback data 660 to the second input terminal B of the adder through the output terminal F.

[0089] Memory 650 can be any form of storage medium. For example, memory 650 may include registers, mass storage, volatile read-write memory, read-only memory (ROM), or similar content, or any combination thereof. Exemplary mass storage may include non-transitory storage media such as disks and solid-state drives. Typical volatile read-write memory may include random access memory (RAM). Example RAM may include dynamic RAM (DRAM), double-data-rate synchronous dynamic RAM (DDR SDRAM), static RAM (SRAM), thyristor RAM (T-RAM), and zero-capacitance RAM (Z-RAM), etc. Exemplary ROM may include mask ROM (MROM), programmable ROM (PROM), programmable erasable ROM (PEROM), electrically erasable programmable ROM (EEPROM), and digital multifunction disk ROM, etc.

[0090] In summary, the first arithmetic unit 110 can perform data statistics on N×n target data in parallel, comparing them with a pre-set reference value to obtain N sum data points; alternatively, it can reuse the n target data points, comparing them with N pre-set reference values ​​to obtain N sum data points. The second arithmetic unit 140 can accumulate the N sum data points output by the first arithmetic unit 110 each time, thereby completing the statistics on a batch of target data in batches. The target data can be images, videos, audio, text data, or any other type of data. Furthermore, the second arithmetic unit 140 can also send the target data to the first arithmetic unit 110. Figure 1 As shown, the second arithmetic unit 140 and the first arithmetic unit 110 can be connected via an interconnection circuit 150, or via a controller 160 and a memory 170.

[0091] During operation, the interconnect circuit 150 can receive the target data from the second arithmetic unit 140 and transmit the target data to the first arithmetic unit 110. For example, the second arithmetic unit 140 can transmit specific target data to a specific arithmetic circuit in the first arithmetic unit 110 through the interconnect circuit 150; the second arithmetic unit 140 can also transmit specific target data to the corresponding arithmetic circuit (e.g., each arithmetic circuit) in the first arithmetic unit 110 in a broadcast manner through the interconnect circuit 150.

[0092] For example, the second arithmetic unit 140 can transmit the grayscale values ​​of N×n pixels in the grayscale image to the first arithmetic unit 110 via the interconnect circuit 150. The interconnect circuit 150 can divide the grayscale values ​​of the N×n pixels into N groups, each group containing n pixel values. Then, the interconnect circuit 150 can send these N groups of grayscale values ​​to the N arithmetic circuits 110-1, 110-2, ..., 110-N respectively, while the n pixel values ​​in each group are sent to the n comparators in the corresponding arithmetic circuit (e.g., each arithmetic circuit). In this way, the interconnect circuit 150 completes the transmission and distribution of the target data.

[0093] During operation, the interconnect circuit 150 can also receive N sum data output from the N arithmetic circuits in parallel and transmit the N sum data to the second arithmetic unit. For example, after the N arithmetic circuits in the first arithmetic unit 110 have calculated the grayscale values ​​sent by the second arithmetic unit 140, they transmit the N sum data to the N accumulation circuits 400 or vector accumulation circuits 500 and / or 600 in the second arithmetic unit 140 via the interconnect circuit 150 to accumulate the sum data. The interconnect circuit 150 can also concatenate the N sum data into a sum data vector and transmit the sum data vector to the second arithmetic unit 140. In this case, the vector accumulation circuit 600 can omit the vector synthesis circuit 620.

[0094] It should be noted that interconnect circuit 150 is used for data transmission. Figure 1 The interconnect circuit 150 is depicted as a binary tree structure. Those skilled in the art will understand that the interconnect circuit 150 can be any circuit capable of performing the data transfer functions disclosed herein, and is not limited to any specific type. Figure 1 It takes the form of a binary tree.

[0095] The memory 170 can be connected to the first arithmetic unit 110 and the second arithmetic unit 140. During runtime, the memory 170 can store target data and send it to the N arithmetic circuits 110-1, 110-2, ..., 110-N of the first arithmetic unit 110, where the target data includes the n input data. Furthermore, the memory 170 can also store target data during runtime and transmit it to the second arithmetic unit 140 or the first arithmetic unit 110. The second arithmetic unit 140 can also transmit calculation results, such as accumulated data or accumulated vectors, to the memory 170 during runtime.

[0096] Memory 170 can be any form of storage medium. For example, memory 170 may include registers, mass storage, removable storage, volatile read-write memory, read-only memory (ROM), or similar content, or any combination thereof. Exemplary mass storage may include non-transitory storage media such as disks, optical discs, and solid-state drives. Exemplary removable storage may include flash drives, floppy disks, optical discs, memory cards, zip disks, magnetic tapes, etc. Typical volatile read-write memory may include random access memory (RAM). Exemplary RAM may include dynamic RAM (DRAM), double-rate synchronous dynamic RAM (DDR SDRAM), static RAM (SRAM), thyristor RAM (T-RAM), and zero-capacitance RAM (Z-RAM), etc. Exemplary ROM may include mask ROM (MROM), programmable ROM (PROM), programmable erasable ROM (PEROM), electrically erasable programmable ROM (EEPROM), and digital multifunction disk ROM, etc.

[0097] The controller 160 can be any type of control circuit that meets the requirements. The controller 160 can be connected to the first arithmetic unit 110, the second arithmetic unit 140, and the controller 160. When the controller 160 is running, it can receive instructions output by the second arithmetic unit 140, decode the instructions, and issue control signals to perform the various operations to complete each instruction.

[0098] For example, the second arithmetic unit 140 can send a control signal to the memory 170 via the controller 160, instructing the memory 170 to send target data and reference data to the second arithmetic unit 140 and / or the first arithmetic unit 110. Depending on different needs, the second arithmetic unit 140 can instruct the memory 170 to send different combinations of target data and reference data to the second arithmetic unit or the first arithmetic unit 110. For example, the N reference data values ​​can be the same, while the input target data (i.e., input data) can be different. In this way, the second arithmetic unit 140 can statistically analyze the values ​​of the same reference data among the target data with different values. The N reference data can be different, while the input target data (i.e., input data) values ​​can be the same, allowing the second arithmetic unit 140 to perform statistical analysis on the reference data. The N reference data and the input target data can both be different, allowing the second arithmetic unit 140 to perform statistical analysis on different target data (i.e., input data) based on different reference values.

[0099] Furthermore, the second arithmetic unit 140 can also send control signals to the first arithmetic unit 110 via the controller 160, instructing the first arithmetic unit 110 to send the sum data to the memory 170 or to the second arithmetic unit 140 via the interconnect circuit 150. The controller 160 can also act as the active sender of control signals, sending signals to the second arithmetic unit 140, the first arithmetic unit 110, and the memory 170, instructing the second arithmetic unit 110 or the memory 170 to send the target data and reference data to the first arithmetic unit 110, and / or instructing the first arithmetic unit 110 to send the sum data to the second arithmetic unit 140, and / or instructing the second arithmetic unit 140 to store the accumulated data in the memory 170.

[0100] The numerical statistics system 100 also includes a direct memory access unit 180. In practical applications, grayscale images often have a large number of pixels; for example, a 640*480 image has more than 300,000 pixels. During the grayscale value statistics process, the grayscale image needs to be read frequently and extensively. Direct memory access allows the memory 170 to quickly read and transfer data, improving efficiency.

[0101] Furthermore, although the systems and methods disclosed herein primarily describe the design of image grayscale value statistical methods, it should be understood that these are merely exemplary embodiments. The systems or methods disclosed herein can be applied to any other type of data statistics. For example, the devices or methods disclosed herein can be used for statistical text analysis.

[0102] Figure 7 This is a structural diagram illustrating a combined processing apparatus 700 according to an embodiment of this disclosure. Figure 7 As shown, the combined processing device 700 includes a computing processing device 702, an interface device 704, other processing devices 706, and a storage device 708. Depending on the application scenario, the computing processing device may include one or more computing devices 710, which may be the first processor 110 and / or the second processor 140 as disclosed herein. Of course, the computing devices 710, which may be the first processor 110 and / or the second processor 140 as disclosed herein, may also be included in the other processing devices 706. Further, the numerical statistics system 100 may be wholly or partially included in the computing device 710, or wholly or partially included in the other processing devices 706.

[0103] In different embodiments, the computing processing apparatus disclosed herein can be configured to perform user-specified operations. In exemplary applications, the computing processing apparatus can be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within the computing processing apparatus can be implemented as an artificial intelligence processor core or a portion of the hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or portions of the hardware structure of artificial intelligence processor cores, the computing processing apparatus disclosed herein can be considered to have a single-core structure or a homogeneous multi-core structure.

[0104] In exemplary operation, the computing processing device disclosed herein can interact with other processing devices through an interface device to jointly complete user-specified operations. Depending on the implementation, the other processing devices disclosed herein may include one or more types of processors such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and an artificial intelligence processor, both general-purpose and / or special-purpose processors. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing processing device disclosed herein can be considered to have a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, they can be considered to form a heterogeneous multi-core structure.

[0105] In one or more embodiments, the other processing device may serve as an interface between the computing processing device disclosed herein (which may be specifically defined as a computing device related to artificial intelligence, such as neural network operations) and external data and control, performing basic controls including but not limited to data transfer, starting and / or stopping the computing device. In another embodiment, the other processing device may also cooperate with the computing processing device to jointly complete the computing task.

[0106] In one or more embodiments, the interface device can be used to transfer data and control commands between a computing processing device and other processing devices. For example, the computing processing device can obtain input data from other processing devices via the interface device and write it to on-chip storage (or memory) of the computing processing device. Further, the computing processing device can obtain control commands from other processing devices via the interface device and write them to on-chip control cache of the computing processing device. Alternatively or optionally, the interface device can also read data from the storage device of the computing processing device and transmit it to other processing devices.

[0107] Additionally or optionally, the combined processing apparatus disclosed herein may further include a storage device. As shown in the figures, the storage device is connected to both the computing processing device and the other processing device. In one or more embodiments, the storage device may be used to store data from the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage of the computing processing device or other processing device.

[0108] In some embodiments, this disclosure also discloses a chip (e.g. Figure 8 The chip shown is 802. In one implementation, the chip is a system-on-chip (SoC) and integrates one or more of the following: Figure 7 The combined processing device shown is described. The chip can be connected to an external interface device (such as...). Figure 8 The external interface device 806 shown is connected to other related components. These related components may be, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. In some application scenarios, the chip may integrate other processing units (e.g., video codecs) and / or interface modules (e.g., DRAM interfaces). In some embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip. In some embodiments, this disclosure also discloses a board that includes the aforementioned chip package structure. The following will be combined with… Figure 8 The board is described in detail.

[0109] Figure 8 This is a schematic diagram illustrating the structure of a board 800 according to an embodiment of this disclosure. For example... Figure 8As shown, the board includes a storage device 804 for storing data, which includes one or more storage units 810. The storage device can be connected and transmit data with the controller 808 and the chip 802 described above via, for example, a bus. Furthermore, the board also includes an external interface device 806, configured for data relay or switching between the chip (or a chip in a chip package) and an external device 812 (e.g., a server or computer). For example, data to be processed can be transmitted from the external device to the chip via the external interface device. Alternatively, the calculation results of the chip can be transmitted back to the external device via the external interface device. Depending on the application scenario, the external interface device can have different interface forms; for example, it can adopt a standard PCIe interface.

[0110] In one or more embodiments, the controller in the disclosed board can be configured to regulate the state of the chip. Therefore, in one application scenario, the controller may include a microcontroller (MCU) for regulating the operating state of the chip.

[0111] Based on the above combination Figure 7 and Figure 8 Based on the description, those skilled in the art will understand that this disclosure also discloses an electronic device or apparatus that may include one or more of the aforementioned boards, one or more of the aforementioned chips, and / or one or more of the aforementioned combined processing apparatus.

[0112] Figure 9 A numerical statistical method 900 according to some embodiments of this disclosure is illustrated. The numerical statistical method can be applied to a chip circuit. The chip circuit may be... Figure 1 The numerical statistics system circuit 100 shown is illustrated. For example, the chip circuit may include a first arithmetic unit 110 and a second arithmetic unit 140 in the numerical statistics system circuit 100. The first arithmetic unit 110 may include N arithmetic circuits, each of which may include an adder circuit and n comparators, where N is a positive integer and n is an integer greater than 1. The numerical statistics method 900 includes the following steps:

[0113] S910: Receive n input data and at least one reference data through the n comparators. Each input data corresponds to one of the at least one reference data. In some embodiments, the n input data and / or the at least one reference data can be received in parallel. Specific operational steps have been described in detail in the preceding sections of this disclosure and will not be repeated here.

[0114] S920: When each of the n input data satisfies a preset condition with its corresponding reference data, a first value is output through the n comparators; otherwise, a second value is output. The specific operation steps have been described in detail in the preceding sections of this disclosure and will not be repeated here.

[0115] S930: The sum of the n output data is obtained by adding the n output data through the addition circuit, and the sum data is output.

[0116] The second arithmetic unit receives N sum data output from the N arithmetic circuits. In some embodiments, the N sum data may be received and output as scalars; in other embodiments, the N sum data may be received and output as vectors. The specific operation steps have been described in detail in the preceding sections of this disclosure and will not be repeated here.

[0117] S940: The second arithmetic unit receives the N sum data and adds the sum data output by the N arithmetic circuits to the corresponding accumulated data. The specific operation steps have been described in detail in the preceding parts of this disclosure and will not be repeated here.

[0118] In some embodiments, adding the sum data output by the N arithmetic circuits to the corresponding accumulated data can be done in parallel by adding the sum data output by the N arithmetic circuits to the accumulated data. The specific operation steps have been described in detail in the preceding sections of this disclosure and will not be repeated here.

[0119] In some embodiments, the sum data and the accumulated data can be scalar accumulation, or the N sum data can be first combined into a sum vector, and then vector accumulation can be performed. The specific operation steps have been described in detail in the preceding sections of this disclosure and will not be repeated here.

[0120] In some embodiments, the numerical statistics method 900 may further include sending corresponding N reference data to the N arithmetic circuits via the second arithmetic unit, wherein the N reference data have the same value. Specific details have been described previously and will not be repeated here.

[0121] In some embodiments, the numerical statistics method 900 may further include sending N corresponding input data to the N arithmetic circuits via the second arithmetic unit, wherein the N input data values ​​are different. Specific details have been described previously and will not be repeated here.

[0122] In some embodiments, the numerical statistics method 900 may further include sending N corresponding reference data to the N arithmetic circuits via the second arithmetic unit, wherein the N reference data values ​​are different. Specific details have been described previously and will not be repeated here.

[0123] In some embodiments, the numerical statistics method 900 may further include sending N corresponding input data to the N arithmetic circuits via the second arithmetic unit, wherein the N input data values ​​are different. Specific details have been described previously and will not be repeated here.

[0124] In some embodiments, the numerical statistics method 900 may further include sending N corresponding input data to the N arithmetic circuits via the second arithmetic unit, wherein the N input data have the same value. Specific details have been described previously and will not be repeated here.

[0125] In some embodiments, the n input data include data for which histogram statistics need to be performed.

[0126] In some embodiments, the n input data include one or more of the pixel data, vector data, and matrix data of the target image.

[0127] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal applications. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0128] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this document, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure may have different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0129] In terms of specific implementation, based on the disclosure and teachings of this document, those skilled in the art will understand that several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document divides them based on logical functions, but in actual implementation, there may be other division methods. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0130] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0131] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSDD). Therefore, when the solution disclosed herein is embodied in the form of a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this disclosure. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0132] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0133] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

[0134] In summary, after reading this disclosure, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this disclosure is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are intended to be made by this disclosure and are within the spirit and scope of the exemplary embodiments disclosed herein.

[0135] It should be understood that in the foregoing description of the embodiments disclosed herein, various features are sometimes combined in a single embodiment, drawing, or description for the purpose of simplifying the disclosure and aiding in the understanding of a feature. Alternatively, various features may be distributed across multiple embodiments of the invention. However, this does not mean that the combination of these features is necessary, and those skilled in the art may extract some features as individual embodiments when reading this disclosure. That is, the embodiments in this disclosure can also be understood as an integration of multiple sub-embodiments. It is also valid when each sub-embodiment contains fewer than all the features of a single foregoing embodiment.

[0136] Each patent, patent application, publication of the patent application, and other materials, such as articles, books, specifications, publications, documents, articles, etc., cited herein may be incorporated by reference. All content used for all purposes, except for any related historical prosecution documents, that may be inconsistent with or conflict with this document, or any related historical prosecution documents that may have a limiting effect on the widest extent of the claims, is now or hereafter associated with this document. For example, in the event of any inconsistency or conflict between the description, definition, and / or use of terms associated with any included material and the terms, description, definition, and / or used in connection with this document, the terms used herein shall prevail.

[0137] Finally, it should be understood that the embodiments disclosed herein are illustrative of the principles of the embodiments disclosed herein. Other modified embodiments are also within the scope of this disclosure. Therefore, the embodiments in this disclosure are merely examples and not limitations. Those skilled in the art can implement the invention of this disclosure by adopting alternative configurations based on the embodiments in this disclosure. Therefore, the embodiments in this disclosure are not limited to those embodiments precisely described in the application.

Claims

1. A numerical statistical system, characterized in that, The first arithmetic unit includes at least N arithmetic circuits, where N is a positive integer, and each of the arithmetic circuits includes: There are n comparators that receive n input data during runtime, where n is an integer greater than 1. Each comparator, during runtime: The first arithmetic unit receives corresponding input data and at least one corresponding reference data, wherein the reference data received by each arithmetic circuit has a different value; wherein the first arithmetic unit is further configured to reuse the input data to perform statistics on the multiple reference data. When the corresponding input data and the corresponding reference data satisfy a preset condition, the comparator outputs a first value; otherwise, the output data is a second value. During the operation of the first arithmetic unit, the n comparators output their respective data to the addition circuit. The n comparators are connected in parallel to the addition circuit. The adder circuit, during operation, sums the n output data of the n comparators and outputs the sum data; The addition circuit includes multiple adders connected in a tree structure; The tree structure includes m leaf node adders and one root node adder, where m is a positive integer; The output of each of the n comparators is connected to one input of each of the m leaf node adders; and The root node adder outputs the sum data; It also includes a second arithmetic unit, connected to the first arithmetic unit, which, when running, performs the following: Receive the sum data output from the N arithmetic circuits respectively; and The sum data output by the N arithmetic circuits are added together with the corresponding accumulated data.

2. The numerical statistical system as described in claim 1, characterized in that, The n comparators receive the n input data and / or at least one reference data in parallel during operation.

3. The numerical statistical system as described in claim 1, characterized in that, The n comparators are connected to the adder circuit in parallel. The adding circuit includes at least n adders connected in series; and The output data of each of the n comparators is input to the input terminal of one of the n adders.

4. The numerical statistical system as described in claim 1, characterized in that, When the second arithmetic unit runs, it adds the sum data output by the N arithmetic circuits to the accumulated data in parallel.

5. The numerical statistical system as described in claim 1, characterized in that, The second arithmetic unit includes at least K accumulator circuits corresponding to the N arithmetic circuits, where K is a natural number, and each accumulator circuit includes at least: An adder includes: The first input terminal receives the sum data, and the second input terminal receives the accumulated data. At the output end, the updated accumulated data is output, wherein the updated accumulated data is the sum of the sum data and the accumulated data; A memory for storing the updated accumulated data.

6. The numerical statistical system as described in claim 1, characterized in that, The second arithmetic unit includes at least one vector accumulation circuit, the vector accumulation circuit comprising: There are N adders, corresponding to the N arithmetic circuits. Each adder includes: a first input terminal for receiving the sum data from the corresponding arithmetic circuit. The second input terminal receives the corresponding accumulated data, and At the output end, the updated accumulated data is output, wherein the updated accumulated data is the sum of the sum data and the corresponding accumulated data; The vector synthesis circuit receives the N updated accumulated data output by the N adders in parallel and synthesizes the N updated accumulated data into an accumulated vector. Memory, including: The input terminal receives the accumulated vector, and At the output end, the N updated accumulated data in the accumulated vector are respectively input into the second input end of the corresponding adder.

7. The numerical statistical system as described in claim 6, characterized in that, The vector accumulation circuit includes: A vector synthesis circuit receives N sum data output from the N arithmetic circuits and synthesizes the N sum data into a single sum vector; Adders include: The first input terminal receives the sum vector. The second input terminal receives the accumulation vector, which includes the corresponding accumulation data, and At the output end, the updated accumulated vector is output, which is the sum of the sum vector and the accumulated vector. Memory, including: The input terminal receives the accumulated vector, and The output terminal inputs the accumulated vector to the second input terminal of the adder.

8. The numerical statistical system as described in claim 1, characterized in that, Also includes: The memory, connected to the first arithmetic unit, stores target data during operation and sends the target data to the N arithmetic circuits, wherein the target data includes the n input data; and / or The memory is connected to the second arithmetic unit, and stores the target data and transmits the target data to the second arithmetic unit during runtime. The second arithmetic unit transmits the calculation result to the memory during operation.

9. The numerical statistical system as described in claim 1, characterized in that, It also includes interconnect circuitry, connected to the second and first arithmetic units, which, during operation: Receive target data from the second arithmetic unit and transmit the target data to the first arithmetic unit; The system receives N sum data output from the N arithmetic circuits in parallel and transmits the N sum data to the second arithmetic unit; and The N sum data are concatenated into a sum data vector, and the sum data vector is transmitted to the second arithmetic unit.

10. The numerical statistical system as described in claim 1, characterized in that, When the second arithmetic unit is running, it sends corresponding N reference data to each of the N arithmetic circuits, and the N reference data have the same value.

11. The numerical statistical system as described in claim 1, characterized in that, When the second arithmetic unit is running, it sends N corresponding reference data to each of the N arithmetic circuits, and the values ​​of the N reference data are different.

12. The numerical statistical system as described in claim 1, characterized in that, The n input data include the data for which histogram statistics need to be performed.

13. The numerical statistical system as described in claim 1, characterized in that, The n input data include one or more of the pixel data, vector data, and matrix data of the target image.

14. A numerical statistical method applied to a chip circuit, said chip circuit comprising N arithmetic circuits in a first arithmetic unit, each arithmetic circuit comprising an adder circuit and n comparators, where N is a positive integer and n is an integer greater than 1, characterized in that... The numerical statistical methods include: The first arithmetic unit receives n input data and at least one reference data through the n comparators, with each input data corresponding to one of the at least one reference data; when the first arithmetic unit is running, the n comparators output their respective output data to the addition circuit; the n comparators are connected to the addition circuit in parallel with each other; When each of the n input data satisfies a preset condition with its corresponding reference data, the first value is output through the n comparators; otherwise, the second value is output. The sum of n output data is obtained by adding the n output data through the addition circuit; and the sum is output; wherein the addition circuit includes multiple adders connected in a tree structure; the tree structure includes m leaf node adders and one root node adder, where m is a positive integer; the output of each of the n comparators is connected to one input of each of the m leaf node adders; and the output of the root node adder outputs the sum. The method further includes reusing the input data through the first arithmetic unit to perform statistical analysis on multiple parameter data; The chip circuit further includes a second arithmetic unit, and the numerical statistics method further includes, through the second arithmetic unit: Receive N sum data; and The sum data output by the N arithmetic circuits are added together with the corresponding accumulated data.

15. The numerical statistical method as described in claim 14, characterized in that, The receiving of n input data and at least one reference data includes: The n input data are received in parallel and / or the at least one reference data is received in parallel.

16. The numerical statistical method as described in claim 14, characterized in that, The process of adding the sum data output by the N arithmetic circuits to the corresponding accumulated data includes: The sum data output by the N arithmetic circuits are added to the accumulated data in parallel.

17. The numerical statistical method as described in claim 14, characterized in that, Also includes: Receive N sum data output from the N arithmetic circuits and combine the N sum data into a sum vector; The step of adding the sum data output by the N arithmetic circuits to the corresponding accumulated data includes: performing vector addition on the sum data output by the N arithmetic circuits to the corresponding accumulated data.

18. The numerical statistical method as described in claim 14, characterized in that, Also includes: The second arithmetic unit sends corresponding N reference data to each of the N arithmetic circuits, and the N reference data have the same value.

19. The numerical statistical method as described in claim 14, characterized in that, It also includes sending corresponding N reference data to the N arithmetic circuits through the second arithmetic unit, wherein the values ​​of the N reference data are different.

20. The numerical statistical method as described in claim 14, characterized in that, The n input data include the data for which histogram statistics need to be performed.

21. The numerical statistical method as described in claim 14, characterized in that, The n input data include one or more of the pixel data, vector data, and matrix data of the target image.

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