Layout method and device of sequential logic device, electronic device and storage medium

Abstract

A layout method and device for sequential logic devices, an electronic device and a storage medium, the layout method comprising: determining the sequential logic device configuration requirements of each layout module according to the physical size of the layout module in the integrated circuit, the sequential logic device configuration requirements including the configuration requirements of the sequential logic device in the layout module for realizing signal transmission through the layout module; determining at least one multiplexing module group in the layout module, each multiplexing module group includes multiple layout modules, and the initial physical structures of the layout modules in the same multiplexing module group are the same; and planning the sequential logic device configuration on each routing path in the routing path design based on the routing path design in the integrated circuit and the sequential logic device configuration requirements of the layout module in the multiplexing module group, so that the configuration methods of the sequential logic devices in the layout modules in the same multiplexing module group are the same. The method is helpful to optimize the physical implementation process of the integrated circuit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a sequential logic device layout method, a sequential logic device layout apparatus, an electronic device, and a storage medium. Background Art

[0002] At present, with the continuous development and progress of chip process technology, high speed, high integration, low power consumption and low cost have become the main development direction of the integrated circuit industry, and the market performance requirements for chip products have also increased accordingly. Therefore, the design scale and complexity of chips have also increased greatly. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a layout method for a sequential logic device, the layout method comprising: determining sequential logic device configuration requirements of each layout module according to physical sizes of multiple layout modules in an integrated circuit, the sequential logic device configuration requirements including configuration requirements of sequential logic devices in the layout module for implementing signal transmission through the layout module; determining at least one multiplexing module group among the multiple layout modules, each multiplexing module group including multiple layout modules, and the initial physical structures of the layout modules in the same multiplexing module group are the same; and planning sequential logic device configurations on each routing path in the routing path design based on a routing path design in the integrated circuit and the sequential logic device configuration requirements of the layout modules in the at least one multiplexing module group, so that the configuration methods of sequential logic devices in the layout modules in the same multiplexing module group are the same.

[0004] For example, in a layout method of a sequential logic device provided in an embodiment of the present disclosure, the sequential logic device configuration requirements include configuration requirements of sequential logic devices in the layout module for respectively implementing signal transmission through the layout module in different directions.

[0005] For example, in a layout method of a sequential logic device provided in an embodiment of the present disclosure, the different directions include at least one of two edge extension directions of the layout module that intersect each other, or at least one diagonal extension direction of the layout module.

[0006] For example, in a layout method for a sequential logic device provided in an embodiment of the present disclosure, the sequential logic device configuration requirements of the layout modules in the same multiplexing module group are the same.

[0007] For example, in a layout method of a sequential logic device provided in an embodiment of the present disclosure, planning the configuration of sequential logic devices on each routing path in the routing path design includes: determining performance parameters of at least one sequential logic device configured on the routing path, and determining a setting position of the at least one sequential logic device on the routing path based on the performance parameters of the at least one sequential logic device.

[0008] For example, the layout method of the sequential logic device provided by an embodiment of the present disclosure also includes: according to the planned configuration of the sequential logic devices on each routing path, corresponding sequential logic devices are respectively set in the multiple layout modules, and the planned physical structure after the multiple layout modules set the sequential logic devices is obtained, and the planned physical structure of the layout modules in each of the multiplexing module groups is the same.

[0009] For example, a layout method for a sequential logic device provided in an embodiment of the present disclosure further includes: compressing two layout modules that belong to the same multiplexing module group and are adjacent to each other into one multiplexing layout module, wherein the multiplexing layout module has the same physical structure as the layout modules in the same multiplexing module group.

[0010] For example, the layout method of a sequential logic device provided by an embodiment of the present disclosure further includes: determining a routing path design in the integrated circuit according to a signal transmission requirement between the multiple layout modules.

[0011] For example, a layout method for a sequential logic device provided by an embodiment of the present disclosure also includes: determining a planned number of sequential logic devices on each routing path in the routing path design, and adjusting the planned number of sequential logic devices on each routing path based on the design performance constraints of the integrated circuit to obtain a constrained planned number of sequential logic devices on each routing path.

[0012] For example, in a layout method for a sequential logic device provided in an embodiment of the present disclosure, the planned number of sequential logic devices on each routing path is adjusted based on the design performance constraint of the integrated circuit, including: in response to the planned number of sequential logic devices on the routing path not satisfying the design performance constraint, reducing the planned number of sequential logic devices on the routing path.

[0013] For example, in a layout method for a sequential logic device provided in an embodiment of the present disclosure, reducing the planned number of sequential logic devices on the routing path includes: reducing the number of sequential logic devices in a layout module that does not belong to any multiplexing module group on the routing path.

[0014] For example, the layout method of a sequential logic device provided by an embodiment of the present disclosure also includes: according to the constraint planning quantity of the sequential logic devices on each routing path, respectively setting corresponding sequential logic devices in the multiple layout modules, and obtaining the constraint planning physical structure of the multiple layout modules.

[0015] For example, the layout method of a sequential logic device provided by an embodiment of the present disclosure further includes: analyzing the signal transmission effect between the multiple layout modules using the constraint planning physical structure, and obtaining an analysis result to determine whether to make a change request for the design performance constraint condition.

[0016] For example, in a layout method for a sequential logic device provided in an embodiment of the present disclosure, the signal transmission effect between the multiple layout modules using the constraint planning physical structure is analyzed to obtain an analysis result for determining whether a change request is made for the design performance constraint condition, including: judging whether the signal transmission effect between the multiple layout modules satisfies a static timing constraint; if so, obtaining an analysis result that no change request is made for the design performance constraint condition; if not, obtaining an analysis result that a change request is made for the design performance constraint condition.

[0017] For example, in a layout method for a sequential logic device provided in an embodiment of the present disclosure, in response to the analysis result being a request for a change to the design performance constraint, the layout method further includes: making a request for a change to the design performance constraint to change the design performance constraint; and in response to the change to the design performance constraint, re-determining the number of constraint plans for the sequential logic device on each routing path based on the changed design performance constraint.

[0018] For example, in the layout method of a sequential logic device provided in an embodiment of the present disclosure, in response to the analysis result that no change request is made for the design performance constraint, the layout method further includes: planning the physical structure according to the constraints of the multiple layout modules, and determining the structural layout of the integrated circuit.

[0019] For example, in a layout method of a sequential logic device provided in an embodiment of the present disclosure, the sequential logic device includes a register.

[0020] At least one embodiment of the present disclosure further provides a sequential logic device layout device, the sequential logic device layout device comprising: a sequential logic device configuration requirement acquisition unit, a multiplexing layout module determination unit and a sequential logic device configuration planning unit; the sequential logic device configuration requirement acquisition unit is configured to determine the sequential logic device configuration requirements of each layout module according to the physical sizes of multiple layout modules in the integrated circuit, the sequential logic device configuration requirements including the configuration requirements of the sequential logic device in the layout module for realizing signal transmission through the layout module; the multiplexing layout module determination unit is configured to determine at least one multiplexing module group among the multiple layout modules, each of the multiplexing module groups includes multiple layout modules, and the initial physical structures of the layout modules in the same multiplexing module group are the same; the sequential logic device configuration planning unit is configured to plan the sequential logic device configuration on each routing path in the routing path design based on the routing path design in the integrated circuit and the sequential logic device configuration requirements of the layout modules in the at least one multiplexing module group, so that the configuration methods of the sequential logic devices in the layout modules in the same multiplexing module group are the same.

[0021] At least one embodiment of the present disclosure further provides an electronic device, which includes a memory and a processor; the memory non-transiently stores computer executable instructions; the processor is configured to run the computer executable instructions, and when the computer executable instructions are executed by the processor, the layout method of the sequential logic device described in any embodiment of the present disclosure is implemented.

[0022] At least one embodiment of the present disclosure further provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the layout method of the sequential logic device according to any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1 A schematic diagram of the layout of a timing register in an integrated circuit;

[0025] Figure 2 A schematic flow chart of a layout method of a sequential logic device provided for some embodiments of the present disclosure;

[0026] Figure 3 A schematic flow chart of another layout method of a sequential logic device provided for some embodiments of the present disclosure;

[0027] Figure 4 A schematic diagram of an integrated circuit provided for some embodiments of the present disclosure;

[0028] Figure 5 A schematic diagram of a sequential logic device configuration requirement list of each layout module in an integrated circuit provided by some embodiments of the present disclosure;

[0029] Figure 6 A schematic diagram of a routing path design in an integrated circuit provided in some embodiments of the present disclosure;

[0030] Figure 7 A schematic diagram of a method for configuring sequential logic devices in each layout module in an integrated circuit provided by some embodiments of the present disclosure;

[0031] Figure 8 A schematic flow chart of another layout method of a sequential logic device provided for some embodiments of the present disclosure;

[0032] Fig. 9 A schematic flow chart of step S36 in a layout method for a sequential logic device provided in some embodiments of the present disclosure;

[0033] Fig.10 A schematic block diagram of a sequential logic device layout apparatus provided for some embodiments of the present disclosure;

[0034] Fig.11 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure;

[0035] Fig.12 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure; and

[0036] Fig.13 A schematic diagram of a storage medium provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0039] With the rapid development of the integrated circuit industry, the scale and complexity of circuit design are constantly increasing, and the difficulty of physical implementation of chips is also gradually increasing accordingly. In the physical implementation process of chips with large circuit scale or complex circuit design, in order to optimize the layout design in the chip, on the premise of meeting the signal transmission requirements in the chip, the same structural design may be adopted between modules located at different positions in the chip, that is, modules with the same structure can be repeatedly used at different positions in the chip, thereby improving the utilization rate of modules with the same structure in the chip; at the same time, it is also conducive to the subsequent compression of two modules with the same structure and adjacent positions in the chip into one module, thereby further simplifying the structural design of the chip.

[0040] In order to meet the signal transmission requirements between different modules in the chip, it is usually necessary to design multiple signal transmission paths in the chip, and configure corresponding timing registers on each signal transmission path according to the actual transmission distance of the signal to ensure stable transmission of the signal on the signal transmission path.

[0041] For example, Figure 1 Taking the signal transmission paths RT1 and RT2 in the integrated circuit shown as an example, the signal transmission path RT1 is module A1→module D→module B1→module C1→module F, and the signal transmission path RT2 is module A2→module E→module B2→module C2→module F. A plurality of timing registers TR1 are arranged on the signal transmission path RT1, and the plurality of timing registers TR1 are roughly evenly distributed along the signal transmission path RT1, so that the signal can be stably transmitted along the signal transmission path RT1; a plurality of timing registers TR2 are arranged on the signal transmission path RT2, and the plurality of timing registers TR2 are roughly evenly distributed along the signal transmission path RT2, so that the signal can be stably transmitted along the signal transmission path RT2.

[0042] For example, the timing registers TR1 and TR2 can be configured to have the same performance parameters, for example, the timing registers TR1 and TR2 can be configured to have the same clock constraints, so that the transmission time of the signal between two adjacent timing registers TR1 on the signal transmission path RT1 is equal to the transmission time of the signal between two adjacent timing registers TR2 on the signal transmission path RT2, that is, the timing registers TR1 and TR2 have the same unit driving distance for signal transmission, thereby simplifying the configuration method of the timing registers on each signal transmission path in the integrated circuit. For example, the timing registers TR1 and TR2 can adopt the same structural design, for example, the timing registers TR1 and TR2 can adopt the same register.

[0043] like Figure 1 As shown, according to the actual transmission distance of the signal on the signal transmission path RT1 and the unit driving distance of the timing register TR1, it is determined that two timing registers TR1 need to be set on the signal transmission path RT1, and the two timing registers TR1 are respectively located in module D and module C1; according to the actual transmission distance of the signal on the signal transmission path RT2 and the unit driving distance of the timing register TR2, it is determined that two timing registers TR2 need to be set on the signal transmission path RT2, and the two timing registers TR2 are respectively located in module B2 and module F.

[0044] However, after the timing registers TR1 and TR2 on the signal transmission paths RT1 and RT2 are laid out respectively in the above manner, the modules originally designed to adopt the same structure in the integrated circuit may not be implemented by the same structure.

[0045] For example, when modules B1 and B2 are designed as multiplexed modules with the same structure, since the timing register TR2 needs to be set in module B2, but the timing register does not need to be set in module B1, modules B1 and B2 cannot be implemented with the same structure, let alone compressed and designed as one module; when modules C1 and C2 are designed as multiplexed modules with the same structure, since the timing register TR1 needs to be set in module C1, but the timing register does not need to be set in module C2, modules C1 and C2 cannot be implemented with the same structure, let alone compressed and designed as one module. Therefore, in order to meet the design performance requirements of the chip, such as compression rate, it is necessary to manually re-adjust the setting position of the timing register in the integrated circuit, so that, for example, modules B1 and B2 and modules C1 and C2 can be respectively implemented as modules with the same structure, which results in a large amount of time being consumed in the design and development process of the chip to layout and design the timing registers in the chip, which prolongs the development cycle of the chip and reduces the physical implementation efficiency of the chip.

[0046] At least one embodiment of the present disclosure provides a layout method for a sequential logic device, the layout method comprising: determining sequential logic device configuration requirements of each layout module respectively according to physical sizes of multiple layout modules in an integrated circuit, the sequential logic device configuration requirements including configuration requirements of sequential logic devices in the layout module for realizing signal transmission through the layout module; determining at least one multiplexing module group among the multiple layout modules, each multiplexing module group including multiple layout modules, and the initial physical structures of the layout modules in the same multiplexing module group are the same; and planning sequential logic device configurations on each routing path in the routing path design based on a routing path design in the integrated circuit and the sequential logic device configuration requirements of the layout modules in at least one multiplexing module group, so that the configuration methods of sequential logic devices in the layout modules in the same multiplexing module group are the same.

[0047] The layout method of the sequential logic device provided by the above-mentioned embodiments of the present disclosure can be applied to the design and development of integrated circuits with different circuit structures or different layout designs, for example, chip design and chip development.

[0048] In the layout method of the sequential logic device provided in the above-mentioned embodiment of the present disclosure, when planning the configuration of the sequential logic device on each routing path, based on the routing path design in the integrated circuit, the sequential logic device configuration requirements of each layout module belonging to the same multiplexing module group are also taken into account, so that the configuration method of the sequential logic device in each layout module in the same multiplexing module group is the same. Therefore, after the preliminary planning of the sequential logic device configuration on each routing path in the integrated circuit, the layout modules using the same initial physical structure can be implemented through the same physical structure, which is conducive to achieving the ideal physical implementation effect of the layout of the sequential logic device in the integrated circuit, thereby improving the physical implementation efficiency of the integrated circuit and shortening the design and development cycle.

[0049] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

[0050] Figure 2 A schematic flowchart of a layout method for a sequential logic device provided for some embodiments of the present disclosure.

[0051] like Figure 2 As shown, the layout method of a sequential logic device provided by an embodiment of the present disclosure includes steps S11 to S13.

[0052] Step S11: determining the sequential logic device configuration requirements of each layout module according to the physical sizes of the multiple layout modules in the integrated circuit, wherein the sequential logic device configuration requirements include the configuration requirements of the sequential logic devices in the layout module for implementing signal transmission through the layout module.

[0053] Step S12: determining at least one multiplexing module group among the multiple layout modules, each multiplexing module group includes multiple layout modules, and the initial physical structures of the layout modules in the same multiplexing module group are the same.

[0054] Step S13: Based on the routing path design in the integrated circuit and the timing logic device configuration requirements of the layout module in at least one multiplexing module group, plan the timing logic device configuration on each routing path in the routing path design so that the configuration method of the timing logic device in the layout module in the same multiplexing module group is the same.

[0055] For example, for the above step S11, the sequential logic device configuration requirements of the layout module can be determined according to the physical size of the layout module, for example, according to the physical length of the layout module in different directions. For example, when the layout module is used to realize signal transmission through the layout module in a certain direction, the actual transmission distance of the signal in the layout module can be determined according to the physical size of the layout module in the direction, and then the sequential logic device configuration requirements for realizing signal transmission in the layout module along the direction can be determined according to the actual transmission distance.

[0056] For example, the sequential logic device configuration requirements include the performance parameters of the sequential logic device used and the corresponding configuration quantity. The performance parameters include, for example, the clock constraints of the sequential logic device, that is, the unit driving distance of the sequential logic device for signal transmission. Furthermore, after determining the performance parameters of the sequential logic device used, the approximate number range of the sequential logic devices that need to be set in the layout module can be calculated based on the transmission distance of the signal in the layout module, such as the minimum number of sequential logic devices that need to be set.

[0057] For example, for the above step S12, the reuse module group is a group of layout modules that can be implemented using the same initial physical structure among the multiple layout modules included in the integrated circuit, that is, each layout module in the reuse module group is designed to be implemented using the same physical structure. The layout modules included in the reuse module group can be respectively arranged at different positions in the integrated circuit or used to implement different functions, so as to improve the utilization rate of the layout modules using the same physical structure in the integrated circuit.

[0058] For example, for the above step S13, when planning the configuration of the sequential logic devices on each routing path, that is, when planning the performance parameters, setting number, setting position, etc. of the sequential logic devices on each routing path, while satisfying that the signal can be stably transmitted along each routing path in the routing path design, the sequential logic device configuration requirements of each layout module belonging to the same multiplexing module group are also taken into account at the same time, so as to satisfy that the configuration method of the sequential logic devices in each layout module belonging to the same multiplexing module group is the same. Therefore, after planning the configuration of the sequential logic devices on each routing path, the physical structure of each layout module belonging to the same multiplexing module group can always remain the same. Furthermore, after configuring the corresponding sequential logic devices in each layout module according to the plan, it is helpful to make each layout module belonging to the same multiplexing module group adopt the same physical structure.

[0059] In this way, after the preliminary planning and configuration of the sequential logic devices in the integrated circuit, the utilization rate of the layout modules using the same physical structure in the integrated circuit can be improved, which is conducive to meeting design performance requirements such as module reuse rate and module compression rate; at the same time, there is no need to spend a lot of time in the subsequent process to manually readjust the setting quantity and setting position of the sequential logic devices in the integrated circuit, which shortens the time required for the layout design of the sequential logic devices during the design and development of the integrated circuit, which is conducive to shortening the design and development cycle of the integrated circuit, reducing design costs and development costs, and improving physical implementation efficiency, thereby improving the competitiveness of electronic products using the integrated circuit.

[0060] In some embodiments of the present disclosure, for multiple layout modules belonging to the same multiplexing module group, the sequential logic device configuration requirements of the multiple layout modules are the same. Therefore, after planning the sequential logic device configuration on each routing path, it can help to keep the physical structure of each layout module belonging to the same multiplexing module group always the same, thereby improving the utilization rate of layout modules with the same physical structure in the integrated circuit; at the same time, it is also conducive to the subsequent compression design between two or more layout modules belonging to the same multiplexing module group and adjacent to each other, thereby improving the module compression rate in the integrated circuit, simplifying the layout structure of the integrated circuit, and reducing the area required to be occupied by the integrated circuit.

[0061] In some embodiments of the present disclosure, the configuration of sequential logic devices on each routing path in the planned routing path design in the above step S13 includes the following step S130.

[0062] Step S130: determining the performance parameters of the sequential logic device configured on the routing path, and determining the setting position of the sequential logic device on the routing path according to the performance parameters of the sequential logic device.

[0063] For example, for signal transmission on different routing paths, performance parameters such as clock constraints of a sequential logic device configured on the routing path may be determined according to the specific type of the signal transmitted on the routing path.

[0064] For example, for each routing path, the sequential logic devices set on the routing path can be configured to have the same performance parameters, such as being configured to have the same clock constraints, so that the transmission time of the signal between any two adjacent sequential logic devices on the routing path is the same, that is, each sequential logic device on the routing path has the same unit driving distance for signal transmission, which helps to determine the setting position of the sequential logic device on the routing path.

[0065] For example, the sequential logic devices on each routing path in the integrated circuit can be configured to have the same performance parameters, that is, each sequential logic device on each routing path has the same unit driving distance for signal transmission. This is conducive to optimizing the process of determining the setting position of the sequential logic devices on each routing path in the integrated circuit. For example, each sequential logic device on each routing path can adopt the same structural design, that is, each sequential logic device on each routing path is implemented in the same way.

[0066] For another example, for each routing path, multiple sequential logic devices arranged on the routing path may also be configured to have different performance parameters, such as different clock constraints, thereby helping to meet actual layout requirements for different signal transmissions. The embodiments of the present disclosure do not impose specific limitations on this.

[0067] For example, sequential logic devices may include devices such as registers, triggers, latches, etc. in digital circuit design that have edge-triggered functions. For example, sequential logic devices have storage and memory functions for input signals, and when receiving the valid edge or valid level of the clock signal, the sequential logic device can be triggered to store the input signal and change the state of the output signal.

[0068] For example, the sequential logic device can be applied to the pipeline operation mode of the integrated circuit, for example, implemented as a register applied to the pipeline operation mode, that is, a pipeline register.

[0069] For example, Figure 1 Taking the layout design of the timing register in the integrated circuit shown in FIG. 1 as an example, when the layout method of the embodiment of the present disclosure is used to layout the timing register in the integrated circuit, while satisfying the requirement that the signals on the routing paths RT1 and RT2 (for example, the signal transmission paths RT1 and RT2) can be stably transmitted along the routing paths RT1 and RT2 respectively, the timing logic device configuration requirements of the layout modules B1 and B2 belonging to the same multiplexing module group and the layout modules C1 and C2 belonging to the same multiplexing module group are also taken into account. Therefore, when designing the layout design of the timing register in the integrated circuit, the layout design of the timing register in the integrated circuit is performed. Figure 1 After the timing registers in the integrated circuit shown are preliminarily planned, the number of timing registers set in the layout modules B1 and B2 can be the same, and the number of timing registers set in the layout modules C1 and C2 can be the same. Furthermore, after the corresponding timing registers are configured in the integrated circuit according to the plan, it can help to implement the layout modules B1 and B2 with the same physical structure, and the layout modules C1 and C2 can be implemented with the same physical structure, which is conducive to meeting the design performance requirements of the integrated circuit, such as module reuse rate, module compression rate, etc.

[0070] For example, when the above layout method of the embodiment of the present disclosure is used to Figure 1 When the timing registers in the integrated circuit shown are laid out and designed, the timing logic device configuration requirements of the layout modules B1 and B2 belonging to the same multiplexing module group and the layout modules C1 and C2 belonging to the same multiplexing module group are taken into consideration. Therefore, when the timing registers in the integrated circuit are laid out and planned, the timing register TR1 on the routing path RT1 can be planned and set in the layout module D and the layout module F, and the timing register TR2 on the routing path RT2 can be planned and set in the layout module E and the layout module F; or, the timing register TR1 on the routing path RT1 can be planned and set in the layout module B1 and the layout module C1, and the timing register TR2 on the routing path RT2 can be planned and set in the layout module B2 and the layout module C2; ​​or, the timing register TR1 on the routing path RT1 can be planned and set in the layout module B1 and the layout module F, and the timing register TR2 on the routing path RT2 can be planned and set in the layout module B2 and the layout module F.

[0071] Figure 3 A schematic flow chart of another layout method of a sequential logic device provided in some embodiments of the present disclosure. It should be noted that, except for step S20 and steps S24 to S25, Figure 3 The other steps S21 to S23 in the layout method of the sequential logic device shown in FIG. Figure 2 Steps S11 to S13 in the layout method of the sequential logic device shown in are substantially the same or similar, and the repeated parts are not repeated herein.

[0072] For example, Figure 3 As shown, the layout method of the sequential logic device also includes the following step S20.

[0073] Step S20: Determine the routing path design in the integrated circuit according to the signal transmission requirements between the multiple layout modules.

[0074] For example, for the above step S20, each routing path in the integrated circuit can be determined according to the signal logic between each layout module in the integrated circuit, such as the signal connection relationship or logical relationship between each layout module, so as to obtain the routing path design in the integrated circuit.

[0075] For example, the above-mentioned step S20 can be executed before step S21 and step S22, or after step S21 and step S22, or between step S21 and step S22, or synchronously with one or more of step S21 and step S22. The embodiment of the present disclosure does not impose any specific restrictions on the execution order of step S20, as long as step S20 is executed before step S23.

[0076] In some embodiments of the present disclosure, Figure 3 As shown, the layout method of the sequential logic device also includes the following step S24.

[0077] Step S24: according to the planned sequential logic device configurations on each routing path, corresponding sequential logic devices are respectively set in multiple layout modules, and the planned physical structures after the sequential logic devices are set in the multiple layout modules are obtained, and the planned physical structures of the layout modules in each multiplexing module group are the same.

[0078] For example, for the above step S24, after the sequential logic device configuration on each routing path is planned, the sequential logic devices on each routing path can be respectively set in the corresponding layout modules according to the plan. For example, for each layout module belonging to the same multiplexing module group, the number, performance parameters, and setting positions of the sequential logic devices set in each layout module are the same, so that each layout module belonging to the same multiplexing module group can have the same planned physical structure.

[0079] As a result, the utilization rate of layout modules using the same physical structure in the integrated circuit can be improved, which is beneficial to optimizing the layout structure of the integrated circuit; and it is also beneficial to the subsequent compression design between two or more layout modules that belong to the same multiplexing module group and are adjacent to each other, thereby improving the module compression rate in the integrated circuit, simplifying the layout structure of the integrated circuit, and reducing the area required to be occupied by the integrated circuit.

[0080] In some embodiments of the present disclosure, Figure 3 As shown, the layout method of the sequential logic device also includes the following step S25.

[0081] Step S25: compressing two layout modules that belong to the same multiplexing module group and are adjacent to each other into one multiplexing layout module, where the multiplexing layout module has the same physical structure as the layout modules in the same multiplexing module group.

[0082] For example, for the above step S25, compression design can be performed between two or more layout modules that use the same physical structure and are adjacent to each other in the integrated circuit, so as to compress the two or more layout modules into one multiplexed layout module. In this way, the layout structure of the integrated circuit can be simplified, the area required to be occupied by the integrated circuit can be reduced, and it is helpful to meet the design performance requirements of the integrated circuit, such as module compression rate.

[0083] In some embodiments of the present disclosure, the sequential logic device configuration requirements include configuration requirements of sequential logic devices in a layout module for realizing signal transmission through the layout module in different directions. For example, for realizing signal transmission through the layout module in different directions, the performance parameters, setting quantity, setting position, etc. of the sequential logic devices required to be configured in the layout module.

[0084] For example, the above-mentioned different directions may include one or more of two edge extension directions of the layout module that intersect each other, or may also include one or more diagonal extension directions of the layout module.

[0085] The following embodiments of the present disclosure are combined with Figure 4 The example of the integrated circuit shown is used to exemplarily illustrate the layout method of the sequential logic device provided by the embodiment of the present disclosure. It should be noted that the layout method of the sequential logic device provided by the embodiment of the present disclosure includes but is not limited to this.

[0086] Figure 4 A schematic diagram of an integrated circuit provided in some embodiments of the present disclosure. Figure 4 As shown, the integrated circuit includes a layout module 111, a layout module 112, a layout module 121, a layout module 122, and a layout module 130. For example, the layout module 111 and the layout module 112 belong to the same multiplexing module group, that is, the layout module 111 and the layout module 112 use the same initial physical structure; the layout module 121 and the layout module 122 belong to another multiplexing module group, that is, the layout module 121 and the layout module 122 use the same initial physical structure; the initial physical structure of the layout module 130 is different from the layout modules 111 and the layout module 112, and is also different from the layout modules 121 and the layout module 122. In other words, the layout module 130 does not belong to the same multiplexing module group as any of the above-mentioned layout modules 111, 112, 121, and 122.

[0087] It should be noted that Figure 4 The number, position, layout mode, etc. of the layout modules included in the integrated circuit shown are only exemplary descriptions, and the embodiments of the present disclosure include but are not limited to them.

[0088] To clearly illustrate the technical solution of the present application, the embodiments of the present disclosure take the use of sequential logic devices with the same performance parameters on each routing path in an integrated circuit as an example to specifically illustrate the layout method of the sequential logic device provided by the embodiments of the present disclosure.

[0089] Figure 5 A schematic diagram of a sequential logic device configuration requirement list for each layout module in an integrated circuit provided in some embodiments of the present disclosure, for example Figure 5 Shows Figure 4 Configuration requirements of sequential logic devices within each layout module in the integrated circuit shown. Figure 6 A schematic diagram of a routing path design in an integrated circuit provided in some embodiments of the present disclosure, for example Figure 6 Shows Figure 4 An example of routing path design in an integrated circuit is shown. Figure 7 A schematic diagram of a method for configuring sequential logic devices in each layout module in an integrated circuit provided by some embodiments of the present disclosure, for example Figure 7 Shows Figure 4 An example of a method for configuring sequential logic devices within each layout module in an integrated circuit is shown.

[0090] For example, in Figure 4 In the case where the sequential logic devices configured in each layout module of the integrated circuit shown in the figure for realizing signal transmission through the layout module all have the same performance parameters, that is, when the same sequential logic devices are used, the number of sequential logic devices configured in different directions such as the X direction, the Y direction, and the diagonal direction (that is, non-X / Y direction) in the layout module 111, the layout module 112, the layout module 121, the layout module 122, and the layout module 130 is as follows: Figure 5 as shown in .

[0091] For example, for the layout module 111, one sequential logic device needs to be set in the layout module 111 to realize signal transmission through the layout module 111 and along the X direction; one sequential logic device needs to be set in the layout module 111 to realize signal transmission through the layout module 111 and along the Y direction; two sequential logic devices need to be set in the layout module 111 to realize signal transmission through the layout module 111 and along the diagonal direction (that is, non-X / Y direction).

[0092] For example, for the layout module 112, one sequential logic device needs to be set in the layout module 112 to realize signal transmission through the layout module 112 and along the X direction; one sequential logic device needs to be set in the layout module 112 to realize signal transmission through the layout module 112 and along the Y direction; two sequential logic devices need to be set in the layout module 112 to realize signal transmission through the layout module 112 and along the diagonal direction (that is, non-X / Y direction).

[0093] For example, for the layout module 121, two sequential logic devices need to be set in the layout module 121 to realize signal transmission through the layout module 121 and along the X direction, for example, the two sequential logic devices are arranged in sequence in the X direction; one sequential logic device needs to be set in the layout module 121 to realize signal transmission through the layout module 121 and along the Y direction; two sequential logic devices need to be set in the layout module 121 to realize signal transmission through the layout module 121 and along the diagonal direction (that is, non-X / Y direction).

[0094] For example, for the layout module 122, two sequential logic devices need to be set in the layout module 122 to realize signal transmission through the layout module 122 and along the X direction, for example, the two sequential logic devices are arranged in sequence in the X direction; one sequential logic device needs to be set in the layout module 122 to realize signal transmission through the layout module 122 and along the Y direction; two sequential logic devices need to be set in the layout module 122 to realize signal transmission through the layout module 122 and along the diagonal direction (that is, non-X / Y direction).

[0095] For example, for the layout module 130, it is necessary to set one sequential logic device in the layout module 130 to realize signal transmission through the layout module 130 and along the X direction; it is necessary to set two sequential logic devices in the layout module 130 to realize signal transmission through the layout module 130 and along the Y direction, for example, the two sequential logic devices are arranged sequentially in the Y direction; it is necessary to set two sequential logic devices in the layout module 130 to realize signal transmission through the layout module 130 and along the diagonal direction (that is, non-X / Y direction).

[0096] It should be noted that Figure 5The number of sequential logic devices that need to be configured in different directions such as the X direction, the Y direction, and the diagonal direction (i.e., non-X / Y direction) in each layout module 111, 112, 121, 122, and 130 shown in FIG is the minimum number required, that is, the number of sequential logic devices actually set in different directions such as the X direction, the Y direction, and the diagonal direction (i.e., non-X / Y direction) in each layout module 111, 112, 121, 122, and 130 can be set to be equal to Figure 5 The corresponding number shown in , or it can be set to be greater than Figure 5 The corresponding numbers shown in .

[0097] For example, Figure 6 As shown, Figure 4 The routing path design in the integrated circuit shown includes two routing paths RT11 and RT12 . The routing path RT11 is module 111 →module 121 →module 130 , and the routing path RT12 is module 112 →module 122 →module 130 .

[0098] Furthermore, if Figure 7 As shown, it can be combined Figure 5 The sequential logic device configuration requirements for each layout module in the integrated circuit shown and Figure 6 The routing paths RT11 and RT12 in the integrated circuit shown in the figure determine the number of sequential logic devices 201 required to be set on the routing path RT11 and the setting position of each sequential logic device 201, and determine the number of sequential logic devices 202 required to be set on the routing path RT12 and the setting position of each sequential logic device 202, thereby realizing the planning of the configuration of the sequential logic devices on the routing paths RT11 and the routing paths RT12 in the integrated circuit.

[0099] In some embodiments of the present disclosure, after preliminary planning of the configuration of sequential logic devices on each routing path in the integrated circuit, it is necessary to determine whether the layout design of the integrated circuit needs to be adjusted or modified based on the design performance constraints specified by the front-end design, for example, whether the configuration of the sequential logic devices on each routing path currently planned in the integrated circuit needs to be adjusted or modified so that the designed integrated circuit meets the design performance constraints specified by the front-end design.

[0100] After adjusting or modifying the layout design of the integrated circuit according to the design performance constraints specified by the front-end design, it is also necessary to perform a performance analysis on the integrated circuit after configuring the sequential logic device, such as analyzing the performance of the integrated circuit such as module reuse rate, module compression rate, static timing, etc., and based on the actual analysis results, determine whether it is necessary to make a change request for the design performance constraints specified by the front-end design to achieve the change of the design performance constraints.

[0101] Furthermore, after the design performance constraints specified by the front-end design are changed, it is re-determined whether feedback adjustment or modification is required for the layout design of the current integrated circuit based on the changed design performance constraints to achieve cyclic iteration.

[0102] Figure 8 A schematic flow chart of another method for placing a sequential logic device provided in some embodiments of the present disclosure. It should be noted that, except for steps S34 to S38, Figure 8 The other steps S31 to S33 in the layout method of the sequential logic device shown in FIG. Figure 2 Steps S11 to S13 in the layout method of the sequential logic device shown in are substantially the same or similar, and the repeated parts are not repeated herein.

[0103] For example, Figure 8 As shown, the layout method of the sequential logic device also includes the following step S34.

[0104] Step S34: Determine the planned number of sequential logic devices on each routing path in the routing path design, and adjust the planned number of sequential logic devices on each routing path based on the design performance constraints of the integrated circuit to obtain the constrained planned number of sequential logic devices on each routing path.

[0105] For example, for the above step S34, the design performance constraint conditions of the integrated circuit can be determined according to the full-chip insertion pipeline register design performance constraint file provided by the front-end design.

[0106] For example, the design performance constraints of the integrated circuit include constraints on the number of sequential logic devices set on each routing path in the integrated circuit, that is, the range of the number of sequential logic devices that can be set on each routing path in the integrated circuit, such as the maximum number of sequential logic devices that can be set on each routing path.

[0107] For example, in the above step S34, the total number of sequential logic devices currently planned on each routing path is first determined respectively as the planned number corresponding to each routing path; then, according to the number constraints on the sequential logic devices that can be set on each routing path in the design performance constraints, the planned number of sequential logic devices currently planned on each routing path is adjusted to obtain the constrained planned number corresponding to each routing path.

[0108] For example, when the planned number of sequential logic devices on the routing path satisfies the constraint on the number of sequential logic devices that can be set on the routing path in the design performance constraint conditions, there is no need to modify the planned number of sequential logic devices currently planned on the routing path, and the planned number is used as the constrained planned number of sequential logic devices on the routing path.

[0109] For example, when the planned number of sequential logic devices on the routing path does not satisfy the constraint on the number of sequential logic devices that can be set on the routing path in the design performance constraint conditions, it is necessary to modify the planned number of sequential logic devices currently planned on the routing path, that is, to modify the total number of sequential logic devices currently planned on the routing path, and use the modified number as the constrained planned number corresponding to the routing path.

[0110] For example, the above step S34, based on the design performance constraint of the integrated circuit, adjusts the planned number of sequential logic devices on each routing path, including the following step S340.

[0111] Step S340: In response to the planned number of sequential logic devices on the routing path not satisfying the design performance constraint, reducing the planned number of sequential logic devices on the routing path.

[0112] For example, for the above step S340, when the planned number of sequential logic devices on the routing path does not satisfy the constraint on the number of sequential logic devices that can be set on the routing path in the design performance constraint conditions, for example, the planned number of sequential logic devices currently planned on the routing path is greater than the maximum number of sequential logic devices that can be set on the routing path specified in the design performance constraint conditions, it is necessary to reduce the total number of sequential logic devices currently planned on the routing path so that the sequential logic device configuration on the routing path satisfies the design performance constraint conditions.

[0113] For example, reducing the planned number of sequential logic devices on the routing path in the above step S340 may include: reducing the number of sequential logic devices in the layout modules that do not belong to any multiplexing module group on the routing path.

[0114] For example, when the planned number of sequential logic devices on the routing path does not meet the design performance constraint conditions, the number of sequential logic devices in the layout module in the non-multiplexed module group (that is, not belonging to any multiplexed module group) can be forcibly adjusted so that the sequential logic device configuration on the routing path temporarily meets the design performance constraint conditions. For example, when the planned number of sequential logic devices currently planned on the routing path is greater than the maximum number of sequential logic devices that can be set on the routing path specified in the design performance constraint conditions, the number of sequential logic devices currently planned in the layout module that does not belong to any multiplexed module group on the routing path can be reduced so that the total number of sequential logic devices on the routing path is reduced. In this way, the adjusted constraint planning number corresponding to the routing path can meet the design performance constraint conditions, and the adverse effects on the design performance requirements of the integrated circuit, such as module reuse rate and module compression rate, can be avoided.

[0115] In some embodiments of the present disclosure, Figure 8 As shown, the layout method of the sequential logic device also includes the following step S35.

[0116] Step S35: according to the constraint planning quantity of the sequential logic devices on each routing path, corresponding sequential logic devices are respectively set in multiple layout modules, and the constraint planning physical structures of the multiple layout modules are obtained.

[0117] For example, for the above step S35, after determining the constraint planning number of the sequential logic devices on each routing path, the corresponding sequential logic devices are respectively set in the multiple layout modules according to the constraint planning number, and then the constraint planning physical structure of the multiple layout modules after the sequential logic devices are set is obtained, and in subsequent steps, based on the constraint planning physical structure of the multiple layout modules after the sequential logic devices are set, the current performance of the integrated circuit, such as module reuse rate, module compression rate, static timing, etc. is analyzed.

[0118] For example, in the layout method of the sequential logic device provided in the embodiment of the present disclosure, compared with before planning the configuration of the sequential logic device on each routing path, after the sequential logic device in the integrated circuit is preliminarily planned and configured, the layout module designed to be implemented with the same physical structure in the integrated circuit can always maintain the same physical structure, or most of the layout modules designed to be implemented with the same physical structure in the integrated circuit can always maintain the same physical structure, which can improve the utilization rate of the layout modules using the same physical structure in the integrated circuit, and is conducive to meeting the design performance requirements such as module reuse rate and module compression rate. Furthermore, when the current performance of the integrated circuit such as module reuse rate, module compression rate, static timing, etc. is subsequently analyzed, the loop iteration time required for feedback adjustment between the actual layout of the integrated circuit and the design performance constraints based on the analysis results can be shortened, thereby improving the iteration efficiency, shortening the design and development cycle of the integrated circuit, reducing the design cost and development cost, and improving the physical implementation efficiency of the integrated circuit, thereby improving the competitiveness of the electronic products using the integrated circuit.

[0119] In some embodiments of the present disclosure, Figure 8 As shown, the layout method of the sequential logic device also includes the following step S36.

[0120] Step S36: Analyze the signal transmission effects between multiple layout modules using the constraint programming physical structure to obtain an analysis result for determining whether to make a change request for the design performance constraint condition.

[0121] For example, for the above step S36, after analyzing the signal transmission effects between multiple layout modules using the constraint programming physical structure, the analysis results of the signal transmission effects such as static timing, signal transmission stability, and signal transmission efficiency in the current integrated circuit can be obtained. For example, the signal transmission effect of the integrated circuit can be compared with the actual requirements (such as the actual application requirements and performance requirements of the product). Therefore, according to the obtained analysis results, it can be judged whether the design performance constraint conditions provided by the front-end design are reasonable or whether they are more preferred or most preferred constraints, and then it can be determined whether it is necessary to make a change request for the design performance constraint conditions to achieve, for example, a change to the design performance constraint conditions.

[0122] Fig. 9 A schematic flowchart of step S36 in a layout method for a sequential logic device provided in some embodiments of the present disclosure.

[0123] For example, Fig. 9 As shown, the above step S36 includes the following steps S361 to S363.

[0124] Step S361: Determine whether the signal transmission effect between multiple layout modules meets the static timing constraints.

[0125] If satisfied (ie, "YES"), step S362 is executed: obtaining analysis results that do not require changes to the design performance constraints.

[0126] If not satisfied (ie, "NO"), step S363 is executed: obtaining analysis results of a request for change of the design performance constraint condition.

[0127] For example, for the above steps S361 to S363, after analyzing the signal transmission effects between multiple layout modules using constraint planning physical structures, the analysis results for the static timing in the current integrated circuit can be obtained, that is, whether the static timing in the current integrated circuit meets the static timing constraints specified in the design performance constraints. In the case where the static timing in the current integrated circuit meets the static timing constraints specified in the design performance constraints, the analysis result is that there is no need to make a change request for the design performance constraints, and then the structural layout of the integrated circuit can be determined based on the current constraint planning physical structure of the layout module. In the case where the static timing in the current integrated circuit does not meet the static timing constraints specified in the design performance constraints, the analysis result is that it is necessary to make a change request for the design performance constraints, and in the subsequent steps, based on whether the design performance constraints are changed, it is determined whether it is necessary to re-determine the constraint planning quantity of the sequential logic devices on each routing path, and then obtain a new constraint planning physical structure of multiple layout modules.

[0128] For example, in the above steps S361 to S363, it is judged whether the static timing in the current integrated circuit meets the static timing constraint. In some other examples of the present disclosure, the above step S36 may also include a process of judging whether, for example, signal transmission stability and signal transmission efficiency in the current integrated circuit meet the corresponding constraints or ranges specified in the design performance constraint conditions. The specific process can refer to the above steps S361 to S363, and the repeated parts will not be repeated here.

[0129] For example, in some embodiments of the present disclosure, the layout method of the sequential logic device also includes a step process for judging whether the performance of the current integrated circuit, such as module reuse rate, module compression rate, etc., meets the corresponding constraints or ranges specified in the design performance constraints. The specific steps and processes can refer to the corresponding content of the above-mentioned step S36, and the repeated parts will not be repeated here.

[0130] In some embodiments of the present disclosure, in response to the analysis result, a request for change is made to the design performance constraint condition, such as Figure 8As shown, the layout method of the sequential logic device also includes the following steps S37 and S38.

[0131] Step S37: In response to the analysis result that a change request is made for the design performance constraint condition, a change request is made for the design performance constraint condition to change the design performance constraint condition.

[0132] Step S38: In response to the change of the design performance constraint condition, re-determine the constraint planning quantity of the sequential logic devices on each routing path based on the changed design performance constraint condition.

[0133] For example, for the above steps S37 and S38, when it is determined based on the analysis results that a request for change of the design performance constraints is required, a request for change of the design performance constraints is made to the front-end design, and the front-end design determines whether to change the currently specified design performance constraints. After the front-end design determines that the currently specified design performance constraints need to be changed and completes the update of the design performance constraints, the constraint planning quantity of the sequential logic devices on each routing path is re-determined based on the changed design performance constraints to meet the changed design performance constraints, that is, return to re-execute the above step S34 and subsequent corresponding steps, for example, return to re-execute the above steps S34 to S36, thereby iterating in a loop to achieve feedback adjustment between the actual layout design of the back-end of the integrated circuit and the design performance constraints specified by the front-end design.

[0134] In some embodiments of the present disclosure, in response to the analysis result that no change request is made for the design performance constraint, or in response to the design performance constraint not being changed after a change request is made for the design performance constraint, the layout method of the sequential logic device also includes the following step S39.

[0135] Step S39: Plan the physical structure according to the constraints of the multiple layout modules and determine the structural layout of the integrated circuit.

[0136] For example, for the above step S39, the physical structure can be planned according to the current constraints of the layout module to determine the structural layout of the integrated circuit, thereby obtaining the structural layout of the integrated circuit that meets the design performance constraints provided by the front-end design.

[0137] The layout method of the sequential logic device provided by the embodiment of the present disclosure can improve the utilization rate of the layout modules using the same physical structure in the integrated circuit, which is conducive to meeting the design performance requirements such as module reuse rate and module compression rate, and then when the performance such as module reuse rate, module compression rate, static timing, etc. of the integrated circuit adjusted based on the design performance constraint conditions provided by the front-end design is subsequently analyzed, the loop iteration time required for feedback adjustment between the actual layout of the integrated circuit and the design performance constraint conditions based on the analysis results can be shortened. Thus, the iteration efficiency is improved, the design and development cycle of the integrated circuit is shortened, the design cost and development cost are reduced, and the physical realization efficiency of the integrated circuit is improved, thereby improving the competitiveness of the electronic products using the integrated circuit.

[0138] It should be noted that the embodiments of the present disclosure do not impose any specific restrictions on the specific number, structure, function, etc. of the layout modules included in the integrated circuit and the sequential logic devices provided in the layout modules.

[0139] It should be noted that the above-mentioned integrated circuits in the embodiments of the present disclosure and the structures and layout designs of the layout modules included therein are only exemplary and non-restrictive. According to actual needs, the above-mentioned integrated circuits and the layout modules therein may also include other components and structures, etc., and the embodiments of the present disclosure do not impose specific restrictions on this. The integrated circuits provided in the embodiments of the present disclosure may also include more components and structures, etc., which may be determined according to actual needs, and the embodiments of the present disclosure do not impose restrictions on this. It should be noted that in the above-mentioned embodiments of the present disclosure, the integrated circuits may include more or fewer circuits, units or modules, and the connection relationship between each circuit, unit or module is not limited and may be determined according to actual needs. The specific configuration of each circuit is not limited, and may be composed of analog devices according to circuit principles, or may be composed of digital chips, or may be composed in other applicable ways.

[0140] For example, the above-mentioned layout module can be hardware, software, firmware, and any feasible combination thereof, such as a dedicated or general circuit, chip, or device, or a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation form of the above-mentioned layout module and integrated circuit.

[0141] It should be noted that the layout module in the present disclosure may refer to a partial design or a partial module in a large circuit design, that is, the layout module in the present disclosure may be a complete digital circuit itself or a partial circuit in a complete circuit, and the present disclosure does not impose any restrictions on this.

[0142] It should be noted that, in the embodiments of the present disclosure, the process of the layout method of the sequential logic device provided by the above-mentioned embodiments of the present disclosure may include more or fewer operations, and these operations may be performed sequentially or in parallel. Although the process of the layout method of the sequential logic device described above includes multiple operations that appear in a specific order, it should be clearly understood that the order of the multiple operations is not limited. The layout method of the sequential logic device described above can be executed once or multiple times according to predetermined conditions.

[0143] At least one embodiment of the present disclosure further provides a sequential logic device layout device, which can enable layout modules using the same initial physical structure to be implemented through the same physical structure after preliminary planning of sequential logic device configurations on various routing paths in an integrated circuit, thereby facilitating the layout of sequential logic devices in the integrated circuit to achieve an ideal physical implementation effect, thereby improving the physical implementation efficiency of the integrated circuit and shortening the design and development cycle.

[0144] Fig.10 A schematic block diagram of a sequential logic device layout apparatus provided for some embodiments of the present disclosure.

[0145] For example, Fig.10 As shown, the sequential logic device layout apparatus 700 includes: a sequential logic device configuration requirement acquisition unit 701 , a multiplexing layout module determination unit 702 , and a sequential logic device configuration planning unit 703 .

[0146] The sequential logic device configuration requirement acquisition unit 701 is configured to determine the sequential logic device configuration requirements of each layout module according to the physical sizes of the multiple layout modules in the integrated circuit, and the sequential logic device configuration requirements include the configuration requirements of the sequential logic devices in the layout module for implementing signal transmission through the layout module. For example, the sequential logic device configuration requirement acquisition unit 701 may execute Figure 2 Step S11 in the layout method of the sequential logic device shown in .

[0147] The reused layout module determination unit 702 is configured to determine at least one reused module group among the multiple layout modules, each reused module group includes multiple layout modules, and the initial physical structures of the layout modules in the same reused module group are the same. For example, the reused layout module determination unit 702 may execute Figure 2 Step S12 in the layout method of the sequential logic device shown in .

[0148] The sequential logic device configuration planning unit 703 is configured to plan the sequential logic device configuration on each routing path in the routing path design based on the routing path design in the integrated circuit and the sequential logic device configuration requirements of the layout module in at least one multiplexing module group, so that the configuration method of the sequential logic devices in the layout modules in the same multiplexing module group is the same. For example, the sequential logic device configuration planning unit 703 can execute Figure 2 Step S13 in the layout method of the sequential logic device shown in .

[0149] For example, the sequential logic device configuration requirement acquisition unit 701, the reused layout module determination unit 702, and the sequential logic device configuration planning unit 703 include codes and programs stored in the memory; the processor can execute the codes and programs to implement some or all functions of the sequential logic device configuration requirement acquisition unit 701, the reused layout module determination unit 702, and the sequential logic device configuration planning unit 703 as described above. For example, the sequential logic device configuration requirement acquisition unit 701, the reused layout module determination unit 702, and the sequential logic device configuration planning unit 703 can be dedicated hardware devices, which are used to implement some or all functions of the sequential logic device configuration requirement acquisition unit 701, the reused layout module determination unit 702, and the sequential logic device configuration planning unit 703 as described above. For example, the sequential logic device configuration requirement acquisition unit 701, the reused layout module determination unit 702, and the sequential logic device configuration planning unit 703 can be a circuit board or a combination of multiple circuit boards, which are used to implement the functions as described above. In an embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processors; and (3) firmware stored in the memories that is executable by the processors.

[0150] It should be noted that the sequential logic device configuration requirement acquisition unit 701 is used to implement Figure 2 In step S11, the multiplexing layout module determination unit 702 is used to implement Figure 2 In step S12, the sequential logic device configuration planning unit 703 is used to implement Figure 2 The step S13 is shown. Therefore, the specific description of the sequential logic device configuration requirement acquisition unit 701 can refer to the embodiment of the sequential logic device layout method described above. Figure 2 For the description of step S11 shown in FIG. 1 , the specific description of the multiplexing layout module determination unit 702 can refer to the embodiment of the layout method of the sequential logic device described above. Figure 2 For the description of step S12 shown in FIG. 1 , the specific description of the sequential logic device configuration planning unit 703 can be referred to in the embodiment of the sequential logic device layout method described above. Figure 2The relevant description of step S13 is shown. In addition, the sequential logic device layout apparatus can achieve the technical effect similar to the aforementioned sequential logic device layout method, which will not be described in detail here.

[0151] In some embodiments of the present disclosure, the above-mentioned sequential logic device configuration requirements include configuration requirements of sequential logic devices in the layout module respectively used to implement signal transmission through the layout module in different directions.

[0152] For example, the different directions include at least one of two edge extension directions of the layout module that intersect each other, or at least one diagonal extension direction of the layout module.

[0153] In some embodiments of the present disclosure, the sequential logic device configuration requirements of the layout modules in the same multiplexing module group are the same.

[0154] For example, sequential logic devices may include devices such as registers, triggers, latches, etc. in digital circuit design that have edge-triggered functions. For example, sequential logic devices have storage and memory functions for input signals, and when receiving the valid edge or valid level of the clock signal, the sequential logic device can be triggered to store the input signal and change the state of the output signal.

[0155] For example, the sequential logic device configuration planning unit 703 is further configured to determine performance parameters of at least one sequential logic device configured on the routing path, and determine the setting position of at least one sequential logic device on the routing path according to the performance parameters of the at least one sequential logic device.

[0156] For example, the sequential logic device layout apparatus 700 further includes a sequential logic device configuration unit, which is configured to respectively set corresponding sequential logic devices in multiple layout modules according to the sequential logic device configurations on each planned routing path, and obtain a planned physical structure after the sequential logic devices are set in the multiple layout modules, and the planned physical structure of the layout modules in each multiplexing module group is the same.

[0157] For example, the sequential logic device layout apparatus 700 further includes a module compression unit configured to compress two layout modules that belong to the same multiplexing module group and are adjacent to each other into one multiplexing layout module, and the multiplexing layout module has the same physical structure as the layout modules in the same multiplexing module group.

[0158] For example, the sequential logic device layout apparatus 700 further includes a routing path design unit, which is configured to determine a routing path design in the integrated circuit according to a signal transmission requirement between a plurality of layout modules.

[0159] For example, the sequential logic device layout apparatus 700 further includes a sequential logic device quantity adjustment unit, which is configured to determine the planned quantity of sequential logic devices on each routing path in the routing path design, and adjust the planned quantity of sequential logic devices on each routing path based on the design performance constraints of the integrated circuit to obtain the constrained planned quantity of sequential logic devices on each routing path.

[0160] For example, the sequential logic device quantity adjustment unit is further configured to reduce the planned quantity of sequential logic devices on the routing path in response to the planned quantity of sequential logic devices on the routing path not satisfying the design performance constraint condition.

[0161] For example, the sequential logic device quantity adjustment unit is further configured to reduce the quantity of sequential logic devices in the layout modules that do not belong to any multiplexing module group on the routing path.

[0162] For example, the sequential logic device layout apparatus 700 further includes a sequential logic device planning adjustment unit, which is configured to respectively set corresponding sequential logic devices in multiple layout modules according to the constraint planning quantity of the sequential logic devices on each routing path, and obtain the constraint planning physical structure of the multiple layout modules.

[0163] For example, the sequential logic device layout apparatus 700 further includes an analysis unit configured to analyze the signal transmission effect between multiple layout modules using the constraint programming physical structure, and obtain an analysis result for determining whether to make a change request for the design performance constraint condition.

[0164] For example, the above-mentioned analysis unit is also configured to determine whether the signal transmission effect between multiple layout modules meets the static timing constraints; if so, an analysis result is obtained that does not request a change to the design performance constraint conditions; if not, an analysis result that requests a change to the design performance constraint conditions is obtained.

[0165] For example, the sequential logic device layout apparatus 700 further includes a change request processing unit, which is configured to: make a change request for a design performance constraint condition to change the design performance constraint condition; and in response to the change of the design performance constraint condition, re-determine the constraint planning quantity of the sequential logic device on each routing path based on the changed design performance constraint condition.

[0166] For example, the sequential logic device layout apparatus 700 further includes an integrated circuit structure layout determination unit, which is configured to plan the physical structure according to the constraints of the plurality of layout modules and determine the structure layout of the integrated circuit.

[0167] At least one embodiment of the present disclosure further provides an electronic device, which includes a processor, a memory, and one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for executing the layout method of the sequential logic device provided by any embodiment of the present disclosure.

[0168] Fig.11 A schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Fig.11 As shown, the electronic device 300 includes a processor 310 and a memory 320. The memory 320 is used to store computer executable instructions (e.g., one or more computer program modules) in a non-transient manner. The processor 310 is used to run the computer executable instructions, and when the computer executable instructions are run by the processor 310, one or more steps in the layout method of the sequential logic device described above can be executed. The memory 320 and the processor 310 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0169] For example, the processor 310 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86 or ARM architecture, etc. The processor 310 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 300 to perform desired functions.

[0170] For example, the memory 320 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 310 may run one or more computer program modules to implement various functions of the electronic device 300. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0171] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 300 can refer to the above description of the layout method of the sequential logic device and the layout apparatus of the sequential logic device, which will not be repeated here.

[0172] Fig.12 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 400 is, for example, suitable for implementing the layout method of the sequential logic device provided in the embodiments of the present disclosure. The electronic device 400 may be a terminal device, etc. It should be noted that, Fig.12 The electronic device 400 shown is merely an example and does not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0173] like Fig.12 As shown, the electronic device 400 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 410, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 420 or a program loaded from a storage device 480 to a random access memory (RAM) 430. In the RAM 430, various programs and data required for the operation of the electronic device 400 are also stored. The processing device 410, the ROM 420, and the RAM 430 are connected to each other via a bus 440. An input / output (I / O) interface 450 is also connected to the bus 440.

[0174] Typically, the following devices may be connected to the I / O interface 450: an input device 460 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 470 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 480 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 490. The communication device 490 may allow the electronic device 400 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Fig.12 The electronic device 400 is shown to have various devices, but it should be understood that it is not required to implement or possess all the devices shown, and the electronic device 400 may alternatively implement or possess more or fewer devices.

[0175] For example, according to an embodiment of the present disclosure, the layout method of the above-mentioned sequential logic device can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the layout method of the above-mentioned sequential logic device. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 490, or installed from the storage device 480, or installed from the ROM 420. When the computer program is executed by the processing device 410, the functions defined in the layout method of the sequential logic device provided in the embodiment of the present disclosure can be implemented.

[0176] Fig.13A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Fig.13 As shown, the storage medium 500 may be a non-transitory computer-readable storage medium, and one or more computer-readable instructions 501 may be non-transitory stored on the storage medium 500. For example, when the computer-readable instructions 501 are executed by a processor, one or more steps in the layout method of the sequential logic device described above may be executed.

[0177] For example, the storage medium 500 may be applied to the above-mentioned electronic device. For example, the storage medium 500 may include a memory in the electronic device.

[0178] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other applicable storage media.

[0179] For example, the description of the storage medium 500 can refer to the description of the memory in the embodiment of the electronic device, and the repeated parts will not be repeated. The specific functions and technical effects of the storage medium 500 can refer to the description of the layout method of the sequential logic device and the layout device of the sequential logic device above, and will not be repeated here.

[0180] There are a few points to note about this disclosure:

[0181] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0182] (2) For the sake of clarity, the thickness and size of layers or structures are exaggerated in the drawings used to describe the embodiments of the present invention. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intervening elements.

[0183] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0184] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A layout method for a sequential logic device, comprising: Determining, according to the physical sizes of the plurality of layout modules in the integrated circuit, respectively, the sequential logic device configuration requirements of each of the layout modules, wherein the sequential logic device configuration requirements include configuration requirements of the sequential logic devices in the layout modules for implementing signal transmission through the layout modules, and the configuration requirements include performance parameters and configuration quantities; Determine at least one multiplexing module group among the multiple layout modules, wherein each of the multiplexing module groups includes multiple layout modules, and the initial physical structures of the layout modules in the same multiplexing module group are the same; and Based on the routing path design in the integrated circuit and the sequential logic device configuration requirements of the layout module in the at least one multiplexing module group, the sequential logic device configuration on each routing path in the routing path design is planned so that the configuration method of the sequential logic device in the layout module in the same multiplexing module group is the same.

2. The layout method of a sequential logic device according to claim 1, wherein: The sequential logic device configuration requirements include configuration requirements of sequential logic devices in the layout module respectively used to implement signal transmission through the layout module in different directions.

3. The layout method of a sequential logic device according to claim 2, wherein: The different directions include at least one of two edge extension directions of the layout module that intersect each other, or at least one diagonal extension direction of the layout module.

4. The layout method of a sequential logic device according to claim 1 or 2, wherein: The sequential logic device configuration requirements of the layout modules in the same multiplexing module group are the same.

5. The layout method of a sequential logic device according to claim 1 or 2, wherein: Planning the configuration of sequential logic devices on each routing path in the routing path design includes: The performance parameters of at least one sequential logic device configured on the routing path are determined, and the setting position of the at least one sequential logic device on the routing path is determined according to the performance parameters of the at least one sequential logic device.

6. The layout method of a sequential logic device according to claim 1 or 2, further comprising: According to the planned configuration of sequential logic devices on each routing path, corresponding sequential logic devices are respectively set in the multiple layout modules, and the planned physical structure after the multiple layout modules set the sequential logic devices is obtained, wherein the planned physical structure of the layout modules in each of the multiplexing module groups is the same.

7. The layout method of a sequential logic device according to claim 6, further comprising: Two layout modules that belong to the same multiplexing module group and are adjacent to each other are compressed into one multiplexing layout module, wherein the multiplexing layout module has the same physical structure as the layout modules in the same multiplexing module group.

8. The layout method of a sequential logic device according to claim 1 or 2, further comprising: A routing path design in the integrated circuit is determined according to signal transmission requirements between the multiple layout modules.

9. The layout method of a sequential logic device according to claim 1 or 2, further comprising: Determine the planned number of sequential logic devices on each routing path in the routing path design, and adjust the planned number of sequential logic devices on each routing path based on the design performance constraints of the integrated circuit to obtain the constrained planned number of sequential logic devices on each routing path.

10. The layout method of a sequential logic device according to claim 9, wherein: Based on the design performance constraint of the integrated circuit, adjusting the planned number of sequential logic devices on each routing path includes: In response to the planned number of sequential logic devices on the routing path not satisfying the design performance constraint, the planned number of sequential logic devices on the routing path is reduced.

11. The layout method of a sequential logic device according to claim 10, wherein: Reducing the number of sequential logic devices planned on the routing path, including: The number of sequential logic devices in the layout modules that do not belong to any multiplexing module group on the routing path is reduced.

12. The layout method of a sequential logic device according to claim 9, further comprising: According to the constraint planning quantity of the sequential logic devices on each routing path, corresponding sequential logic devices are respectively arranged in the multiple layout modules, and the constraint planning physical structures of the multiple layout modules are obtained.

13. The layout method of a sequential logic device according to claim 12, further comprising: The signal transmission effect between the plurality of layout modules using the constraint planning physical structure is analyzed to obtain an analysis result for determining whether to make a change request for the design performance constraint condition.

14. The layout method of a sequential logic device according to claim 13, wherein: Analyzing the signal transmission effect between the plurality of layout modules using the constraint planning physical structure to obtain an analysis result for determining whether to make a change request for the design performance constraint condition, including: Determine whether the signal transmission effect between the multiple layout modules meets the static timing constraints; if so, obtain the analysis result of not making a change request for the design performance constraint condition; if not, obtain the analysis result of making a change request for the design performance constraint condition.

15. The layout method of a sequential logic device according to claim 13, wherein: In response to the analysis result being a request for a change to the design performance constraint, the layout method further includes: Proposing a change request for the design performance constraint condition to change the design performance constraint condition; and In response to the change of the design performance constraint condition, the constraint planning quantity of the sequential logic devices on each routing path is re-determined based on the changed design performance constraint condition.

16. The layout method of a sequential logic device according to claim 13, wherein: In response to the analysis result indicating that no change request is made for the design performance constraint condition, the layout method further includes: The physical structure is planned according to the constraints of the plurality of layout modules, and the structural layout of the integrated circuit is determined.

17. The layout method of a sequential logic device according to claim 1 or 2, wherein: The sequential logic device includes a register.

18. A sequential logic device layout device, comprising: a sequential logic device configuration requirement acquisition unit, configured to determine the sequential logic device configuration requirement of each layout module according to the physical sizes of the multiple layout modules in the integrated circuit, wherein the sequential logic device configuration requirement includes the configuration requirement of the sequential logic device in the layout module for implementing signal transmission through the layout module, and the configuration requirement includes performance parameters and configuration quantity; a multiplexing layout module determining unit, configured to determine at least one multiplexing module group among the plurality of layout modules, wherein each of the multiplexing module groups includes a plurality of layout modules, and the initial physical structures of the layout modules in the same multiplexing module group are the same; and The sequential logic device configuration planning unit is configured to plan the sequential logic device configuration on each routing path in the routing path design based on the routing path design in the integrated circuit and the sequential logic device configuration requirements of the layout module in the at least one multiplexing module group, so that the configuration method of the sequential logic device in the layout module in the same multiplexing module group is the same.

19. An electronic device comprising: A memory non-transitorily stores computer executable instructions; a processor configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the processor, the layout method of the sequential logic device according to any one of claims 1-17 is implemented.

20. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the layout method of a sequential logic device according to any one of claims 1 to 17 is implemented.

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