A cache memory applied to three-dimensional graphics depth testing

Abstract

The present application provides a cache memory applied to three-dimensional graphics depth testing, including: a Cache control unit, a secondary Cache RAM storage body, a primary high-speed Cache, a data positioning unit, and a dynamic allocation unit; wherein, the Cache control unit allocates storage addresses and controls Cache Lines; the secondary Cache RAM storage body stores secondary Cache Lines; the primary high-speed Cache caches primary Cache Lines; the data positioning unit determines the position of depth data in a Cache Line; the dynamic allocation unit dynamically allocates testing tasks. By combining two levels of caches with different rates, the response speed of the Cache is increased, the read / write latency is reduced, and the throughput is increased. It is ensured that when the Cache is hit, only one depth data read request is sent, and multiple associated depth data can be returned simultaneously within one clock cycle.

Description

Technical Field

[0001] This application relates to the field of 3D graphics processing, and particularly to a cache memory applied to 3D graphics depth testing. Background Art

[0002] In the per-fragment operation of the 3D (three-dimensional) graphics processing pipeline, depth buffer testing is generally required to confirm the mutual occlusion relationship between pixels. In this application process, the depth buffer testing algorithm needs to first read the depth values of 4 fragments in a 2×2 block from the depth buffer area in the external memory, then test them with the depth value of the fragment output by shading, and finally write the depth values that pass the test back to the external memory.

[0003] The fragments output by the upper shading unit are organized by the horizontal and vertical coordinates (x, y) of the fragments. In the depth buffer, the fragment data is stored and accessed in a certain organization method (linear storage or block storage).

[0004] During the processing of depth testing, every time the testing unit receives the depth value of a fragment, it needs to fetch the depth value at the corresponding (x, y) coordinates from the depth buffer for occlusion testing. If an ordinary Cache (cache memory) is used, an address needs to be sent to the Cache once for each fragment, and a request for reading and writing depth data is made.

[0005] In view of the actual processing process in which the upper shading unit delivers fragments to the depth testing unit, the fragments form a 2×2 block in the (x, y) coordinate space. In this case, if requests are still sent individually for each fragment, a maximum of 4 consecutive read and write requests need to be sent for one block. This does not utilize the format regularity of the data, resulting in an overly long interface waiting period for the upper-level unit and causing a bottleneck in Cache access efficiency. Summary of the Invention

[0006] To solve one of the above technical deficiencies, this application provides a cache memory applied to 3D graphics depth testing.

[0007] In the first aspect of this application, a cache memory applied to 3D graphics depth testing is provided, which is characterized in that its composition structure includes: a Cache control unit, a secondary Cache RAM storage body, a primary high-speed Cache, a data positioning unit, and a dynamic allocation unit;

[0008] Among them,

[0009] The Cache control unit is used to allocate storage addresses and control Cache Lines;

[0010] The secondary Cache RAM storage body is used to store secondary Cache Lines;

[0011] The primary high-speed Cache is used to cache the primary Cache Line.

[0012] The data positioning unit is used to determine the position of the depth data in the Cache Line.

[0013] The dynamic allocation unit is used to dynamically allocate test tasks for the lower-level test unit.

[0014] Optionally, the Cache control unit is used to allocate storage addresses for the depth values of the depth data in a linear or block format according to the coordinates (x, y) of the depth data input by the upper-level shading unit and the base address configured in the register.

[0015] Optionally, the requested data block in the Cache control unit includes 4 segments, and each segment corresponds to the depth data of the coordinates (x, y), (x + 1, y), (x, y + 1), and (x + 1, y + 1) respectively.

[0016] Optionally, the requested data block is represented by (x, y) as the starting address, and is used to allocate storage addresses for the data block for the depth values of the depth data in a linear or block format.

[0017] Optionally, in the Cache control unit, the storage address includes a base address and an offset relative to the base address;

[0018] The offset of any segment in the data block is determined by the following formula:

[0019] OFFSET = (X[max]~X[2], Y[1], Y[0], X[1], X[0])

[0020] Where max is the total number of bits of the x-axis coordinate value in the binary system for the any segment, X[max] is the value of the max-th bit of the x-axis coordinate value in the binary system for the any segment, X[2] is the value of the 2nd bit of the x-axis coordinate value in the binary system for the any segment, X[1] is the value of the 1st bit of the x-axis coordinate value in the binary system for the any segment, X[0] is the value of the 0th bit of the x-axis coordinate value in the binary system for the any segment, Y[1] is the value of the 1st bit of the y-axis coordinate value in the binary system for the any segment, and Y[0] is the value of the 0th bit of the y-axis coordinate value in the binary system for the any segment.

[0021] Optionally, the first segment of the data block corresponds to the depth data of the (x, y) coordinates;

[0022] The hit status of the first segment is used as the hit status of the data block;

[0023] The high bit in the address of the first segment is the identifier of the depth data of the (x, y) coordinates in the Cache RAM bank, and the low bit is the offset address of the depth data of the (x, y) coordinates in the Cache RAM bank.

[0024] Optionally, the Cache control unit sends a first-level hit index to the first-level high-speed cache according to the hit status of the generated address in the Cache Line; at the same time, it sends a read / write cache address to the external memory.

[0025] Optionally, the first-level Cache Line and the second-level Cache Line form two-level Cache Lines;

[0026] Among them, the first-level Cache Line is a high-speed Cache Line; the second-level Cache Line is a sub-speed Cache Line;

[0027] When the Cache control unit obtains a data request, it first controls the first-level Cache Line to perform a low-latency high-speed search. When the search fails, it generates a second-level index and controls the first-level Cache Line to perform a search based on the second-level index.

[0028] Optionally, the data positioning unit is used to determine the position of the requested data in the Cache Line according to the address of the data block, the sub-pixel direction, the address block mode, and the number of bits per pixel.

[0029] Optionally, the dynamic allocation unit is used to dynamically allocate test tasks to the lower-level test unit according to read and write requests, segment masks and data repeatability, and cache data positions.

[0030] The present application provides a cache memory applied to three-dimensional graphic depth testing, which comprises: a Cache control unit, a secondary Cache RAM storage body, a primary high-speed Cache, a data positioning unit, and a dynamic allocation unit; wherein, the Cache control unit is used for allocating storage addresses and controlling Cache Lines; the secondary Cache RAM storage body is used for storing secondary Cache Lines; the primary high-speed Cache is used for caching primary Cache Lines; the data positioning unit is used for determining the position of depth data in a Cache Line; and the dynamic allocation unit is used for dynamically allocating testing tasks to lower-level testing units. The present application combines two caches with different rates and two algorithm units to improve the response speed of the cache as much as possible, reduce read / write latency, and increase throughput. At the same time, it is ensured that when the cache hits, only one depth data read request is sent, and multiple associated depth data can be returned simultaneously within one clock cycle. Description of the Drawings

[0031] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0032] Figure 1 is a schematic diagram of the general structure of a cache memory applied to three-dimensional graphic depth testing provided by an embodiment of the present application;

[0033] Figure 2 is a schematic diagram of the detailed process structure of a cache memory applied to three-dimensional graphic depth testing provided by an embodiment of the present application;

[0034] Figure 3 is a schematic diagram of the data organization and coordinate operation of a Cache RAM storage body provided by an embodiment of the present application;

[0035] Figure 4 is a schematic diagram of the coordinates, data positioning, and dynamic allocation of a Cache RAM storage body provided by an embodiment of the present application. Detailed Embodiments

[0036] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the following further describes the exemplary embodiments of the present application in detail with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0037] In the process of implementing the present application, the inventors found that in the actual processing of the upper-level shading unit transmitting the fragments to the depth test unit, the fragments are organized into 2×2 blocks in the (x, y) coordinate space. In this case, if a request is still sent for each fragment separately, a block needs to send a maximum of 4 read and write requests in succession. This does not take advantage of the regularity of the data format, resulting in a long interface waiting period for the upper-level unit and a bottleneck in cache access efficiency.

[0038] In response to the above problems, a high-speed cache memory for three-dimensional graphics depth testing is provided in an embodiment of the present application, which comprises: a cache control unit, a secondary cache RAM storage body, a primary high-speed cache, a data location unit and a dynamic allocation unit; wherein the cache control unit is used to allocate storage addresses and control cache lines; the secondary cache RAM storage body is used to store the secondary cache lines; the primary high-speed cache is used to cache the primary cache lines; the data location unit is used to determine the position of the depth data in the cache line; the dynamic allocation unit is used to dynamically allocate test tasks to the lower-level test units. The present application improves the response speed of the cache as much as possible, reduces the read and write delays, and increases the throughput through the combination of two levels of caches with different rates and two algorithm units. At the same time, it is ensured that when the cache hits, only one depth data read request is sent, and multiple associated depth data can be returned simultaneously within one clock cycle.

[0039] See also Figure 1 The embodiment provides a high-speed cache memory for three-dimensional graphics depth testing, including: a cache (high-speed cache memory) control unit, a second-level cache RAM (Random Access Memory) storage body, a first-level high-speed cache, a data location unit and a dynamic allocation unit.

[0040] 1. Cache control unit

[0041] Cache control unit, used to allocate storage addresses and control cache lines.

[0042] Specifically,

[0043] The cache control unit is used to allocate storage addresses for the depth values of the depth data in a linear or block format according to the coordinates (x, y) of the depth data input by the upper-level shading unit and the base address configured by the register.

[0044] For example, a Cache control unit is used to allocate the storage address of a data block for the depth value of depth data in a linear or block format according to the coordinates (x, y) of the depth data input by the upper shading unit and the base address configured in the register.

[0045] The data block includes 4 segments, and each segment corresponds to the depth data of the coordinates (x, y), (x + 1, y), (x, y + 1), and (x + 1, y + 1) respectively.

[0046] Among them, the storage address includes the base address and the offset relative to the base address.

[0047] The offset of any segment in the data block is determined by the following formula:

[0048] OFFSET = (X[max] ~ X[2], Y[1], Y[0], X[1], X[0])

[0049] Among them, max is the total number of bits of the x-axis coordinate value in binary for any segment, X[max] is the value of the max-th bit of the x-axis coordinate value in binary for any segment, X[2] is the value of the 2nd bit of the x-axis coordinate value in binary for any segment, X[1] is the value of the 1st bit of the x-axis coordinate value in binary for any segment, X[0] is the value of the 0th bit of the x-axis coordinate value in binary for any segment, Y[1] is the value of the 1st bit of the y-axis coordinate value in binary for any segment, and Y[0] is the value of the 0th bit of the y-axis coordinate value in binary for any segment.

[0050] In addition, the first segment of the data block corresponds to the depth data of the (x, y) coordinates.

[0051] The address of the first segment is used as the address of the data block.

[0052] The hit status of the first segment is used as the hit status of the data block.

[0053] In the address of the first segment, the high bits are the identifier of the depth data of the (x, y) coordinates in the Cache RAM storage bank, and the low bits are the offset address of the depth data of the (x, y) coordinates in the Cache RAM storage bank.

[0054] That is to say, the requested data block includes 4 segments, and each segment corresponds to the depth data of the coordinates (x, y), (x + 1, y), (x, y + 1), and (x + 1, y + 1) respectively. Taking (x, y) as the first address represents the entire block, and is used to allocate the storage address of the data block for the depth value of the depth data in a linear or block format.

[0055] In addition, the Cache control unit is also used to send an internal index to the Cache RAM storage bank according to the hit status of the data block, and at the same time, send a read / write address to the external memory.

[0056] That is to say, the Cache control unit sends the first-level hit index to the first-level high-speed Cache according to the hit status of the generated address in the Cache Line; meanwhile, it sends the read / write cache address to the external memory.

[0057] In addition, before the Cache control unit sends the internal index to the Cache RAM bank, the Cache control unit also sends the internal index to the register high-speed Cache bank, and the register high-speed Cache bank fails to index the data.

[0058] That is to say, the Cache control unit first sends the internal index to the register high-speed Cache bank. If the register high-speed Cache bank fails to index the data, then the Cache control unit sends the internal index to the Cache RAM bank according to the hit status of the data block. Meanwhile, it sends the read / write address to the external memory.

[0059] 2. Secondary Cache RAM bank

[0060] The Cache RAM bank is used to store the secondary Cache Line.

[0061] The Cache RAM bank is composed of multiple Cache Lines. Data is stored in one Cache Line, and multiple data are stored in one Cache Line.

[0062] 3. First-level high-speed Cache

[0063] The register high-speed Cache is used to cache the first-level Cache Line.

[0064] Since the register high-speed Cache caches the deep data stored in the Cache RAM, the structure of the register high-speed Cache is the same as that of the Cache RAM bank. It is also composed of multiple Cache Lines. Data is stored in one Cache Line, and multiple data are stored in one Cache Line.

[0065] The Cache RAM bank and the register high-speed Cache can form a secondary data Cache. Through this secondary data Cache, it can be ensured that when the Cache hits, only one deep data read request is sent, and the deep data of 4 segments within the block can be returned simultaneously within one clock cycle.

[0066] Among them, the first-level Cache Line and the secondary Cache Line form two-level Cache Lines.

[0067] The primary cache line is the high-speed cache line, and the secondary cache line is the sub-speed cache line;

[0068] When the cache control unit receives a data request, it first controls the primary cache line to perform a low-latency high-speed search. When the search fails, it generates a secondary index and controls the primary cache line to perform a search based on the secondary index.

[0069] That is to say, the cache memory of this embodiment consists of two levels of cache lines, including a group of high-speed primary cache lines and a group of sub-speed secondary cache lines.

[0070] In the two-level structure, when a data request is received, a low-latency high-speed search is preferentially performed in the primary cache line. When the primary cache misses, a secondary index is generated and the request is passed to the secondary cache, and so on.

[0071] 4. Data Location Unit

[0072] The data location unit is used to determine the position of the depth data in the cache line.

[0073] For example, determine the cache data position in the cache RAM bank or register cache according to the read and write requests.

[0074] Specifically,

[0075] The data location unit is used to determine whether there is a target cache line in the register cache according to the read and write requests. If it exists, determine the cache data position from the target cache line. If it does not exist, determine the target cache line in the cache RAM bank and determine the cache data position from the target cache line.

[0076] For example, determine the position of the requested cache data in the cache line according to the address of the data block, the sub-pixel direction, the address block mode, and the number of bits per pixel.

[0077] 5. Dynamic Allocation Unit

[0078] The dynamic allocation unit is used to dynamically allocate test tasks for the lower-level test unit.

[0079] For example, allocate test units according to the read and write requests and the cache data position.

[0080] Specifically, the dynamic allocation unit is used to dynamically allocate test tasks to lower-level test units based on read and write requests, segment masks and data repeatability, and cache data locations.

[0081] The high-speed cache memory applied to the three-dimensional graphics depth test provided by this embodiment is a secondary data cache dedicated to the depth test, which can ensure that when the cache hits, only one depth data read request is sent, and the depth data of 4 fragments in the block can be returned simultaneously within one clock cycle. At the same time, the architecture of the first-level register high-speed cache + the second-level cache RAM storage body makes most of the read and write operations occur in the first-level register end, increasing the response speed of the cache, greatly eliminating the access waiting bottleneck of the depth cache cache, and reducing power consumption. At the same time, the dynamic allocation unit in the high-speed cache memory applied to the three-dimensional graphics depth test provided by this embodiment can dynamically allocate the read depth data to multiple processing units, minimize the idle cycle of parallel processing, and improve the processing effect.

[0082] The high-speed cache memory applied to the three-dimensional graphics depth test provided by this embodiment is described again below. Figure 2 The high-speed cache memory for three-dimensional graphics depth testing provided in this embodiment includes a cache control unit, a cache Ram storage body, a register high-speed cache, a data positioning unit and a dynamic allocation unit. The depth data input by the upper-level shading unit is organized in the (x, y) coordinate space. The address block operation unit in the cache control unit allocates storage addresses to the depth values of the fragments in a linear or block format according to their (x, y) coordinates and the base address configured by the register.

[0083] The following describes the address allocation in a 4×4 block format. Figure 3 As shown, 32 fragments are arranged in an (x, y) coordinate organization manner. According to the configured 4×4 block format, the fragments are stored in the cache line by block and assigned addresses.

[0084] The calculation formula of address offset is:

[0085] OFFSET=(X[max]~X[2], Y[1], Y[0], X[1], X[0])

[0086] Among them, max is the total number of bits of the x-axis coordinate value in binary in any fragment, X[max] is the value of the max-th bit of the x-axis coordinate value in binary in any fragment, X[2] is the value of the 2nd bit of the x-axis coordinate value in binary in any fragment, X[1] is the value of the 1st bit of the x-axis coordinate value in binary in any fragment, X[0] is the value of the 0th bit of the x-axis coordinate value in binary in any fragment, Y[1] is the value of the 1st bit of the y-axis coordinate value in binary in any fragment, and Y[0] is the value of the 0th bit of the y-axis coordinate value in binary in any fragment. That is, X[a] represents the a-th bit of the x-axis coordinate value in binary.

[0087] When the Cache control unit determines Cache hit, the data in the Cache is organized in the form of several Cache Lines. The data of the upper shading unit is grouped in sets of 4 fragments. The spatial arrangement relationship of the 4 fragments is a 2×2 block, namely (x, y), (x + 1, y), (x, y + 1), (x + 1, y + 1), where (x, y) is the first fragment of a data block, and with the coordinates of the first fragment as the identifier, the positions and addresses of all 4 fragments are automatically recognized. At the same time, the hit status of the first fragment address is used to represent the hit status of the entire data block. The high bits of the address are used as the identification tag of the Cache Line to determine the hit, and the low bits of the address are used for offset positioning within the Cache Line. The Cache control unit sends an internal index to the internal storage in the Cache according to the hit result, and sends a read / write address to the external storage at the same time.

[0088] In addition, the cache memory applied to the three-dimensional graphics depth test provided in this embodiment has a two-level Cache design. To reduce the number of accesses to the second-level Cache RAM storage and further reduce the access waiting time, this embodiment designs a first-level register high-speed Cache. The register high-speed Cache uses registers as the storage to further cache the large Cache Lines ( Figure 2 labeled as level 2 lines in Figure 2 in the Cache RAM storage) to form several high-speed Cache Lines ( labeled as level 1 lines in ). When the first-level register high-speed Cache hits, the data directly flows within the first-level high-speed storage, and the Cache Lines in the first-level register high-speed Cache are written and read; when the first level misses, an access is requested from the second level.

[0089] In addition, the cache memory provided in this embodiment for three-dimensional graphics depth testing can also perform cache level deletion. Since the cache control unit is independent of the first-level register high-speed cache and the second-level cache RAM memory bank, the first-level register high-speed cache can be directly bypassed between the L2 control and L2 storage, and the L2 index is directly provided to the L2 storage, simply implementing a custom cache level configuration.

[0090] In addition, when the cache memory provided in this embodiment for three-dimensional graphics depth testing performs data positioning and dynamic allocation, since a block only sends one request once, while the first-level register high-speed cache reads an entire cache line at a time. As Figure 4 shown, the data positioning unit restores the positions of the 4 depth data within the block in the first-level register high-speed cache or the second-level cache RAM memory bank, and reads and writes the corresponding data according to the positioning.

[0091] Among them, during data positioning, the inputs are the 2×2 block first pixel address, sub-pixel direction, address block mode, and bits per pixel. The outputs are the positions of the 4 segments in the cache line of the first-level register high-speed cache or the second-level cache RAM memory bank.

[0092] After the positioning is completed, the dynamic allocation unit dynamically allocates the valid data to a plurality of test units according to the segment mask and data repeatability, reducing the idle rate of the test units.

[0093] The cache memory provided in this embodiment for three-dimensional graphics depth testing has good performance. Using a two-level cache structure, it performs low-latency data access and write-back in a pipelined manner, improving efficiency while reducing power consumption; it is specifically optimized for three-dimensional graphics processing, reducing the number of accesses to the storage.

[0094] Moreover, the cache memory provided in this embodiment for three-dimensional graphics depth testing is convenient to use, with low coupling between each module. The first-level cache can be directly shielded or enabled by changing the wiring, and it is easy to customize deletion or addition, having good reusability and scalability.

[0095] This embodiment provides a cache memory applied to 3D graphics depth testing, which consists of: a Cache control unit, a secondary Cache RAM storage body, a primary high-speed Cache, a data positioning unit, and a dynamic allocation unit; among them, the Cache control unit is used to allocate storage addresses and control Cache Lines; the secondary Cache RAM storage body is used to store secondary Cache Lines; the primary high-speed Cache is used to cache primary Cache Lines; the data positioning unit is used to determine the position of depth data in Cache Lines; the dynamic allocation unit is used to dynamically allocate test tasks for lower-level test units. This application combines two caches with different rates and two algorithm units to improve the response speed of the cache as much as possible, reduce read and write latency, and increase throughput. At the same time, it is ensured that when the cache hits, only one depth data read request is sent, and multiple associated depth data can be returned simultaneously within one clock cycle.

[0096] Those skilled in the art should understand that although the preferred embodiments of this application have been described, once those skilled in the art learn the basic creative concepts, additional changes and modifications can be made to these embodiments. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0097] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.

Claims

1. A cache memory applied to depth testing of three-dimensional graphics, characterized in that, Its composition structure includes: a Cache control unit, a secondary Cache RAM storage body, a primary high-speed Cache, a data positioning unit, and a dynamic allocation unit; Among them, the Cache control unit is used to allocate storage addresses and control Cache Lines; the secondary Cache RAM storage body is used to store secondary Cache Lines; the primary high-speed Cache is used to cache primary Cache Lines; the data positioning unit is used to determine the position of depth data in a Cache Line; the dynamic allocation unit is used to dynamically allocate test tasks for lower-level test units; the Cache control unit is used to allocate storage addresses for the depth values of the depth data in a linear or block format according to the coordinates (x, y) of the depth data input by the upper-level shading unit and the base address configured in the register; The data block requested in the Cache control unit includes 4 segments, and each segment corresponds to the depth data of the coordinates (x, y), (x + 1, y), (x, y + 1), and (x + 1, y + 1) respectively.

2. The cache memory according to claim 1, wherein The requested data block is represented by (x, y) as the starting address, and is used to allocate the storage address of the data block for the depth values of the depth data in a linear or block format.

3. The cache memory according to claim 2, characterized in that, In the Cache control unit, the storage address includes a base address and an offset relative to the base address; The offset of any segment in the data block is determined by the following formula: OFFSET = (X[max]~X[2], Y[1], Y[0], X[1], X[0]) where max is the total number of bits of the x-axis coordinate value in binary in the any segment, X[max] is the value of the x-axis coordinate value in the any segment at the max-th bit in the binary, X[2] is the value of the x-axis coordinate value in the any segment at the 2nd bit in the binary, X[1] is the value of the x-axis coordinate value in the any segment at the 1st bit in the binary, X[0] is the value of the x-axis coordinate value in the any segment at the 0th bit in the binary, Y[1] is the value of the y-axis coordinate value in the any segment at the 1st bit in the binary, and Y[0] is the value of the y-axis coordinate value in the any segment at the 0th bit in the binary.

4. The cache memory according to claim 2, characterized in that, The first segment of the data block corresponds to the depth data of the (x, y) coordinates; The hit status of the first segment is used as the hit status of the data block; The high bits in the address of the first segment are the identifier of the depth data of the (x, y) coordinates in the Cache RAM storage body, and the low bits are the offset address of the depth data of the (x, y) coordinates in the Cache RAM storage body.

5. The cache memory according to claim 1, wherein The Cache control unit sends a primary hit index to the primary high-speed Cache according to the hit status of the generated address in the Cache Line; at the same time, it sends a read / write cache address to the external memory.

6. The cache memory according to claim 1, wherein The primary Cache Line and the secondary Cache Line form two-level Cache Lines; Among them, the first-level Cache Line is a high-speed Cache Line; the second-level Cache Line is a sub-speed Cache Line; When the Cache control unit obtains a data request, it first controls the first-level Cache Line to perform a low-latency high-speed search. When a miss occurs, it then generates a second-level index and controls the second-level Cache Line to perform a search based on the second-level index.

7. The cache memory according to claim 1, characterized in that, The data positioning unit is used to determine the position of the requested data in the Cache Line according to the address of the data block, the sub-pixel direction, the address block mode, and the number of bits per pixel.

8. The cache memory according to claim 1, wherein, The dynamic allocation unit is used to dynamically allocate test tasks to the lower-level test unit according to read and write requests, fragment masks, data repeatability, and the position of cached data.

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