A packaging substrate structure and preparation method thereof

Abstract

A packaging substrate structure and its preparation method, wherein the packaging substrate structure comprises: a composite functional layer; a chip located on a side surface of the composite functional layer; and a plurality of discrete stoppers located on the composite functional layer around the sides of the chip, wherein the stoppers comprise: a solder pad located on a side surface of the composite functional layer; and a stopper welded to a surface of the solder pad facing away from the composite functional layer, wherein the lateral characteristic dimension of the stopper is greater than or equal to the lateral characteristic dimension of the solder pad. The packaging substrate structure provided by the present invention achieves high chip positioning accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of packaging substrates, and in particular to a packaging substrate structure and a preparation method thereof. Background Art

[0002] As a crucial component of chip packaging, the package substrate supports and protects the chip, connecting the upper and lower chips or circuit boards. Embedding the chip within the substrate and connecting it to other components via internal and external wiring layers is an effective way to reduce the overall size of the device.

[0003] Currently, there are two main methods for positioning chips embedded in substrates: one is conductive adhesive bonding, and the other is solder reflow bonding. The former, due to uneven conductive adhesive application and thickness, cannot achieve high surface flatness, which can easily lead to warping and displacement. Furthermore, the risk of chip movement during the conductive adhesive curing process can affect alignment accuracy. The latter uses solder reflow bonding to secure the chip, but chip movement during the reflow process cannot be controlled.

[0004] Currently, the positioning accuracy of the positioning structure for embedding the chip into the packaging substrate is low. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the defect of low positioning accuracy of the positioning structure for embedding a chip into a packaging substrate in the prior art, thereby providing a packaging substrate structure and a preparation method.

[0006] The present invention provides a packaging substrate structure, comprising: a composite functional layer; a chip located on one side surface of the composite functional layer; a plurality of discrete limiting members located on the composite functional layer around the side of the chip, wherein the limiting members comprise: a solder pad located on one side surface of the composite functional layer; and a limiting portion welded to a surface of the solder pad facing away from the composite functional layer, wherein a lateral characteristic dimension of the limiting portion is greater than or equal to a lateral characteristic dimension of the solder pad.

[0007] Optionally, the limiting portion is a solder ball, and the lateral characteristic dimension of the limiting portion is the diameter of the solder ball.

[0008] Optionally, the limiting member is provided on each side of the chip.

[0009] Optionally, the chip has a first side and a second side that are relatively arranged, and a third side and a fourth side that are relatively arranged; the several discrete limiting members include: a first limiting member and a second limiting member located on the first side of the chip; a third limiting member and a fourth limiting member located on the second side of the chip; a fifth limiting member and a sixth limiting member located on the third side of the chip; and a seventh limiting member and an eighth limiting member located on the fourth side of the chip.

[0010] Optionally, the composite functional layer includes: a core plate structure; a first laminate structure located on a side surface of the core plate structure facing the chip; and a second laminate structure located on a side surface of the core plate structure facing away from the first laminate structure.

[0011] Optionally, the core plate structure includes: a core plate; a third conductive column passing through the core plate; a first inner wire layer located on a side surface of the core plate facing away from the second laminate structure and covered by the first laminate structure; a second inner wire layer located on a side surface of the core plate facing away from the first laminate structure and covered by the second laminate structure; the first inner wire layer and the second inner wire layer are electrically connected through the third conductive column.

[0012] Optionally, the first laminate structure includes: a first laminate; a fourth conductive column passing through the first laminate; a third inner layer located on the surface of the first laminate facing away from the core plate structure; the third inner layer is electrically connected to the first inner layer through the fourth conductive column.

[0013] Optionally, it also includes: a first plastic encapsulation layer, located on one side surface of the composite functional layer and burying the chip and the several discrete limiting parts; a first conductive column, passing through the first plastic encapsulation layer on the chip; a sixth conductive column, the sixth conductive column passing through the first plastic encapsulation layer on the side of the chip; a first outer line layer, the first outer line layer is located on the side surface of the first plastic encapsulation layer facing away from the composite functional layer, the first outer line layer is electrically connected to the chip through the first conductive column; the first outer line layer is electrically connected to the third inner line layer through the sixth conductive column.

[0014] Optionally, the composite functional layer also includes: a second plastic sealing layer, located on the surface of the second laminate structure facing away from the core board structure; a second conductive column, passing through the second plastic sealing layer; a second outer line layer, located on the surface of the second plastic sealing layer facing away from the second laminate structure; the second laminate structure includes: a second laminate, a fifth conductive column passing through the second laminate, a fourth inner line layer located on the surface of the second laminate facing away from the core board structure and covered by the second plastic sealing layer; the fourth inner line layer is electrically connected to the second inner line layer through the fifth conductive column; the fourth inner line layer is electrically connected to the second outer line layer through the second conductive column.

[0015] Optionally, the distance between the limiting portion and the chip is greater than or equal to zero and less than or equal to 5 μm.

[0016] The present invention also provides a method for preparing a package substrate structure, comprising: forming a composite functional layer;

[0017] A plurality of discrete limiting members are formed on the surface of one side of the composite functional layer, and the steps of forming the limiting members include: forming a solder pad on the surface of one side of the composite functional layer; providing a limiting portion, welding the limiting portion to the surface of the solder pad facing away from the composite functional layer, and the lateral characteristic size of the limiting portion is greater than or equal to the lateral characteristic size of the solder pad; arranging a chip on the surface of the composite functional layer, and the chip is limited by the plurality of discrete limiting members.

[0018] Optionally, one side surface of the composite functional layer has a chip pre-embedded area; the chip pre-embedded area has a first side and a second side arranged opposite to each other, and a third side and a fourth side arranged opposite to each other; the step of forming the plurality of discrete limiting members includes: forming a first soldering pad and a second soldering pad on the first side of the chip pre-embedded area; in the process of forming the first soldering pad and the second soldering pad, forming a third soldering pad and a fourth soldering pad on the second side of the chip pre-embedded area, forming a fifth soldering pad and a sixth soldering pad on the third side of the chip pre-embedded area, and forming a seventh soldering pad and an eighth soldering pad on the fourth side of the chip pre-embedded area; providing a first limiting portion, a second limiting portion, a third limiting portion, a fourth limiting portion, a fifth limiting portion, a sixth limiting portion, a seventh limiting portion and an eighth limiting portion; welding the first limiting portion to the surface of the first soldering pad facing away from the composite functional layer; The second limiting portion is welded together with the surface of the second solder pad facing away from the composite functional layer; the third limiting portion is welded together with the surface of the third solder pad facing away from the composite functional layer; the fourth limiting portion is welded together with the surface of the fourth solder pad facing away from the composite functional layer; the fifth limiting portion is welded together with the surface of the fifth solder pad facing away from the composite functional layer; the sixth limiting portion is welded together with the surface of the sixth solder pad facing away from the composite functional layer; the seventh limiting portion is welded together with the surface of the seventh solder pad facing away from the composite functional layer; the eighth limiting portion is welded together with the surface of the eighth solder pad facing away from the composite functional layer; the step of arranging a chip on the surface of the composite functional layer is: arranging a chip in the chip embedded area.

[0019] Optionally, the step of forming the composite functional layer includes: forming a core panel structure; forming a first laminate structure on one side surface of the core panel structure; and forming a second laminate structure on a side surface of the core panel structure facing away from the first laminate structure.

[0020] Optionally, the step of forming the core plate structure includes: providing a core plate; forming a third conductive column penetrating the core plate; forming a first inner line layer and a second inner line layer on both side surfaces of the core plate, respectively, wherein the first inner line layer and the second inner line layer are electrically connected via the third conductive column;

[0021] After the first buildup structure is formed, the first buildup structure covers the first inner wire layer; after the second buildup structure is formed, the second buildup structure covers the second inner wire layer.

[0022] Optionally, the step of forming the first laminate structure includes: forming a first laminate covering the first inner line layer; forming a fourth conductive column passing through the first laminate; forming a third inner line layer on the surface of the first laminate facing away from the core board structure; and the third inner line layer is electrically connected to the first inner line layer through the fourth conductive column.

[0023] Optionally, it also includes: forming a first plastic encapsulation layer on one side surface of the composite functional layer, the first plastic encapsulation layer burying the chip and the several discrete limiting parts; forming a first conductive column passing through the first plastic encapsulation layer on the chip; forming a sixth conductive column passing through the first plastic encapsulation layer on the side of the chip; forming a first outer line layer on the side surface of the first plastic encapsulation layer facing away from the composite functional layer, the first outer line layer is electrically connected to the chip through the first conductive column, and the first outer line layer is electrically connected to the third inner line layer through the sixth conductive column.

[0024] Optionally, the step of forming the composite functional layer also includes: forming a second plastic sealing layer on the side surface of the second laminate structure facing away from the core plate structure; forming a second conductive column passing through the second plastic sealing layer; forming a second outer line layer on the side surface of the second plastic sealing layer facing away from the second laminate structure; the step of forming the second laminate structure includes: forming a second laminate on the side surface of the core plate structure facing away from the first laminate structure; forming a fifth conductive column passing through the second laminate; forming a fourth inner line layer on the side surface of the second laminate facing away from the core plate structure; the fourth inner line layer is electrically connected to the second inner line layer through the fifth conductive column; the fourth inner line layer is electrically connected to the second outer line layer through the second conductive column.

[0025] The technical solution of the present invention has the following advantages:

[0026] The packaging substrate structure provided by the technical solution of the present invention comprises a plurality of discrete limiting members located on the composite functional layer around the side of the chip, and the limiting members are used to limit the position of the chip. The limiting members include: a solder pad located on the surface of one side of the composite functional layer; and a limiting portion welded to the surface of the solder pad facing away from the composite functional layer. The accuracy of chip positioning is mainly determined by the center position of the solder pad and the size deviation of the limiting portion itself. The center position of the solder pad is controlled with high accuracy, and even if the lateral characteristic size of the solder pad changes, it will not affect the center position of the limiting portion. In addition, because the limiting portion is a standard part, the lateral characteristic size deviation of the limiting portion is small, and the lateral characteristic size of the limiting portion is greater than or equal to the lateral characteristic size of the solder pad, the limiting member can be used to directly position the chip with high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 A preparation flow chart of a packaging substrate structure according to an embodiment of the present invention;

[0029] Figures 2 to 9 The figure is a schematic structural diagram of a preparation process of a packaging substrate structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] This embodiment provides a method for preparing a package substrate structure. Figure 1 , including the following steps:

[0035] S1: forming a composite functional layer;

[0036] S2: forming a plurality of discrete limiting members on a surface of one side of the composite functional layer, wherein the step of forming the limiting members comprises: forming a solder pad on a surface of one side of the composite functional layer; providing a limiting portion, and soldering the limiting portion to a surface of the solder pad facing away from the composite functional layer, wherein a lateral characteristic dimension of the limiting portion is greater than or equal to a lateral characteristic dimension of the solder pad;

[0037] S3: a chip is arranged on the surface of the composite functional layer, wherein the chip is limited by a plurality of separate limiting members.

[0038] The accuracy of chip positioning is primarily determined by the center position of the pad and the dimensional deviation of the retaining element itself. The pad's center position is precisely controlled, and even if the pad's lateral characteristic dimensions vary, this does not affect the center position of the retaining element. Furthermore, because the retaining element is a standard component, its lateral characteristic dimension deviation is minimal, and its lateral characteristic dimension is greater than or equal to that of the pad. Therefore, the retaining element can be used to directly position the chip with high precision.

[0039] The following combination Figures 2 to 9 Detailed description.

[0040] The steps of forming the composite functional layer include: forming a core plate structure; forming a first laminate structure on one side surface of the core plate structure; and forming a second laminate structure on the side surface of the core plate structure facing away from the first laminate structure.

[0041] refer to Figure 2The steps of forming the core plate structure include: providing a core plate 100; forming a third conductive column 103 passing through the core plate; forming a first inner line layer 101 and a second inner line layer 102 on both side surfaces of the core plate 100, respectively, and the first inner line layer 101 and the second inner line layer 102 are electrically connected through the third conductive column 103.

[0042] refer to Figure 3 The steps of forming the first build-up structure include: forming a first build-up layer 200 covering the first inner line layer 101; forming a fourth conductive column 201 penetrating the first build-up layer 200; forming a third inner line layer 202 on a surface of the first build-up layer 200 facing away from the core plate structure; and electrically connecting the third inner line layer 202 to the first inner line layer 101 via the fourth conductive column 201.

[0043] Continue to refer Figure 3 The steps of forming the second laminate structure include: forming a second laminate 300 on the surface of the core plate structure on the side facing away from the first laminate structure; forming a fifth conductive column 301 passing through the second laminate 300; forming a fourth inner line layer 302 on the surface of the second laminate 300 on the side facing away from the core plate structure; and electrically connecting the fourth inner line layer 302 and the second inner line layer 102 through the fifth conductive column 301.

[0044] After the first buildup structure is formed, the first buildup structure covers the first inner line layer 101 ; after the second buildup structure is formed, the second buildup structure covers the second inner line layer 102 .

[0045] The step of forming the composite functional layer also includes: forming a second plastic encapsulation layer 600 on the side surface of the second laminate structure facing away from the core plate structure; forming a second conductive column 601 passing through the second plastic encapsulation layer 600; forming a second outer line layer 602 on the side surface of the second plastic encapsulation layer 600 facing away from the second laminate structure; and the fourth inner line layer 302 is electrically connected to the second outer line layer 602 through the second conductive column 601.

[0046] Before forming the second plastic encapsulation layer 600, after forming the first laminate structure, a number of discrete limiting members are formed on the surface of the first laminate structure on the side facing away from the core board structure, and the steps of forming the limiting members include: forming a solder pad on the surface of one side of the composite functional layer; providing a limiting portion, and welding the limiting portion to the surface of the solder pad on the side facing away from the composite functional layer, wherein the lateral characteristic dimension of the limiting portion is greater than or equal to the lateral characteristic dimension of the solder pad.

[0047] refer to Figures 4 to 7, the first laminated structure has a chip embedded area 400 on one side facing away from the core board structure; the chip embedded area 400 has a first side 401 and a second side 402, as well as a third side 403 and a fourth side 404, which are arranged opposite to each other; the steps of forming the plurality of discrete limiting members include: forming a first solder pad 405 and a second solder pad 406 on the first side 401 of the chip embedded area; in the process of forming the first solder pad 405 and the second solder pad 406, forming a third solder pad 407 and a fourth solder pad 408 on the second side 402 of the chip embedded area, forming a fifth solder pad 409 and a sixth solder pad 410 on the third side 403 of the chip embedded area, and forming a seventh solder pad 411 and an eighth solder pad 412 on the fourth side 404 of the chip embedded area; providing a first limiting portion, a second limiting portion, a third limiting portion, a fourth limiting portion, a fifth limiting portion, a sixth limiting portion, a seventh limiting portion and an eighth limiting portion. the first limiting portion and the surface of the first solder pad 405 facing away from the composite functional layer; the second limiting portion and the surface of the second solder pad 406 facing away from the composite functional layer; the third limiting portion and the surface of the third solder pad 407 facing away from the composite functional layer; the fourth limiting portion and the surface of the fourth solder pad 408 facing away from the composite functional layer; the fifth limiting portion and the surface of the fifth solder pad 409 facing away from the composite functional layer; the sixth limiting portion and the surface of the sixth solder pad 410 facing away from the composite functional layer; the seventh limiting portion and the surface of the seventh solder pad 411 facing away from the composite functional layer; the eighth limiting portion and the surface of the eighth solder pad 412 facing away from the composite functional layer.

[0048] In this embodiment, the first to eighth limiting portions are solder balls. In other embodiments, the limiting portions may be other components.

[0049] In this embodiment, the process of welding the limiting portion and the pad is a reflow process. In other embodiments, other welding processes may be used.

[0050] refer to Figure 8 The step of arranging a chip on the surface of the composite functional layer is as follows: arranging a chip 500 in the chip embedded area 400 .

[0051] The distance between the limiting portion and the chip 500 is greater than or equal to zero and less than or equal to 5 μm. The minimum value of the distance between the limiting portion and the chip 500 is zero. If the distance between the limiting portion and the chip 500 is greater than 5 μm, the positioning accuracy of the limiting portion for the chip 500 is low, and the positioning effect is weakened.

[0052] refer to Figure 9 After the chip 500 is arranged on the surface of the composite functional layer, a first plastic encapsulation layer 700 is formed on one side surface of the composite functional layer, and the first plastic encapsulation layer 700 buries the chip 500 and the plurality of discrete limiting members; a first conductive column 703 is formed that passes through the first plastic encapsulation layer 700 on the chip 500; a sixth conductive column 701 is formed that passes through the first plastic encapsulation layer 700 on the side of the chip; a first outer line layer 702 is formed on the side surface of the first plastic encapsulation layer 700 that is away from the composite functional layer, the first outer line layer 702 is electrically connected to the chip 500 through the first conductive column 703, and the first outer line layer 702 is electrically connected to the third inner line layer 202 through the sixth conductive column 701.

[0053] Accordingly, this embodiment also provides a packaging substrate structure, referring to Figure 6 and Figure 9 ,include:

[0054] A composite functional layer; a chip 500, located on one side surface of the composite functional layer; a plurality of discrete limiting members located on the composite functional layer around the side of the chip 500, the limiting members comprising: a solder pad located on one side surface of the composite functional layer; a limiting portion welded to the surface of the solder pad facing away from the composite functional layer, the lateral characteristic dimension of the limiting portion being greater than or equal to the lateral characteristic dimension of the solder pad.

[0055] The limiting portion is a solder ball, and the transverse characteristic dimension of the limiting portion is the diameter of the solder ball.

[0056] The limiting member is provided on each side of the chip 500 .

[0057] The chip 500 has a first side 401 and a second side 402 arranged opposite to each other, and a third side 403 and a fourth side 404 arranged opposite to each other; the plurality of discrete limiting members include: a first limiting member and a second limiting member located on the first side 401 of the chip 500; a third limiting member and a fourth limiting member located on the second side 402 of the chip 500; a fifth limiting member and a sixth limiting member located on the third side 403 of the chip 500; and a seventh limiting member and an eighth limiting member located on the fourth side 404 of the chip 500.

[0058] The composite functional layer includes: a core plate structure; a first laminate structure located on a side of the core plate structure facing the chip 500; and a second laminate structure located on a side of the core plate structure facing away from the first laminate structure.

[0059] The core plate structure includes: a core plate 100; a third conductive column 103 passing through the core plate 100; a first inner line layer 101 located on the side surface of the core plate 100 facing away from the second laminate structure and covered by the first laminate structure; a second inner line layer 102 located on the side surface of the core plate 100 facing away from the first laminate structure and covered by the second laminate structure; the first inner line layer 101 and the second inner line layer 102 are electrically connected through the third conductive column 103.

[0060] The first laminate structure includes: a first laminate 200; a fourth conductive column 201 passing through the first laminate 200; a third inner layer 202 located on the surface of the first laminate 200 facing away from the core structure; the third inner layer 202 is electrically connected to the first inner layer 101 through the fourth conductive column 201.

[0061] The first plastic encapsulation layer 700 is located on one side surface of the composite functional layer and buries the chip 500, the plurality of discrete limiting members, and the third inner line layer 202; the first conductive pillar 703 penetrates the first plastic encapsulation layer 700 on the chip 500; the sixth conductive pillar 701 penetrates the first plastic encapsulation layer 700 on the side of the chip 500; the first outer line layer 702 is located on the side surface of the first plastic encapsulation layer 700 facing away from the composite functional layer, the first outer line layer 702 is electrically connected to the chip 500 through the first conductive pillar 703; the first outer line layer 702 is electrically connected to the third inner line layer 202 through the sixth conductive pillar 701.

[0062] The composite functional layer also includes: a second plastic encapsulation layer 600, located on the surface of the second laminate structure facing away from the core board structure; a second conductive column 601, passing through the second plastic encapsulation layer 600; and a second outer line layer 602, located on the surface of the second plastic encapsulation layer 600 facing away from the second laminate structure.

[0063] The second build-up structure includes: a second build-up layer 300, a fifth conductive pillar 301 extending through the second build-up layer 300, and a fourth inner line layer 302 located on a surface of the second build-up layer 300 facing away from the core structure and covered by the second plastic encapsulation layer 600; the fourth inner line layer 302 is electrically connected to the second inner line layer 102 via the fifth conductive pillar 301;

[0064] The fourth inner line layer 302 is electrically connected to the second outer line layer 602 through the second conductive pillar 601 .

[0065] The distance between the limiting portion and the chip 500 is greater than or equal to zero and less than or equal to 5 μm.

[0066] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A packaging substrate structure, characterized in that: include: Composite functional layer; A chip is located on one side surface of the composite functional layer; A plurality of discrete stoppers located on the composite functional layer around the side of the chip, the stoppers comprising: a solder pad located on one surface of the composite functional layer; a stopper welded to a surface of the solder pad facing away from the composite functional layer, the stopper having a lateral characteristic dimension greater than or equal to the lateral characteristic dimension of the solder pad; The limiting part is a standard part.

2. The packaging substrate structure according to claim 1, wherein: The limiting portion is a solder ball, and the transverse characteristic dimension of the limiting portion is the diameter of the solder ball.

3. The packaging substrate structure according to claim 1, wherein: The limiting component is provided on each side of the chip.

4. The packaging substrate structure according to claim 3, wherein: The chip has a first side and a second side that are opposite to each other, and a third side and a fourth side that are opposite to each other; The several discrete limiting members include: a first limiting member and a second limiting member located on the first side of the chip; a third limiting member and a fourth limiting member located on the second side of the chip; a fifth limiting member and a sixth limiting member located on the third side of the chip; and a seventh limiting member and an eighth limiting member located on the fourth side of the chip.

5. The packaging substrate structure according to claim 1, wherein: The composite functional layer includes: a core plate structure; a first laminate structure located on a side surface of the core plate structure facing the chip; and a second laminate structure located on a side surface of the core plate structure facing away from the first laminate structure.

6. The packaging substrate structure according to claim 5, wherein: The core plate structure includes: a core plate; a third conductive column passing through the core plate; a first inner wire layer located on a surface of the core plate facing away from the second laminate structure and covered by the first laminate structure; a second inner wire layer located on a surface of the core plate facing away from the first laminate structure and covered by the second laminate structure; the first inner wire layer and the second inner wire layer are electrically connected through the third conductive column.

7. The packaging substrate structure according to claim 6, wherein: The first build-up structure includes: a first build-up layer; a fourth conductive column running through the first build-up layer; a third inner line layer located on a surface of the first build-up layer facing away from the core plate structure; the third inner line layer is electrically connected to the first inner line layer through the fourth conductive column.

8. The packaging substrate structure according to claim 7, wherein: Also includes: a first plastic encapsulation layer, located on one side surface of the composite functional layer and burying the chip and the plurality of discrete stoppers; a first conductive pillar, penetrating the first plastic encapsulation layer on the chip; and a sixth conductive pillar, penetrating the first plastic encapsulation layer on the side of the chip; The first outer line layer is located on the surface of the first plastic packaging layer on the side facing away from the composite functional layer. The first outer line layer is electrically connected to the chip through the first conductive column; the first outer line layer is electrically connected to the third inner line layer through the sixth conductive column.

9. The packaging substrate structure according to claim 6, wherein: The composite functional layer further includes: a second plastic encapsulation layer, located on a surface of the second laminate structure facing away from the core plate structure; a second conductive column, passing through the second plastic encapsulation layer; a second outer line layer, located on a surface of the second plastic encapsulation layer facing away from the second laminate structure; The second build-up structure includes: a second build-up layer, a fifth conductive post extending through the second build-up layer, and a fourth inner wire layer located on a surface of the second build-up layer facing away from the core structure and covered by the second plastic encapsulation layer; the fourth inner wire layer and the second inner wire layer are electrically connected via the fifth conductive post; The fourth inner line layer is electrically connected to the second outer line layer through the second conductive column.

10. The package substrate structure according to claim 1, wherein: The distance between the limiting portion and the chip is greater than or equal to zero and less than or equal to 5 μm.

11. A method for preparing a package substrate structure, characterized in that: include: forming a composite functional layer; A plurality of discrete limiting members are formed on one side surface of the composite functional layer, wherein the step of forming the limiting members comprises: forming a solder pad on one side surface of the composite functional layer; Providing a limiting portion, welding the limiting portion to a surface of the pad facing away from the composite functional layer, wherein a lateral characteristic dimension of the limiting portion is greater than or equal to a lateral characteristic dimension of the pad; A chip is arranged on the surface of the composite functional layer, wherein the chip is limited by a plurality of discrete limiting members; The limiting part is a standard part.

12. The method for preparing a package substrate structure according to claim 11, wherein: One side surface of the composite functional layer has a chip pre-embedded area; the chip pre-embedded area has a first side and a second side that are oppositely arranged, and a third side and a fourth side that are oppositely arranged; The step of forming the plurality of discrete limiting members includes: forming a first solder pad and a second solder pad on a first side of the chip embedded area; in the process of forming the first solder pad and the second solder pad, forming a third solder pad and a fourth solder pad on a second side of the chip embedded area, forming a fifth solder pad and a sixth solder pad on a third side of the chip embedded area, and forming a seventh solder pad and an eighth solder pad on a fourth side of the chip embedded area; Providing a first limiting portion, a second limiting portion, a third limiting portion, a fourth limiting portion, a fifth limiting portion, a sixth limiting portion, a seventh limiting portion and an eighth limiting portion; Welding the first limiting portion and the surface of the first welding pad facing away from the composite functional layer together; welding the second limiting portion and the surface of the second welding pad facing away from the composite functional layer; Welding the third limiting portion and the surface of the third welding pad facing away from the composite functional layer together; Welding the fourth limiting portion and the surface of the fourth welding pad facing away from the composite functional layer together; Welding the fifth limiting portion and the surface of the fifth welding pad facing away from the composite functional layer together; Welding the sixth limiting portion and the surface of the sixth welding pad facing away from the composite functional layer together; Welding the seventh limiting portion and the surface of the seventh welding pad facing away from the composite functional layer together; Welding the eighth limiting portion and the surface of the eighth welding pad facing away from the composite functional layer together; The step of arranging a chip on the surface of the composite functional layer comprises: arranging a chip in the chip pre-embedded area.

13. The method for preparing a package substrate structure according to claim 11, wherein: The steps of forming the composite functional layer include: forming a core plate structure; forming a first laminate structure on one side surface of the core plate structure; and forming a second laminate structure on the side surface of the core plate structure facing away from the first laminate structure.

14. The method for preparing a package substrate structure according to claim 13, wherein: The steps of forming the core plate structure include: providing a core plate; forming a third conductive column penetrating the core plate; forming a first inner line layer and a second inner line layer on both sides of the core plate, respectively, wherein the first inner line layer and the second inner line layer are electrically connected via the third conductive column; After the first buildup structure is formed, the first buildup structure covers the first inner wire layer; after the second buildup structure is formed, the second buildup structure covers the second inner wire layer.

15. The method for preparing a package substrate structure according to claim 14, wherein: The steps of forming the first laminate structure include: forming a first laminate covering the first inner line layer; forming a fourth conductive column passing through the first laminate; forming a third inner line layer on a surface of the first laminate facing away from the core plate structure; and electrically connecting the third inner line layer to the first inner line layer through the fourth conductive column.

16. The method for preparing a package substrate structure according to claim 15, wherein: Also includes: forming a first plastic encapsulation layer on one side surface of the composite functional layer, wherein the first plastic encapsulation layer buries the chip and the plurality of discrete limiting members; A first conductive column is formed that passes through the first plastic encapsulation layer on the chip; a sixth conductive column is formed that passes through the first plastic encapsulation layer on the side of the chip; a first outer line layer is formed on the surface of the first plastic encapsulation layer on the side facing away from the composite functional layer, the first outer line layer is electrically connected to the chip through the first conductive column, and the first outer line layer is electrically connected to the third inner line layer through the sixth conductive column.

17. The method for preparing a package substrate structure according to claim 14, wherein: The step of forming the composite functional layer further includes: forming a second plastic encapsulation layer on a surface of the second laminate structure facing away from the core plate structure; forming a second conductive column penetrating the second plastic encapsulation layer; and forming a second outer line layer on a surface of the second plastic encapsulation layer facing away from the second laminate structure. The steps of forming a second laminate structure include: forming a second laminate on the surface of the core plate structure facing away from the first laminate structure; forming a fifth conductive column passing through the second laminate; forming a fourth inner line layer on the surface of the second laminate facing away from the core plate structure; the fourth inner line layer and the second inner line layer are electrically connected through the fifth conductive column; and the fourth inner line layer and the second outer line layer are electrically connected through the second conductive column.

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