Display panel and display device

Abstract

The present application discloses a display panel and a display device, wherein the display panel includes a first active layer, a gate layer, a second active layer and a source-drain layer, and a first channel, a second channel, a gate, a source and a drain of a compensation transistor are sequentially constructed in the first active layer, the second active layer, the gate layer and the source-drain layer, and the first channel is constructed as one of an N-type channel and a P-type channel, and the second channel is constructed as the other of the N-type channel and the P-type channel. Under the control of the rising edge and / or falling edge of a square wave signal, the gate of the compensation transistor can pulse a DC signal connected thereto; at the same time, the compensation transistor uses fewer film layers to construct the gate, the source and the drain, thereby simplifying the structure and manufacturing process of the compensation transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Display technology requires the use of a large number of thin-film transistors, for example, pixel circuits or gate drive circuits, etc. However, existing single thin-film transistors are turned on in response to one state of high potential or low potential, and are turned off in response to the other state of high potential or low potential. They are unable to pulse the input DC signal, and thus cannot meet the diverse needs of display technology.

[0003] Therefore, it is necessary to propose a thin film transistor that can process direct current signals in pulse form to meet the continuous development of display technology.

[0004] It should be noted that the above introduction to the background technology is only for the purpose of facilitating a clear and complete understanding of the technical solution of the present application. Therefore, it cannot be considered that the above technical solution is well known to those skilled in the art simply because it appears in the background technology of the present application. Summary of the invention

[0005] The present application provides a display panel and a display device to solve the technical problem of the lack of thin film transistors with pulse processing capability in conventional technical solutions.

[0006] In a first aspect, the present application provides a display panel, which includes a first active layer, a gate layer, a second active layer and a source-drain layer, the first active layer includes a first source region, a first channel region and a first drain region of a compensation transistor; the gate layer includes a gate of the compensation transistor, and the projection of the gate of the compensation transistor on the first active layer at least partially overlaps with the first channel region; the second active layer includes a second source region, a second channel region and a second drain region of the compensation transistor, and the projection of the second channel region on the gate layer at least partially overlaps with the gate of the compensation transistor; the source-drain layer includes a source of the compensation transistor and a drain of the compensation transistor, the source of the compensation transistor is electrically connected to the first source region and the second source region, and the drain of the compensation transistor is electrically connected to the first drain region and the second drain region; wherein the first channel region is one of an N-type channel region or a P-type channel region, and the second channel region is the other of an N-type channel region or a P-type channel region.

[0007] In some embodiments, the material forming the N-type channel region includes oxide, and the material forming the P-type channel region includes low temperature polysilicon.

[0008] In some embodiments, the display panel also includes a positive power signal line, a drive signal line, and a pixel circuit, the positive power signal line is electrically connected to one of the source / drain of the compensation transistor; the drive signal line is electrically connected to the gate of the compensation transistor, and the drive signal line is used to transmit a square wave signal; the pixel circuit is electrically connected to the other one of the source / drain of the compensation transistor.

[0009] In some embodiments, the positive power signal line is used to transmit a positive power signal, and the positive power signal has a first high potential and / or a second high potential; the high potential of the square wave signal is used to turn on an N-channel transistor, and the low potential of the square wave signal is used to turn on a P-channel transistor.

[0010] In some embodiments, the second high potential is greater than the first high potential; when the square wave signal is at a low potential, the positive power supply signal is one of the first high potential or the second high potential; when the square wave signal is at a high potential, the positive power supply signal is the other of the first high potential or the second high potential.

[0011] In some of the embodiments, the working phase of the pixel circuit includes a light emitting phase, during which the square wave signal switches between a low potential and a high potential at least once.

[0012] In some embodiments, the pixel circuit includes a driving transistor, and one of the source / drain of the driving transistor is electrically connected to the other of the source / drain of the compensation transistor.

[0013] In some embodiments, the pixel circuit also includes a first light-emitting control transistor, one of the source / drain of the first light-emitting control transistor is electrically connected to another of the source / drain of the compensation transistor, and the other of the source / drain of the first light-emitting control transistor is electrically connected to another of the source / drain of the compensation transistor.

[0014] In some embodiments, a positive power signal line is electrically connected to at least two compensation transistors.

[0015] In a second aspect, the present application provides a display device, comprising a display panel according to at least one of the above-mentioned embodiments, wherein the display panel comprises a display area and a fan-out area adjacent to the display area, and the compensation transistor is located in the display area and / or the fan-out area.

[0016] The display panel and display device provided by the present application sequentially construct the first channel, the second channel, the gate, the source and the drain of the compensation transistor in the first active layer, the second active layer, the gate layer and the source-drain layer, and the first channel is constructed as one of the N-type channel and the P-type channel, and the second channel is constructed as the other of the N-type channel and the P-type channel. The gate of the compensation transistor is controlled by the rising edge and / or falling edge of the square wave signal, and the compensation transistor can pulse the DC signal connected. At the same time, the compensation transistor uses fewer film layers to form the gate, the source and the drain, thereby simplifying the structure and manufacturing process of the compensation transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0018] Figure 1 It is a structural schematic diagram of a display panel in a traditional technical solution.

[0019] Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0020] Figure 3 for Figure 2 Schematic diagram of the spatial relationship between the first channel region, the gate and the second channel region of the compensation transistor.

[0021] Figure 4 A circuit schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0022] Figure 5 Another circuit schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0023] Figure 6 for Figure 4 or Figure 5 Timing diagram of the pixel circuit shown in .

[0024] Figure 7 A circuit schematic diagram of multiple compensation transistor connections provided in an embodiment of the present application.

[0025] Figure 8 Another structural schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0027] like Figure 1 The display panel shown includes a flexible substrate PI, a buffer layer BF1, a composite film layer LY3, an active layer PY1, a gate insulating layer GI1, a first gate layer, a gate insulating layer GI2, a second gate layer, an interlayer insulating layer ILD1, an active layer IG1, a gate insulating layer GI3, a third gate layer, an interlayer insulating layer ILD2, a first metal layer, an insulating layer PV1, a flat layer PLN1, a second metal layer SD2, a flat layer PLN2, an anode layer AND, a pixel definition layer PDL, an organic light-emitting layer OL1 and a pillar PS.

[0028] The anode layer AND includes one or more anodes AND1. The second metal layer SD2 includes one or more metal blocks SD21. The metal block SD21 is electrically connected to the anode AND1 and the drain SD12.

[0029] The material of the active layer PY1 is low temperature polysilicon. The first gate layer includes a gate GE11. The second gate layer includes a gate GE21. The active layer PY1, the gate GE11 and the gate GE21 at least partially overlap in the thickness direction of the display panel, and the first metal layer includes a source electrode SD11 and a drain electrode SD12, thereby forming a low temperature polysilicon thin film transistor.

[0030] The second gate layer further includes a gate GE22. The material of the active layer IG1 is indium gallium zinc oxide. The third gate layer includes a gate GE31. The gate GE22, the active layer IG1 and the gate GE31 at least partially overlap in the thickness direction of the display panel, and the first metal layer further includes a source electrode SD13 and a drain electrode SD14, so as to form a metal oxide thin film transistor.

[0031] The drain connection region of the low temperature polysilicon thin film transistor is electrically connected to the source of the metal oxide thin film transistor, so that the low temperature polysilicon thin film transistor and the metal oxide thin film transistor can be combined to form an oxide thin film transistor.

[0032] It can be seen from this that the traditional technology requires more composition processes to construct an oxide thin film transistor or the film structure is too complex. In view of this, it is necessary to propose a polycrystalline oxide thin film transistor or a low-temperature polycrystalline oxide thin film transistor with fewer composition processes or a simple film structure to process DC signals in a pulsed manner to meet the development needs of display technology.

[0033] Specifically, see Figures 2 to 8 ,like Figure 2 As shown, this embodiment provides a display panel, which includes a substrate 100, a composite film layer 200, a first active layer 210, a composite gate insulating layer 300, a gate layer 310, a second active layer 320, a source and drain electrode layer 330, a flat layer 400, a pixel definition layer 500, an anode layer 700 and a pillar 600. Among them, the anode layer 700 includes one or more anodes 710, and the anode 710 can be electrically connected to the drain 331 of the compensation transistor T1. The composite film layer 200 may include at least one buffer layer. The composite gate insulating layer 300 may include two gate insulating layers, and the gate layer 310 is located between the two gate insulating layers.

[0034] The first active layer 210 includes a first source region, a first channel region 211, and a first drain region of the compensation transistor T1; the gate layer 310 includes a gate 311 of the compensation transistor T1, and the projection of the gate 311 of the compensation transistor T1 on the first active layer 210 at least partially overlaps with the first channel region 211; the second active layer 320 includes a second source region, a second channel region 321, and a second drain region of the compensation transistor T1, and the projection of the second channel region 321 on the gate layer 310 overlaps with the projection of the compensation transistor T1. The gate 311 of T1 at least partially overlaps; the source-drain layer 330 includes a source 332 of the compensation transistor T1 and a drain 331 of the compensation transistor T1, the source 332 of the compensation transistor T1 is electrically connected to the first source region and the second source region, and the drain 331 of the compensation transistor T1 is electrically connected to the first drain region and the second drain region; wherein the first channel region 211 is one of an N-type channel region or a P-type channel region, and the second channel region 321 is the other of an N-type channel region or a P-type channel region.

[0035] It can be understood that the display panel provided in this embodiment constructs the first channel, the second channel, the gate, the source and the drain of the compensation transistor T1 in the first active layer 210, the second active layer 320, the gate layer 310 and the source-drain layer 330 in sequence, and the first channel is constructed as one of the N-type channel and the P-type channel, and the second channel is the other of the N-type channel and the P-type channel. Under the control of the rising edge and / or falling edge of the square wave signal XCK, the gate 311 of the compensation transistor T1 can pulse the DC signal connected thereto; at the same time, the compensation transistor T1 constructs the gate, the source and the drain with fewer film layers, thereby simplifying the structure and manufacturing process of the compensation transistor T1.

[0036] In one embodiment, the constituent material of the N-type channel region includes oxide, specifically, the oxide may be a metal oxide, preferably, indium gallium zinc oxide. The constituent material of the P-type channel region includes low temperature polysilicon.

[0037] like Figure 3 As shown, the first channel region 211 is located in a first plane formed by the X-axis and the Y-axis, the second plane where the gate 311 of the compensation transistor T1 is located is parallel to the first plane, and the third plane where the second channel region 321 is located is parallel to the first plane or the second plane. Along the Z-axis direction, the first channel region 211, the gate 311 of the compensation transistor T1, and the second channel region 321 can be arranged in sequence; or, the first channel region 211 and the second channel region 321 can be interchanged.

[0038] like Figure 4 or Figure 5 As shown, in one embodiment, the display panel also includes a positive power signal line VDDL, a drive signal line XCKL and a pixel circuit 90, the positive power signal line VDDL is electrically connected to one of the source 332 / drain of the compensation transistor T1; the drive signal line XCKL is electrically connected to the gate 311 of the compensation transistor T1, and the drive signal line XCKL is used to transmit the square wave signal XCK; the pixel circuit 90 is electrically connected to the other of the source 332 / drain of the compensation transistor T1.

[0039] It can be understood that the compensation transistor T1 can be equivalent to a parallel connection of an N-channel transistor T11 and a P-channel transistor T12, that is, one of the source / drain of the transistor T11 is connected to one of the source / drain of the transistor T12, the other of the source / drain of the transistor T11 is connected to the other of the source / drain of the transistor T12, and the gate of the transistor T11 is connected to the gate of the transistor T12. The high potential of the square wave signal XCK can turn on the transistor T11, and the high potential of the square wave signal XCK can turn on the transistor T12. Therefore, when the square wave signal XCK switches between the high potential and the low potential, a flash phenomenon, i.e., a pulse of extremely small width, will be formed for the positive power supply signal VDD flowing through the compensation transistor T1, that is, a DC signal can be processed in a pulsed manner.

[0040] The positive power signal VDD shows an attenuation trend from the beginning of output due to load voltage drop and thin film transistor leakage, resulting in a large voltage difference between the upper and lower parts of the panel, which is specifically manifested in a large difference in brightness between the upper and lower parts of the display panel.

[0041] Therefore, after the positive power signal VDD is pulsed through the compensation transistor T1, the potential of the positive power signal VDD can be restored to the initial potential without loss after each pulse, and then provided to the corresponding pixel circuit 90. In this way, the voltage of the positive power signal VDD supplied to different pixel circuits 90 can be reduced, thereby reducing the brightness difference of the display panel.

[0042] like Figure 4 As shown, in one embodiment, the pixel circuit 90 includes a driving transistor T2 , and one of the source / drain of the driving transistor T2 is electrically connected to the other of the source 332 / drain of the compensation transistor T1 .

[0043] The pixel circuit 90 may further include a light emitting device LED, wherein the anode of the light emitting device LED is electrically connected to the other of the source 332 / drain of the compensation transistor T1, and the cathode of the light emitting device LED is electrically connected to one of the source / drain of the driving transistor T2. Figure 5 As shown, the anode of the light emitting device LED is electrically connected to the other of the source / drain of the driving transistor T2, and the cathode of the light emitting device LED is grounded.

[0044] like Figure 5 As shown, in one embodiment, the pixel circuit 90 also includes a first light-emitting control transistor T3, one of the source / drain of the first light-emitting control transistor T3 is electrically connected to the other of the source 332 / drain of the compensation transistor T1, and the other of the source / drain of the first light-emitting control transistor T3 is electrically connected to the other of the source 332 / drain of the compensation transistor T1.

[0045] like Figure 4 As shown, in one embodiment, the anode of the light emitting device LED can also be electrically connected to the other of the source 332 / drain of the compensation transistor T1, and the cathode of the light emitting device LED is electrically connected to one of the source / drain of the first light emitting control transistor T3.

[0046] like Figure 5 As shown, in one embodiment, the pixel circuit 90 also includes a second light emitting control transistor T4, one of the source / drain of the second light emitting control transistor T4 is electrically connected to the other of the source / drain of the driving transistor T2, the other of the source / drain of the second light emitting control transistor T4 is electrically connected to the anode of the light emitting device LED, and the cathode of the light emitting device LED is grounded.

[0047] Among them, at least one of the gate of the first light emission control transistor T3 or the gate of the second light emission control transistor T4 can be connected to the light emission control signal EM.

[0048] In one embodiment, the positive power signal line VDDL is used to transmit the positive power signal VDD, and the positive power signal VDD has a first high potential and / or a second high potential; the high potential of the square wave signal XCK is used to turn on the N-channel transistor, and the low potential of the square wave signal XCK is used to turn on the P-channel transistor.

[0049] It can be understood that both the first high potential and the second high potential can drive the light emitting device LED to emit light.

[0050] In one embodiment, the second high potential is greater than the first high potential; when the square wave signal XCK is at a low potential, the positive power signal VDD is one of the first high potential or the second high potential; when the square wave signal XCK is at a high potential, the positive power signal VDD is the other of the first high potential or the second high potential.

[0051] It can be understood that by configuring the positive power signal VDD to have two different high potentials, when switching to the second high potential with a higher potential, the light emitting brightness of the light emitting device LED can be further improved.

[0052] In one embodiment, the working phase of the pixel circuit 90 includes a light emitting phase. In the light emitting phase, the square wave signal XCK switches between a low potential and a high potential at least once.

[0053] The working sequence of the pixel circuit 90 is as follows: Figure 6 As shown, when the light-emitting control signal EM is at a low potential, the first light-emitting control transistor T3 and / or the second light-emitting control transistor T4 are turned on. At this time, the pixel circuit 90 operates in the light-emitting phase in a frame time t1, that is, the light-emitting device LED is in a light-emitting state; the square wave signal XCK has at least one rising edge or falling edge in the light-emitting phase. Figure 4 or Figure 5 It can be seen from the waveform of the potential VDDA at point A of the pixel circuit 90 that each rising edge or falling edge of the square wave signal XCK can pull up or restore the potential at point A. It can be seen that as the number of rising edges and / or falling edges of the square wave signal XCK increases in the light-emitting stage, the light-emitting brightness of the entire display panel will be more uniform, that is, the average voltage of the positive power signal VDD supplying power to each pixel circuit 90 in one frame is closer to being equal or equal.

[0054] like Figure 7As shown, in one embodiment, a positive power signal line VDDL is electrically connected to one of the sources 332 / drains of at least two compensation transistors T1, and the other of the sources 332 / drains of each compensation transistor T1 is respectively connected to the corresponding pixel circuit 90. For example, from left to right, the other of the sources 332 / drains of the first compensation transistor T1 can be connected to the first pixel circuit 90, the other of the sources 332 / drains of the second compensation transistor T1 can be connected to the second pixel circuit 90, the other of the sources 332 / drains of the third compensation transistor T1 can be connected to the third pixel circuit 90, and the other of the sources 332 / drains of the fourth compensation transistor T1 can be connected to the fourth pixel circuit 90. It can be understood that in this way, multiple compensation transistors T1 can share the same positive power signal line VDDL, which can save the number of positive power signal lines VDDL used.

[0055] The positive power signal VDD in the positive power signal line VDDL is input to one of the source 332 / drain of at least two compensation transistors T1 .

[0056] like Figure 8 As shown, in one of the embodiments, this embodiment provides a display device, which includes the display panel of at least one of the above embodiments, the display panel includes a display area AA and a fan-out area FA adjacent to the display area AA, and the construction area TA of the compensation transistor T1 may include the display area and / or the fan-out area.

[0057] It can be understood that the display device provided in this embodiment constructs the first channel, the second channel, the gate, the source and the drain of the compensation transistor T1 in the first active layer 210, the second active layer 320, the gate layer 310 and the source-drain layer 330 in sequence, and the first channel is constructed as one of the N-type channel and the P-type channel, and the second channel is the other of the N-type channel and the P-type channel. Under the control of the rising edge and / or falling edge of the square wave signal XCK, the gate 311 of the compensation transistor T1 can pulse the DC signal connected thereto; at the same time, the compensation transistor T1 constructs the gate, the source and the drain with fewer film layers, thereby simplifying the structure and manufacturing process of the compensation transistor T1.

[0058] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0059] The display panel and the display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A first active layer, wherein the first active layer includes a first source region, a first channel region, and a first drain region of the compensation transistor; a gate layer, the gate layer comprising a gate of the compensation transistor, wherein a projection of the gate of the compensation transistor on the first active layer at least partially overlaps with the first channel region; a second active layer, wherein the second active layer comprises a second source region, a second channel region and a second drain region of the compensation transistor, wherein a projection of the second channel region on the gate layer at least partially overlaps with a gate of the compensation transistor; as well as a source-drain layer, wherein the source-drain layer includes a source of the compensation transistor and a drain of the compensation transistor, the source of the compensation transistor is electrically connected to the first source region and the second source region, and the drain of the compensation transistor is electrically connected to the first drain region and the second drain region; The first channel region is one of an N-type channel region and a P-type channel region, and the second channel region is the other of the N-type channel region and the P-type channel region.

2. The display panel according to claim 1, characterized in that: The constituent material of the N-type channel region includes oxide, and the constituent material of the P-type channel region includes low-temperature polysilicon.

3. The display panel according to claim 2, characterized in that: The display panel further includes: A positive power signal line, the positive power signal line being electrically connected to one of the source / drain of the compensation transistor; a driving signal line, the driving signal line being electrically connected to a gate of the compensation transistor, the driving signal line being used to transmit a square wave signal; and A pixel circuit is electrically connected to the other of the source and the drain of the compensation transistor.

4. The display panel according to claim 3, characterized in that: The positive power signal line is used to transmit a positive power signal, and the positive power signal has a first high potential and / or a second high potential; the high potential of the square wave signal is used to turn on an N-channel transistor, and the low potential of the square wave signal is used to turn on a P-channel transistor.

5. The display panel according to claim 4, characterized in that: The second high potential is greater than the first high potential; when the square wave signal is a low potential, the positive power supply signal is one of the first high potential or the second high potential; when the square wave signal is a high potential, the positive power supply signal is the other of the first high potential or the second high potential.

6. The display panel according to claim 3, characterized in that: The working phase of the pixel circuit includes a light emitting phase, during which the square wave signal switches between a low potential and a high potential at least once.

7. The display panel according to claim 6, characterized in that: The pixel circuit includes a driving transistor, one of a source / drain of the driving transistor is electrically connected to the other of a source / drain of the compensation transistor.

8. The display panel according to claim 7, characterized in that: The pixel circuit also includes a first light-emitting control transistor, one of the source / drain of the first light-emitting control transistor is electrically connected to the other of the source / drain of the compensation transistor, and the other of the source / drain of the first light-emitting control transistor is electrically connected to the other of the source / drain of the compensation transistor.

9. The display panel according to claim 3, characterized in that: A positive power signal line is electrically connected to at least two compensation transistors.

10. A display device, characterized in that: The display panel comprises a display panel as claimed in any one of claims 1 to 9, wherein the display panel comprises a display area and a fan-out area adjacent to the display area, and the compensation transistor is located in the display area and / or the fan-out area.

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