Depletion-mode SiC heterojunction transistor epitaxial structure and preparation method thereof

Abstract

The present invention discloses a depletion-mode SiC heterojunction transistor epitaxial structure and a preparation method thereof. The depletion-mode SiC heterojunction transistor epitaxial structure comprises, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type drift layer containing a superjunction structure, a 4H-SiC channel layer, and a 3C-SiC barrier layer. The epitaxial structure has high electron mobility and can reduce leakage channels, thereby avoiding device failure caused by large leakage current in the substrate facet growth area.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a depletion-mode SiC heterojunction transistor epitaxial structure and a preparation method thereof, and specifically relates to a depletion-mode SiC heterojunction transistor epitaxial structure containing a superjunction and a preparation method thereof. Background Art

[0002] The third generation of wide bandgap semiconductor materials represented by SiC have the characteristics of wide bandgap, high critical breakdown electric field, high thermal conductivity, high carrier saturation drift, etc., and are particularly suitable for the production of high temperature, high voltage, high frequency, high power, radiation-resistant and other semiconductor devices.

[0003] Among SiC polytypes, 3C-SiC, 4H-SiC, and 6H-SiC are the most widely used. The band gap of 3C-SiC is 2.3eV, and the band gap of 4H-SiC is as high as 3.2eV, with a band gap difference of 0.9eV. Due to the large difference in band gaps, the heterojunction device formed by 3C-SiC and 4H-SiC has great potential.

[0004] However, when a 3C-SiC / 4H-SiC heterojunction structure is applied to a field-effect transistor device, in the off state, with the device source grounded, the gate negatively charged, and the drain positively charged, the leakage path of the device bulk material primarily passes vertically through the 4H-SiC epitaxial layer and then horizontally through the interface between the 4H-SiC substrate and the 4H-SiC epitaxial buffer layer. Therefore, conventional growth of 3C-SiC / 4H-SiC heterojunction structures is based on semi-insulating substrates. However, semi-insulating SiC substrates are expensive, so using relatively inexpensive, highly doped conductive SiC substrates is the future development direction.

[0005] However, currently, highly doped conductive SiC substrates all have small facet growth and large substrate concentration non-uniformity, such as Figure 3 As shown. The small facet is the part of the growth interface parallel to the (0001) plane. Step flow growth cannot be carried out on the small facet, and the (0001) plane is also the crystal plane that is most easily nitrogen-doped, so it will appear darker in color on the substrate. The depth of the color on the substrate is mainly determined by the nitrogen content. The darker the color, the higher the nitrogen content and the lower the resistivity. Therefore, the leakage current of the 3C-SiC / 4H-SiC heterojunction device made of the epitaxial layer grown on the small facet is much greater than that of the normal crystal facet. Therefore, there is an urgent need to improve the compressive strength of the 4H-SiC epitaxial layer. Summary of the Invention

[0006] To solve the above technical problems, the present invention provides a depletion-mode SiC heterojunction transistor epitaxial structure and a preparation method thereof. The epitaxial structure has high electron mobility and can reduce leakage channels, thereby avoiding device failure caused by large leakage current in the small growth area of ​​the substrate.

[0007] The technical solution adopted by the present invention is as follows:

[0008] A depletion-mode SiC heterojunction transistor epitaxial structure comprises, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type drift layer containing a superjunction structure, a 4H-SiC channel layer, and a 3C-SiC barrier layer.

[0009] The substrate layer is a positive-axis N-type SiC substrate layer.

[0010] The thickness of the N-type drift layer containing the super junction structure is 5 to 50 μm.

[0011] In the N-type drift layer including the super junction structure, the super junction structure is arranged vertically downward along the surface of the N-type drift layer.

[0012] The super junction structure has a depth of 10 to 40 μm.

[0013] The thickness of the N-type highly doped 4H-SiC buffer layer is 0.5 to 1 μm, and the N doping concentration is 5×10 17 cm -3 ~2×10 18 cm -3 .

[0014] The thickness of the 4H-SiC channel layer is 1-2 μm.

[0015] The thickness of the 3C-SiC barrier layer is 5-10 μm.

[0016] The present invention also provides a method for preparing the depletion-mode SiC heterojunction transistor epitaxial structure, the method comprising the following steps:

[0017] (1) in-situ etching of the SiC substrate to obtain a SiC substrate layer;

[0018] (2) growing an N-type highly doped 4H-SiC buffer layer on the SiC substrate layer;

[0019] (3) growing an N-type 4H-SiC drift layer on the N-type highly doped 4H-SiC buffer layer;

[0020] (4) etching a trench downward from the surface of the N-type 4H-SiC drift layer;

[0021] (5) Filling the trench with P-type 4H-SiC;

[0022] (6) polishing, removing the epitaxial layer that has grown excessively on the top of the mesa during the filling process, until a smooth N-type drift layer with a superjunction structure is obtained;

[0023] (6) growing a 4H-SiC channel layer on the N-type drift layer containing the superjunction structure;

[0024] (7) A 3C-SiC barrier layer is grown on the 4H-SiC channel layer.

[0025] In step (4), the groove sidewall has an inclination angle of 90°, and the bottom width is consistent with the top width of the terrace, both of which are 1.5 to 2 μm.

[0026] The present invention also provides a device containing the depletion-mode SiC heterojunction transistor epitaxial structure, wherein a source electrode, a Schottky contact gate electrode, a drain electrode, and a SiN isolation layer are arranged on the 3C-SiC barrier layer of the depletion-mode SiC heterojunction high electron mobility transistor epitaxial structure; the source electrode and the drain electrode are respectively located on both sides of the Schottky contact gate electrode; a SiN isolation layer is arranged between the source electrode and the Schottky contact gate electrode; and a SiN isolation layer is arranged between the Schottky contact gate electrode and the drain electrode.

[0027] When the device is in the off state, the source terminal of the device is grounded, the gate is loaded with a negative voltage, and the drain terminal is loaded with a positive voltage, the leakage path of the device body material mainly passes vertically through the 3C-SiC barrier layer, the 4H-SiC channel layer, the N-type drift layer containing a superjunction structure, and the N-type highly doped 4H-SiC buffer layer in sequence, and then passes horizontally through the interface between the N-type SiC substrate and the N-type highly doped 4H-SiC buffer layer. The presence of the N-type drift layer containing the superjunction structure can reduce the leakage channel and avoid device failure caused by large leakage current in the small growth area of ​​the substrate.

[0028] In the N-type drift layer containing a superjunction structure in the depletion-mode SiC heterojunction transistor epitaxial structure provided by the present invention, the superjunction achieves charge compensation and serves as a voltage-withstand layer by adopting an alternating P-type doped region and N-type doped region structure. The superjunction device introduces P-type doping into a conventional N-type voltage-withstand layer, so that when the device is reverse blocking voltage, the charge depletion layer expands simultaneously in both the longitudinal and lateral directions. Since the longitudinal thickness of the voltage-withstand layer is much greater than the lateral width of the alternating P / N-type regions, the voltage-withstand layer is completely depleted due to the extension of the lateral depletion region under very low reverse voltage.

[0029] In the depletion-mode SiC heterojunction transistor epitaxial structure provided by the present invention, a superjunction structure is provided below the heterojunction structure. The superjunction serves as a high-resistance layer, which can reduce the leakage channel and avoid device failure caused by large leakage current in the growth area of ​​the small surface of the substrate.

[0030] Compared with the prior art, the present invention also has the following beneficial effects:

[0031] 1. The present invention adopts a 3C / 4H-SiC heterojunction structure in the epitaxial structure of a depletion-mode SiC heterojunction transistor. The 3C / 4H-SiC heterojunction is a heterojunction composed of the same elemental material but different crystal forms. This novel heterojunction structure can easily avoid the interface state problem that is difficult to solve in the heterojunction structure formed by the traditional AlGaN / GaN. The interface state is mainly caused by lattice mismatch. For most different crystal forms of the same material, the lattice mismatch between the (111) plane of the cubic crystal form and the (0001) plane of the hexagonal crystal form is negligible. Therefore, the depletion-mode SiC heterojunction transistor epitaxial structure provided by the present invention has high electron mobility.

[0032] 2. In the epitaxial structure of a depletion-mode SiC heterojunction transistor, the present invention selects a positive-axis N-type SiC carbon-surface substrate as the SiC substrate layer, which is cheaper than a semi-insulating substrate. An N-type highly doped 4H-SiC buffer layer is provided on the positive-axis N-type SiC carbon-surface substrate to buffer the mismatch stress generated by the concentration difference between the substrate and the drift layer. An N-type drift layer containing a superjunction structure is provided on the N-type highly doped 4H-SiC buffer layer to block reverse breakdown and serve as a voltage-resistant layer. A 4H-SiC channel layer provided thereon serves as an intrinsic SiC layer to reduce the effects of interface roughness scattering and defect scattering. A 3C-SiC barrier layer provides carriers. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A structural diagram of the epitaxial structure of a depletion-mode SiC heterojunction transistor;

[0034] Figure 2 Schematic diagram of the leakage channel when the depletion-mode SiC heterojunction transistor epitaxial structure is applied to field-effect transistor devices;

[0035] Figure 3 Schematic diagram of facet growth of highly doped conductive SiC substrate;

[0036] In the figure, 1-SiC substrate layer, 2-N-type highly doped 4H-SiC buffer layer, 3-N-type drift layer with super junction structure, 4-4H-SiC channel layer, 5-3C-SiC barrier layer, 6-source, 7-drain, 8-Schottky contact gate, 9-SiN isolation layer. DETAILED DESCRIPTION

[0037] A depletion-mode SiC heterojunction high electron mobility transistor epitaxial structure comprises, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type drift layer containing a super junction structure, a 4H-SiC channel layer, and a 3C-SiC barrier layer.

[0038] The method for preparing the depletion-mode SiC heterojunction high electron mobility transistor epitaxial structure comprises the following steps:

[0039] 1) In-situ etching of SiC substrate: Select a positive axis N-type SiC carbon surface substrate, introduce H2 at a flow rate of 160-240 slm and HCl at a flow rate of 30-100 sccm, and etch at a pressure of 50-200 mbar and a temperature of 1450-1500°C for 10-30 minutes;

[0040] 2) Growth of N-type highly doped 4H-SiC buffer layer: Stop the HCl flow and introduce carrier gas H2, chlorine-containing silicon source gas, carbon source and N2 at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm and 40-100 sccm, respectively. Grow a 0.5-1 μm thick N-type highly doped 4H-SiC buffer layer at a temperature of 1580-1700°C and a pressure of 50-200 mbar. The doping concentration is 5×10 17 cm -3 ~2×10 18 cm -3 ;

[0041] 3) Growth of N-type 4H-SiC drift layer: H2 carrier gas, chlorine-containing silicon source gas, carbon source gas, and N2 were introduced at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm, and 10-50 sccm, respectively, at a temperature of 1580-1700°C and a pressure of 50-200 mbar to grow a 5-50 μm thick N-type 4H-SiC epitaxial layer with a doping concentration of 1×10 14 cm -3 ~2×10 16 cm -3 ;

[0042] 4) Remove and clean; perform trench etching on the N-type 4H-SiC drift layer grown on the substrate, etching to a depth of 10 to 40 μm along the <11-20> crystal direction, with a trench sidewall angle of 90° and a bottom width consistent with the top width of the mesa, both 1.5 to 2 μm. After etching, remove the mask; clean again, dry, and place in an epitaxial furnace;

[0043] 5) Filling the etched trenches with P-type 4H-SiC by introducing a chlorine-containing silicon source gas, a carbon source, HCl, and an Al dopant at flow rates of 100-500 sccm, 100-500 sccm, 1000-5000 sccm, and 20-100 sccm, respectively, and introducing a carrier gas H2 at 150-300 slm, controlling Cl / Si=20-50, at a temperature of 1580-1750°C and a pressure of 100-600 mbar, until the trenches are completely filled;

[0044] 6) Polishing: Chemical mechanical polishing is performed using a standard process to remove the overgrown P-type 4H-SiC on the top of the mesa, resulting in a smooth upper surface with alternating p-type and n-type regions;

[0045] 7) Growth of 4H-SiC channel layer: The epitaxial growth furnace was placed again, and a carrier gas H2, a chlorine-containing silicon source gas, and a carbon source were introduced at flow rates of 160-240 slm, 80-500 sccm, and 80-500 sccm, respectively, at a temperature of 1580-1650°C and a pressure of 50-200 mbar to grow a 1-2 μm thick 4H-SiC channel layer;

[0046] 8) 3C-SiC barrier layer growth: H2, silicon source, carbon source, and N2 are introduced at flow rates of 160-240 slm, 100-500 sccm, 100-500 sccm, and 15-50 sccm, respectively, at a temperature of 1400-1500°C and a pressure of 200-500 mbar to grow a 5-10 μm thick 3C-SiC barrier layer;

[0047] 9) Cool down to room temperature under H2 protection.

[0048] In the above steps, the chlorine-containing silicon source gas is SiCl4, SiHCl3, SiH2C12 or SiH3Cl.

[0049] The present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0050] Example 1

[0051] A depletion-mode SiC heterojunction high electron mobility transistor epitaxial structure comprises, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type drift layer containing a superjunction structure, a 4H-SiC channel layer, and a 3C-SiC barrier layer.

[0052] The method for preparing the depletion-mode SiC heterojunction high electron mobility transistor epitaxial structure comprises the following steps:

[0053] 1) In-situ etching of SiC substrates: A positive-axis N-type SiC carbon-surface substrate was selected, and H2 and HCl were introduced at a flow rate of 196 slm and 40 sccm, respectively, at a pressure of 100 mbar and a temperature of 1500°C for 10 min.

[0054] 2) Growth of N-type highly doped 4H-SiC buffer layer: Stop the HCl flow and introduce H2 carrier gas, chlorine-containing silicon source gas, carbon source, and N2 at flow rates of 196 slm, 340 sccm, 380 sccm, and 40 sccm, respectively. Grow a 1 μm thick N-type highly doped 4H-SiC buffer layer at 1600°C and 100 mbar. The doping concentration is 1×10 18 cm -3 ;

[0055] 3) Growth of N-type 4H-SiC drift layer: H2 carrier gas, chlorine-containing silicon source gas, carbon source, and N2 were introduced at flow rates of 196 slm, 320 sccm, 380 sccm, and 10 sccm, respectively, at 1600°C and 100 mbar to grow a 50 μm thick N-type 4H-SiC barrier layer with a doping concentration of 5×10 15 cm -3 ;

[0056] 4) Remove and clean; perform trench etching on the N-type 4H-SiC drift layer grown on the substrate, etching to a depth of 40 μm along the <11-20> crystal direction, with a trench sidewall inclination angle of 90°, and the bottom width consistent with the top width of the mesa, both of which are 2 μm. After etching, remove the mask; clean again, dry, and send to the epitaxial furnace;

[0057] 5) Filling the etched trenches with P-type 4H-SiC by introducing a chlorine-containing silicon source gas, a carbon source, HCl, and an Al dopant at flow rates of 100 sccm, 110 sccm, 3000 sccm, and 30 sccm, respectively, and introducing H2 carrier gas at 196 slm, controlling the Cl / Si ratio to 30, at a temperature of 1750°C and a pressure of 300 mbar until the trenches were completely filled;

[0058] 6) Polishing: Chemical mechanical polishing is performed using a standard process to remove the overgrown P-type 4H-SiC on the top of the mesa, resulting in a smooth upper surface with alternating p-type and n-type regions;

[0059] 7) Growth of 4H-SiC Channel Layer: The substrate was placed in the epitaxial furnace again, and a carrier gas of H2, a chlorine-containing silicon source gas, and a carbon source were introduced at flow rates of 196 slm, 200 sccm, and 220 sccm, respectively, at a temperature of 1650°C and a pressure of 80 mbar to grow a 1 μm thick 4H-SiC channel layer.

[0060] 8) 3C-SiC barrier layer growth: H2, silicon source, carbon source, and N2 were introduced at flow rates of 196 slm, 200 sccm, 220 sccm, and 23 sccm, respectively, at a temperature of 1400°C and a pressure of 300 mbar to grow a 10 μm thick 3C-SiC barrier layer;

[0061] 9) Cool down to room temperature under H2 protection.

[0062] In the above steps, the chlorine-containing silicon source gas is SiCl4, SiHCl3, SiH2C12 or SiH3Cl.

[0063] Example 2

[0064] A field effect transistor device is provided, wherein a source electrode, a Schottky contact gate electrode, a drain electrode, and a SiN isolation layer are arranged on a 3C-SiC barrier layer of the depletion-mode SiC heterojunction high electron mobility transistor epitaxial structure in Example 1; the source electrode and the drain electrode are respectively located on either side of the Schottky contact gate electrode; a SiN isolation layer is arranged between the source electrode and the Schottky contact gate electrode; and a SiN isolation layer is arranged between the Schottky contact gate electrode and the drain electrode.

[0065] Comparative Example 1

[0066] A SiC heterojunction transistor epitaxial structure comprises, from bottom to top, a semi-insulating 4H-SiC substrate, a 4H-SiC channel layer, and an N-type 3C-SiC barrier layer.

[0067] The method for preparing the SiC heterojunction transistor epitaxial structure comprises the following steps:

[0068] 1) In-situ etching of a semi-insulating 4H-SiC substrate: A positive-axis N-type SiC carbon-surface substrate was selected, and H2 and HCl were introduced at a flow rate of 196 sccm and 40 sccm, respectively, at a pressure of 100 mbar and a temperature of 1500°C for 10 min.

[0069] 2) Growth of a 4H-SiC channel layer: A 5 μm thick N-type 4H-SiC channel layer was grown at 1600°C and 100 mbar by introducing a carrier gas of H2, a chlorine-containing silicon source gas, and a carbon source at flow rates of 196 slm, 340 scc, and 380 sccm, respectively.

[0070] 3) Growth of an N-type 3C-SiC barrier layer: H2, silicon source, carbon source, and N2 were introduced at flow rates of 196 slm, 200 sccm, 220 sccm, and 23 sccm, respectively, at 1400°C and 300 mbar to grow a 10 μm thick 3C-SiC barrier layer.

[0071] 4) Cool down to room temperature under H2 protection.

[0072] The performance data of the transistor epitaxial structures in Example 1 and the comparative example are shown in Table 1.

[0073] Table 1

[0074] Extension Source Migration Surface electron density Square resistance Example 1 2265.73 <![CDATA[9.56×10 12 ]]> 312.67 Comparative Example 2066.41 <![CDATA[7.73×10 12 ]]> 357.12

[0075] The yields of the transistor epitaxial structures in Example 1 and Comparative Example 1 are shown in Table 2.

[0076] Table 2

[0077] Extension Source Comprehensive yield VF yield BVR yield IR yield Example 1 96.39％ 100％ 97.50％ 98.87％ Comparative Example 66.27％ 100％ 94％ 68.14％

[0078] The detailed description of the depletion-mode SiC heterojunction transistor epitaxial structure and the preparation method thereof with reference to the above-mentioned embodiments is illustrative rather than restrictive. Several embodiments can be listed according to the limited scope. Therefore, changes and modifications without departing from the overall concept of the present invention should fall within the scope of protection of the present invention.

Claims

1. A depletion-mode SiC heterojunction transistor epitaxial structure, characterized in that: The depletion-mode SiC heterojunction transistor epitaxial structure includes, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type drift layer with a superjunction structure, a 4H-SiC channel layer, and a 3C-SiC barrier layer. The substrate layer is a positive axis N-type SiC substrate layer, the thickness of the N-type highly doped 4H-SiC buffer layer is 0.5 to 1 μm, and the N doping concentration is 5×10 17 cm -3 ~2×10 18 cm -3 .

2. The depletion-mode SiC heterojunction transistor epitaxial structure according to claim 1, wherein: The thickness of the N-type drift layer containing the super junction structure is 5 to 50 μm.

3. The depletion-mode SiC heterojunction transistor epitaxial structure according to claim 1 or 2, characterized in that: In the N-type drift layer including the super junction structure, the super junction structure is arranged vertically downward along the surface of the N-type drift layer.

4. The depletion-mode SiC heterojunction transistor epitaxial structure according to claim 1 or 2, characterized in that: The super junction structure has a depth of 10 to 40 μm.

5. The depletion-mode SiC heterojunction transistor epitaxial structure according to claim 1, wherein: The thickness of the 4H-SiC channel layer is 1-2 μm.

6. The depletion-mode SiC heterojunction transistor epitaxial structure according to claim 1, wherein: The thickness of the 3C-SiC barrier layer is 5-10 μm.

7. The method for preparing a depletion-mode SiC heterojunction transistor epitaxial structure according to any one of claims 1 to 6, wherein: The preparation method comprises the following steps: (1) in-situ etching of the SiC substrate to obtain a SiC substrate layer; (2) growing an N-type highly doped 4H-SiC buffer layer on the SiC substrate layer; (3) growing an N-type 4H-SiC drift layer on the N-type highly doped 4H-SiC buffer layer; (4) etching a trench downward from the surface of the N-type 4H-SiC drift layer; (5) Filling the trench with P-type 4H-SiC; (6) polishing, removing the epitaxial layer that has grown excessively on the top of the mesa during the filling process, until a smooth N-type drift layer with a superjunction structure is obtained; (6) growing a 4H-SiC channel layer on the N-type drift layer containing the superjunction structure; (7) A 3C-SiC barrier layer is grown on the 4H-SiC channel layer.

8. The preparation method according to claim 7, characterized in that In step (4), the groove sidewall has an inclination angle of 90°, and the bottom width is consistent with the top width of the terrace, both of which are 1.5 to 2 μm.

9. A device comprising the depletion-mode SiC heterojunction transistor epitaxial structure according to any one of claims 1 to 6.

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