Neuromorphic internal calculation device based on double-layer ferroelectric heterojunction and regulation and control method

Abstract

The invention discloses a neural morphological memory calculation device based on a double-layer ferroelectric heterojunction. The neural morphological memory calculation device comprises a substrate, a bottom electrode layer, a ferroelectric dielectric layer, a ferroelectric semimetal layer and a top electrode layer which are arranged in sequence, the bottom electrode layer and the ferroelectric dielectric layer form a first contact surface; the ferroelectric semimetal layer and the ferroelectric dielectric layer form a second contact surface; and the top electrode layer and the ferroelectric semimetal layer form a third contact surface. The invention further discloses a regulation and control method of the neural morphology in-memory calculation device based on the double-layer ferroelectric heterojunction, according to the neural morphology in-memory calculation device based on the double-layer ferroelectric heterojunction and the method provided by the invention, the ferroelectric polarization overturning dynamics of the device is regulated and controlled by utilizing the interfacial effects of the first contact surface, the second contact surface and the third contact surface, so that the neural morphology in-memory calculation device based on the double-layer ferroelectric heterojunction is obtained. And the non-volatile conductance state of the device is regulated and controlled, and finally, the functions of storage and neural morphology calculation are realized in the device at the same time.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of ferroelectric electron device, and particularly relates to a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction, and a method for regulating the neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction. BACKGROUND

[0002] Traditional ferroelectric random access memory (FeRAM) uses ferroelectric capacitors to realize storage function, and is widely studied based on its advantages of non-volatility, high stability and fast reading and writing. However, since the data reading is performed by recording the current when the ferroelectric polarization flips, the process needs to re-write data and is considered as "destructive" reading, which affects the service life of the device. Meanwhile, when the lateral size of the ferroelectric capacitor is reduced to the nanometer level, the stored charge is too low to be detected. A new type of ferroelectric memory based on ferroelectric tunnel junction (FTJ) can overcome the above problems. FTJ performs non-destructive and low-power data reading by detecting different orders of magnitude of tunneling current generated when the ferroelectric polarization orientation is different. At the same time, since the quantum tunneling effect occurs only when the size of the ferroelectric film between the two electrodes is at the nanometer level, the size of FTJ is also conducive to the integration of the memory, and it is expected to become a new generation of memory with high density, low power consumption and fast reading and writing.

[0003] In addition, the data processing of modern computers adopts the von Neumann architecture with separated storage units and processor units. The difference in access speed between operation and storage of the architecture limits the speed of processor operation, and the back-and-forth transmission of data between the storage unit and the processor unit also generates a large amount of energy consumption, which is difficult to meet the requirements of low power consumption and interconnection of all things in the future. Therefore, the neural network computing (brain-like computing) architecture that directly performs calculation in the storage module (in-memory computing) by simulating the working mode of the biological brain is one of the effective means to break through the "von Neumann bottleneck" and effectively solve the energy consumption problem and improve the computing ability of the traditional computer. In neural network computing, artificial synapse devices reflect the signal transmission weight between front and rear neurons, which directly affects the computing speed, accuracy and energy consumption of the neural network chip, and is a key factor to realize high-performance neural network computing.

[0004] The artificial synapse device based on the ferroelectric heterojunction relies on the polarization flip dynamics of the ferroelectric domain, has low power consumption and can continuously regulate the conductance, and thus realizes the in-memory computing function with high energy efficiency. However, since factors such as strain (including lattice distortion), interface doping, interface defects, interface adsorption of polar molecules, electrode effect, ferroelectric domain morphology, and lattice quality have important influence on the polarization flip dynamics of the ferroelectric domain, how to regulate the polarization flip dynamics of the ferroelectric domain to realize high linearity, high symmetry, high dynamic range, and multiple conductance state number of synaptic plasticity is a key problem to be solved for the current ferroelectric synapse device. SUMMARY

[0005] The first object of the present application is to provide a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction, to regulate the ferroelectric polarization flipping dynamics of the device by the interface effect of the first contact surface, the second contact surface and the third contact surface, and to regulate the non-volatile conductive state of the device, and finally to realize the functions of storage and neuromorphic computing in the device.

[0006] The second object of the present application is to provide a regulation method of a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction.

[0007] The first technical solution adopted by the present application is a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction, which comprises a substrate, a bottom electrode layer, a ferroelectric dielectric layer, a ferroelectric semimetal layer and a top electrode layer arranged in sequence. The bottom electrode layer and the ferroelectric dielectric layer form a first contact surface; the ferroelectric semimetal layer and the ferroelectric dielectric layer form a second contact surface; and the top electrode layer and the ferroelectric semimetal layer form a third contact surface.

[0008] The first technical solution of the present application is also characterized in that, The thickness of the ferroelectric dielectric layer is 0.1 nm-100 nm.

[0009] The material of the ferroelectric dielectric layer is PMN-PT ((1-x)[PbMg 1 / 3 Nb 2 / 3 O3]-x[PbTiO3] ), PZN-PT ((1-x)Pb(Zn 1 / 3 Nb 2 / 3 )O3]-x[PbTiO3] ), PSN-PT (Pb(Sc 1 / 2 Nb 1 / 2 )-PbTiO3 ), Pb(In 1 / 2 Nb 1 / 2 )-PbTiO3, Pb(Yb 1 / 2 Nb 1 / 2 )-PbTiO3, BaTiO3, BiFeO3, PbTiO3, SrTiO3, LiNbO3, LiTaO3, HfO2, ZrO2, Hf (1-x) Zr x O2, SiC, GaN, KNbO3, KH2PO4, Pb(Zr 1-x Ti x )O3, LiOsO3, CaTiO3, KTiO3, Ba x Sr 1-x TiO3 (BST ), (Pb,La)TiO3 (PLT ), LaTiO3, (BiLa)4Ti3O 12 (BLT ), SrRuO3, BaHfO3, La1-x Sr x MnO3, BaMnF4, BaNiF4, BaMgF4, BaCuF4, BaZnF4, BaCoF4, BaFeF4, BaMnF4, BiN, ZnO, Ba2PbCl4, PVDF, P(VDF-TrFE), C 13 H 14 ClN5O2Cd, TiO2.

[0010] ferroelectric semimetal layer material is any one or more of a-In2Se3, b'-In2Se3, CuInP2S6, AgBiP2Se6, CuInP2Se6, MoS2, MoTe2, WS2, WSe2, WTe2, SnTe, SnSe, SnS, GeSe, GeS, GeTe, GaAs, P2O3, SiGe, SiTe, SiSn, GeSn, b-GeSe, PbTe, MoSe, GaTeCl, MAPbI3, MAPbBr3, Cu2O, SeO3, Sc2CO2, CrN, CrB2, g-C6N8H, and graphene, germanene, stanene, disulfide modified with a polar chemical group -CH2F, -CHO, -COOH, or -CONH2.

[0011] the material of the bottom electrode layer and the top electrode layer is graphene, graphite, carbon nanotube, carbonyl compound, conductive polymer, Pt, Au, Ag, Pd, Cu, Fe, Ni, Pb, Pt-Rh, Pt-Au, TiO2, SnO2, ZnO, CuO, Cu2O, Fe2O3, Fe3O4, MnO2, Co3O4, NiO, RuO2, IrO2, PbO2, WO3, MoO3, V2O5, Nb2O5, Al2O3, In2O3, Ga2O3, In2O3 SnO2 (ITO), ZnO:Al (AZO), ZnO:Ga (GZO), InGaZnO4 (IGZO), LiCoO2, LiMn2O4, LiFePO4, LiNi x Co_yMn_zO2 (NCM), LiNi x Co_yAl_zO2 (NCA), Li4Ti5O 12 (LTO), SnO, SnO2, Co3O4, Mn3O4, ZnCo2O4, CoFe2O4, SrRuO3 (SRO), La 1₋x Sr x MnO3 (LSMO), LaNiO3 (LNO), Nb:SrTiO3 (Nb:STO), La 1₋ xSr x CoO3 (LSCO), La 1₋x Ca x MnO3 (LCMO), SrVO3 (SVO), VO2.

[0012] The second technical solution adopted by the present application is that data writing is realized by applying an excitation voltage to the first contact surface or the third contact surface; and data reading is realized by applying a detection voltage to the first contact surface or the third contact surface.

[0013] The second technical solution of the present application is further characterized in that, Specifically, the excitation voltage and the detection voltage applied to the first contact surface are as follows: the excitation voltage is applied to the first contact surface of the bottom electrode layer to flow through the ferroelectric dielectric layer and the ferroelectric half-metallic layer, and the top electrode is grounded, so as to realize data writing; and the detection voltage is applied to the first contact surface of the bottom electrode layer, and the top electrode layer is grounded, so as to realize data reading. Specifically, the excitation voltage and the detection voltage applied to the third contact surface are as follows: Specifically, the excitation voltage and the detection voltage applied to the third contact surface are as follows: The excitation voltage changes the ferroelectric polarization orientation, and the detection voltage is smaller than the excitation voltage and cannot change the polarization orientation; the excitation voltage controls the polarization orientation of the ferroelectric dielectric layer, and controls the polarization orientation of the ferroelectric half-metallic layer in combination with the polarization flipping dynamics characteristics of the ferroelectric dielectric layer; When the excitation voltage is a single pulse voltage, the dual-bit storage of data "0" and "1" is realized; When the excitation voltage is a series of pulse voltage sequences, multi-state storage with multiple non-volatile conductive states is realized; When the excitation voltage pulse sequence first forms a conductive state gradually increasing and then forms a conductive state gradually decreasing, the neuromorphic computing function of enhancing synaptic plasticity and weakening synaptic plasticity is realized.

[0014] Compared with the prior art, the present application has the following beneficial effects: (1) The neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction provided by the application, according to the device structure, the interface effect generated by the second contact surface formed by the contact of the ferroelectric semimetal layer and the ferroelectric dielectric layer is the main factor for regulating the ferroelectric polarization flip dynamics, the band matching at the interface will form a contact built-in electric field regulator for the carrier transport characteristics of the device, and the ferroelectric dielectric layer with a lower coercive field will first form a polarization electric field to regulate the interface carrier distribution, when the excitation voltage is further increased, the ferroelectric semimetal layer with a higher coercive field will also form another gradually increasing polarization electric field to regulate the carrier state density / interface barrier of the second contact surface, and finally under the regulation of the two polarization electric fields, a high on-off ratio and multiple linearly changing nonvolatile conductance states are formed, realizing the high-performance in-memory computing function.

[0015] (2) The neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction provided by the application, similar to the conventional metal (semimetal) / ferroelectric dielectric heterojunction structure, the band matching (work function difference) at the first contact surface formed by the bottom electrode and the ferroelectric dielectric layer and the third contact surface formed by the ferroelectric semimetal layer and the top electrode will also affect the conductance state on-off ratio of the entire device. However, due to the sufficient carriers in the metal (semimetal), it is difficult to realize high linearity and high symmetry nonvolatile conductance state changes through interface regulation, therefore, the application constructs a ferroelectric semimetal / ferroelectric dielectric heterojunction structure, first regulates the distribution of a large number of carriers in the ferroelectric semimetal layer at the interface by means of the polarization electric field of the ferroelectric dielectric layer, then realizes high symmetry and high linearity nonvolatile conductance state regulation by means of the gradually changing polarization electric field in the ferroelectric semimetal layer regulated by the excitation voltage, and finally realizes high on-off ratio nonvolatile storage and high-precision neuromorphic computing function by means of the polarization electric fields of the two ferroelectric layers, the rich carriers in the ferroelectric semimetal layer, and the band arrangement at the contact interface, thereby developing a high-performance in-memory computing device. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of the neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction of the application.

[0017] Figure 2 It is a schematic diagram of the regulation method of the neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction in Example 6 of the application.

[0018] Figure 3 It is a schematic diagram of the regulation method of the neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction in Example 7 of the application.

[0019] Figure 4 It is a polarization flip characteristic test diagram of the ferroelectric dielectric layer of the neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction of the application.

[0020] Figure 5 This is a test diagram of the polarization reversal characteristics of the ferroelectric semi-metal layer of the neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction of the present invention.

[0021] Figure 6 This is a test diagram of the two-state storage switching ratio of the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction of the present invention.

[0022] Figure 7 This is a voltage sequence diagram for testing the multi-state storage switching ratio of the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to the present invention.

[0023] Figure 8 This is a test diagram of the multi-state storage switching ratio of the neuromorphic in-memory computing device based on the double-layer ferroelectric heterojunction of the present invention. Figure 9 This is a test diagram of the polymorphic storage non-volatile memory of the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction of the present invention.

[0024] Figure 10 This is a multi-cycle long-term synaptic plasticity test diagram of the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction of the present invention.

[0025] Figure 11 Schematic diagram of the artificial neural network structure of the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction of the present invention.

[0026] Figure 12 This is a diagram showing the artificial neural network training recognition rate of the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to the present invention. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments described are only some embodiments of the present invention, not all embodiments.

[0028] Example 1 The present invention provides a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction, such as Figure 1 As shown, it includes a substrate 1, a bottom electrode layer 2, a ferroelectric dielectric layer 3, a ferroelectric semi-metal layer 4 and a top electrode layer 5 arranged in sequence; The bottom electrode layer 2 and the ferroelectric dielectric layer 3 form a first contact surface; the ferroelectric semi-metal layer 4 and the ferroelectric dielectric layer 3 form a second contact surface; and the top electrode layer 5 and the ferroelectric semi-metal layer 4 form a third contact surface.

[0029] Among them, the ferroelectric dielectric layer and the ferroelectric semimetal layer have different ferroelectric polarization reversal dynamic characteristics.

[0030] Example 2 In the present embodiment, the ferroelectric dielectric layer 3 has a thickness of 0.1 nm to 100 nm, and the ferroelectric dielectric layer 3 material is PMN-PT ((1-x)[PbMg 1 / 3 Nb 2 / 3 O3]-x[PbTiO3], PZN-PT ((1-x)Pb(Zn 1 / 3 Nb 2 / 3 )O3]-x[PbTiO3], PSN-PT (Pb(Sc 1 / 2 Nb 1 / 2 )-PbTiO3], Pb(In 1 / 2 Nb 1 / 2 )-PbTiO3, Pb(Yb 1 / 2 Nb 1 / 2 )-PbTiO3, BaTiO3, BiFeO3, PbTiO3, SrTiO3, LiNbO3, LiTaO3, HfO2, ZrO2, Hf (1-x) Zr x O2, SiC, GaN, KNbO3, KH2PO4, Pb(Zr 1- x Ti x )O3, LiOsO3, CaTiO3, KTiO3, Ba x Sr 1-x TiO3 (BST), (Pb, La)TiO3 (PLT), LaTiO3, (BiLa)4Ti3O 12 (BLT), SrRuO3, BaHfO3, La 1-x Sr x MnO3, BaMnF4, BaNiF4, BaMgF4, BaCuF4, BaZnF4, BaCoF4, BaFeF4, BaMnF4, BiN, ZnO, Ba2PbCl4, PVDF, P(VDF-TrFE), C 13 H 14 ClN5O2Cd, TiO2, or any one or more of the foregoing.

[0031] Example 3 In this embodiment, the material of the ferroelectric semi-metal layer 4 is any one or more of α-In2Se3, β'-In2Se3, CuInP2S6, AgBiP2Se6, CuInP2Se6, MoS2, MoTe2, WS2, WSe2, WTe2, SnTe, SnSe, SnS, GeSe, GeS, GeTe, GaAs, P2O3, SiGe, SiTe, SiSn, GeSn, β-GeSe, PbTe, MoSe, GaTeCl, MAPbI3, MAPbBr3, Cu2O, SeO3, Sc2CO2, CrN, CrB2, g-C6N8H, and graphene, germanene, stanene, and disulfide modified with polar chemical groups -CH2F, -CHO, -COOH or -CONH2.

[0032] Example 4 In this embodiment, the materials of the bottom electrode layer 2 and the top electrode layer 5 are graphene, graphite, carbon nanotubes, carbonyl compounds, conductive polymers, Pt, Au, Ag, Pd, Cu, Fe, Ni, Pb, Pt-Rh, Pt-Au, TiO2, SnO2, ZnO, CuO, Cu2O, Fe2O3, Fe3O4, MnO2, Co3O4, NiO, RuO2, IrO2, PbO2, WO3, MoO3, V2O5, Nb2O5, Al2O3, In2O3, Ga2O3, In2O3·SnO2 (ITO), ZnO:Al (AZO), ZnO:Ga (GZO), InGaZnO4 (IGZO), LiCoO2, LiMn2O4, LiFePO4, LiNi x Co_yMn_zO2 (NCM), LiNi x Co_yAl_zO2 (NCA), Li4Ti5O 12 (LTO), SnO, SnO2, Co3O4, Mn3O4, ZnCo2O4, CoFe2O4, SrRuO3 (SRO), La 1₋x Sr x MnO3 (LSMO), LaNiO3 (LNO), Nb:SrTiO3 (Nb:STO), La 1₋x Sr x CoO3 (LSCO), La 1₋x Ca x Any one or more of MnO3 (LCMO), SrVO3 (SVO), and VO2.

[0033] Example 5 This embodiment provides a control method for a neuromorphic in-memory computer based on a double-layer ferroelectric heterojunction. Using the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction provided in the above embodiment, the specific steps are: data writing is achieved by applying an excitation voltage to the first contact surface or the third contact surface; and data reading is achieved by applying a detection voltage to the first contact surface or the third contact surface.

[0034] Example 6 On the basis of Example 5, the excitation voltage and the detection voltage are applied to the first contact surface as follows: the excitation voltage flowing through the ferroelectric dielectric layer 3 and the ferroelectric semi-metal layer 4 is applied to the first contact surface of the bottom electrode layer 2 and the top electrode is grounded to achieve data writing; and the detection voltage is applied to the first contact surface of the bottom electrode layer 2 and the top electrode layer 5 is grounded to achieve data reading; More specifically, if Figure 2 As shown, the excitation voltage Bias 1 flowing through the ferroelectric dielectric layer 3 and the ferroelectric semi-metal layer 4 is applied to the bottom electrode 2 through the first contact surface and the top electrode 5 is grounded. FE1 is the ferroelectric dielectric layer 3, E p1 The ferroelectric polarization electric field formed by it, FE2 is the ferroelectric semi-metal layer 4, E p2 The coercive electric field required for the polarization reversal of FE1 is smaller than that of FE2. When the applied Bias 1 is a positive bias voltage V that can reverse the polarization orientation of FE1 to the upward state, + When the coercive electric field of FE2 is larger, the ferroelectric polarization of FE2 is not completely reversed, and it mainly shows semi-metallic characteristics. Therefore, the electrons in the FE2 layer are p1 Under the action of the second contact surface to stabilize the polarization orientation of FE1, E p1 Larger and pointing upward, E p2 The second contact surface gathers a small amount of electrons. When the positive bias voltage of Bias 1 is increased (V ++ ) is greater than the coercive electric field required for the polarization reversal of FE2, the polarization orientation of FE1 is more stably maintained in the upward state under sufficient screening charge, and FE2 is also reversed and maintained in the downward state under the action of a larger excitation voltage, showing both semi-metallic and ferroelectric polarization characteristics, E p1 and E p2 Together they attract a large number of electrons to gather at the second contact surface. At this time, E p1 Larger and pointing upward, E p2 Increases and points downward, and a large number of electrons gather on the second contact surface. Similarly, when the applied Bias 1 is a negative bias voltage V that can flip the polarization orientation of FE1 to the downward state, - When the coercive electric field of FE2 is larger, the ferroelectric polarization of FE2 is not completely reversed, and it mainly shows semi-metallic characteristics. Therefore, the holes in the FE2 layer arep1 Under the action of the second contact surface to stabilize the polarization orientation of FE1, E p1 Larger and pointing downward, E p2 Small and upward, a small amount of holes are gathered on the second contact surface. When the negative bias voltage of Bias 1 is increased (V - - ) is greater than the coercive electric field required for the polarization reversal of FE2, the polarization orientation of FE1 is more stably maintained in the downward state under sufficient screening charge, and FE2 is also reversed and maintained in the upward state under the action of a larger excitation voltage, showing both semi-metallic and ferroelectric polarization characteristics, E p1 and E p2 Together they attract a large number of holes to gather at the second contact surface. At this time, E p1 Larger and pointing downward, E p2 The second contact surface is enlarged and directed upward, and a large number of cavities are gathered.

[0035] Depend on Figure 2 It can be seen that the excitation voltage first flips and stabilizes the ferroelectric polarization orientation of the FE1 layer, forming a stable polarization field that regulates the carrier distribution at the second contact interface. Furthermore, as the excitation voltage increases, the polarization orientation of the FE2 layer gradually flips and stabilizes, forming a gradually increasing ferroelectric polarization field and a gradually increasing carrier concentration at the second contact interface. This allows the device's interface barrier height to be gradually controlled, resulting in multiple linearly varying nonvolatile conduction states. In addition to the ferroelectric polarization fields of FE1 and FE2, the band structures of FE1 and FE2 and the built-in electric field at the second contact interface, resulting from their different work functions, also regulate the interface carrier distribution and barrier height. Together, these three factors determine the interface barrier height at the second contact interface. Furthermore, the band matching between the first contact interface and the third release interface also influences the device's total barrier height and its storage-on / off ratio under different polarization orientations.

[0036] Example 7 In this embodiment, the excitation voltage and the detection voltage are applied to the third contact surface, specifically: the excitation voltage flowing through the ferroelectric semi-metal layer 4 and the ferroelectric dielectric layer 3 is applied to the third contact surface of the top electrode 5 and the bottom electrode layer 2 is grounded, so as to achieve data writing; and the detection voltage is applied to the third contact surface of the top electrode layer 5 and the bottom electrode layer 2 is grounded, so as to achieve data reading.

[0037] More specifically, if Figure 3 As shown, the top electrode 5 is applied with an excitation voltage Bias 2 flowing through the ferroelectric semi-metal layer 4 and the ferroelectric dielectric layer 3 through the third contact surface and the bottom electrode 2 is grounded. FE1 is the ferroelectric dielectric layer 3, and E p1 The ferroelectric polarization electric field formed by it, FE2 is the ferroelectric semi-metal layer 4, E p2The coercive electric field required for the polarization reversal of FE1 is smaller than that of FE2. When the applied Bias 2 is a positive bias voltage V that can reverse the polarization orientation of FE1 to the downward state, + When the excitation voltage is directly applied to the upper surface of FE2, the ferroelectric polarization of FE2 is not completely reversed due to the larger coercive electric field of FE2. The polarization orientation of FE1 is reversed to the downward state. At this time, E p1 Larger, E p2 The positive bias voltage of Bias 1 (V ++ ) is greater than the coercive electric field required for the polarization reversal of FE2, the polarization orientation of FE2 is reversed and stably maintained in the downward state, and a large number of electrons are gathered on the second contact surface to stabilize the polarization orientation of FE2. The screening charges gathered on the second contact surface reverse the polarization orientation of FE1 to the upward state. At this time, E p1 Larger and pointing upward, E p2 Increases and points downward, and a large number of electrons gather on the second contact surface. Similarly, when the applied Bias2 is a negative bias voltage V that can flip the polarization orientation of FE1 to the downward state, - When the coercive electric field of FE2 is larger, the ferroelectric polarization of FE2 is not completely reversed, so the electrons in the FE2 layer are p1 Under the action of the second contact surface to stabilize the polarization orientation of FE1, E p1 Larger, E p2 The electrons in the FE2 layer gather at the second contact surface to stabilize the polarization orientation of FE1. When the negative bias voltage of Bias 2 is increased (V - - ) is greater than the coercive electric field required for the polarization reversal of FE2, the polarization orientation of FE2 is reversed and maintained in the upward state, and a large number of holes are gathered on the second contact surface to stabilize the polarization orientation of FE2. The screening charges gathered on the second contact surface reverse the polarization orientation of FE1 to the downward state. At this time, E p1 Larger and pointing downward, E p2 Increases and points upward, and a large number of holes gather on the second contact surface. Figure 3 The polarization orientation of FE1 and FE2 when the data is written is shown in FIG. Figure 2 Although different, they can both achieve the gradual regulation of the interface carrier distribution and the interface barrier height at the second contact surface.

[0038] Example 8 This embodiment provides a test of the polarization reversal characteristics of the ferroelectric dielectric layer of a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction. Figure 4As shown, after applying positive and negative bias voltage greater than coercive voltage on the top surface of ferroelectric semimetal layer and grounding the bottom electrode, the polarization orientation of ferroelectric semimetal layer can be completely flipped to downward and upward, and the written domain can be stably saved. Through the hysteresis loop test, it can be seen that the positive and negative coercive voltage of polarization flip of ferroelectric semimetal layer is about +3 V and -1 V, which produces a larger imprint, and the polarization response under positive bias is slightly stronger than that under negative bias, and the coercive potential of polarization flip of ferroelectric semimetal layer is greater than that of ferroelectric dielectric layer.

[0039] Example 9 This embodiment provides the polarization flip characteristics test of ferroelectric semimetal layer of neuromorphic in-memory computing device based on double-layer ferroelectric heterojunction, as shown in Figure 5 As shown, after applying positive and negative bias voltage greater than coercive voltage on the top surface of ferroelectric semimetal layer and grounding the bottom electrode, the polarization orientation of ferroelectric semimetal layer can be completely flipped to downward and upward, and the written domain can be stably saved. Through the hysteresis loop test, it can be seen that the positive and negative coercive voltage of polarization flip of ferroelectric semimetal layer is about +3 V and -1 V, which produces a larger imprint, and the polarization response under positive bias is slightly stronger than that under negative bias, and the coercive potential of polarization flip of ferroelectric semimetal layer is greater than that of ferroelectric dielectric layer.

[0040] Example 10 This embodiment provides the bistable storage on-off ratio test of neuromorphic in-memory computing device based on double-layer ferroelectric heterojunction, as shown in Figure 6 As shown, the on-off ratio is measured by the data reading process after writing data. The test result adopts the method provided in Example 6, so the polarization orientation of ferroelectric dielectric layer is preferentially regulated. The polarization flip characteristics of ferroelectric dielectric layer and ferroelectric semimetal layer are respectively shown in Figure 4 and Figure 5 As shown, it can be seen that the polarization flip characteristics of ferroelectric dielectric layer are symmetrical, and the coercive voltage is smaller than that of ferroelectric semimetal layer; since the applied voltage is applied from the top surface during the hysteresis loop test, but the applied voltage is applied from the bottom electrode during the on-off ratio test, the ferroelectric polarization of ferroelectric semimetal layer is more prone to flip when the positive bias is applied to the bottom electrode, and it is more difficult to flip when the negative bias is applied. Although not shown, the specific writing process is to flip the polarization orientation of ferroelectric dielectric layer to upward (P + ) by applying a positive excitation voltage (V up ) greater than the coercive voltage of ferroelectric polarization to the bottom electrode layer, since the polarization orientation of ferroelectric semimetal layer is prone to flip under positive bias, it is also in the upward state, and finally the data "0" is written; the polarization orientation of ferroelectric dielectric layer is flipped to downward (P down ) by applying a negative excitation voltage greater than the coercive voltage of ferroelectric polarization to the bottom electrode layer, since the polarization orientation of ferroelectric semimetal layer is more difficult to flip under negative bias, a larger amplitude of excitation voltage (V - -) flip up to the final write data "1". The data read process after writing is completed is as follows: after writing data, a detection voltage with a voltage amplitude much smaller than the coercive voltage is applied for data reading. It can be seen that after writing data "0", the polarization of the ferroelectric dielectric layer is flipped up to the upward (P up ) state, at this time, the total ferroelectric polarization electric field generated by the ferroelectric dielectric layer and the ferroelectric semimetal layer at the second contact surface is consistent with the direction of the interface contact electric field generated by the band matching, the interface barrier increases, which is manifested as a low conductive state; when writing data "1", the total polarization electric field at the second contact surface is opposite to the contact electric field, the interface barrier decreases, which is manifested as a high conductive state, and the on-off ratio of the conductive state reaches 10 4 .

[0041] Example 11 This embodiment provides a multi-state storage on-off ratio test of a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction, as shown in Figure 7 The excitation voltage pulse sequence is as follows: a gradually increasing negative excitation voltage is applied to the ferroelectric dielectric layer until the polarization is completely flipped down to the downward (P down ) state, then the negative excitation voltage is reduced to zero, and the conductive state generated by the residual polarization is observed, then a gradually increasing positive excitation voltage is applied to the ferroelectric dielectric layer until the polarization is completely flipped up to the upward (P up ) state, then the negative excitation voltage is reduced to zero, and the conductive state generated by the residual polarization at this time is observed. The multi-state storage on-off ratio test is a data read process after the ferroelectric polarization is gradually flipped by applying the excitation voltage pulse sequence, as shown in Figure 8 , after applying the excitation voltage to flip the polarization orientation, a detection voltage with a small pulse amplitude is applied to complete data reading. It can be seen that the on-off ratio of the non-volatile multi-state storage is about 7x10 3 .

[0042] Example 12 This embodiment provides a multi-state storage stability test of a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction. As shown in Figure 9 It can be seen that the non-volatile conductive state in Figure 9 gradually decreases with the increase of the amplitude of the positive excitation voltage, which indicates that the polarization orientation of the ferroelectric dielectric layer is gradually flipped up to the upward state, showing a low conductive state, and remains stable after completing data writing, verifying the non-volatility of the multi-state storage of the device.

[0043] Example 13 This embodiment provides a long-term synaptic plasticity test of a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction. As shown in Figure 10As shown, it can be seen that after a voltage pulse sequence capable of gradually flipping the ferroelectric polarization orientation is applied to the device, the polarization orientation will be gradually flipped to the downward and upward states in turn, multiple gradually increasing and gradually decreasing nonvolatile conductance platforms appear, showing long-term enhancement / attenuation synaptic plasticity, and the synaptic characteristics have high linearity, high symmetry, and excellent cycle stability.

[0044] Embodiment 14 The present embodiment provides a neural network training precision test diagram of a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction. As shown, Figure 11 As shown, the artificial neural network using the in-memory computing device of the present application as the artificial neural network synaptic matrix is composed of three layers, 784 input neurons, 100 hidden neurons, and 10 output neurons, and the neural network is trained using the back propagation method. As shown, Figure 12 As shown, based on the artificial neural network, the digital recognition function is trained, and after four training iterations, the recognition accuracy is higher than 90%, and is stable at 94.68% recognition accuracy, close to the ideal recognition accuracy 95.20% of the neural network realized by software, which shows that using the synaptic plasticity characteristics of the device as the weight matrix can realize excellent neuromorphic computing function.

[0045] Based on the above structural design and the beneficial effects produced, the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction provided by the present application utilizes the interface effect of the first contact surface, the second contact surface, and the third contact surface to control the ferroelectric polarization flipping dynamics of the device, especially the interface band matching, the ferroelectric half-metal layer polarization electric field, and the ferroelectric dielectric layer polarization electric field jointly control the distribution of the carriers in the second contact surface and the interface potential barrier in the ferroelectric half-metal layer, finally forming a nonvolatile conductance state with high switching ratio and multiple linear change platforms, realizing high-performance neuromorphic in-memory computing function.

Claims

1. A neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction, characterized in that: It comprises a substrate (1), a bottom electrode layer (2), a ferroelectric dielectric layer (3), a ferroelectric semimetal layer (4) and a top electrode layer (5) which are arranged in sequence; The bottom electrode layer (2) and the ferroelectric dielectric layer (3) form a first contact surface; the ferroelectric semimetal layer (4) and the ferroelectric dielectric layer (3) form a second contact surface; and the top electrode layer (5) and the ferroelectric semimetal layer (4) form a third contact surface.

2. The neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to claim 1, characterized in that: The thickness of the ferroelectric dielectric layer (3) is 0.1 nm-100 nm.

3. The neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to claim 1, characterized in that: The material of the ferroelectric dielectric layer (3) is PMN-PT ((1-x) [PbMg 1 / 3 Nb 2 / 3 O3]-x[PbTiO3]), PZN-PT ((1-x)Pb(Zn 1 / 3 Nb 2 / 3 )O3]-x[PbTiO3]), PSN-PT (Pb(Sc 1 / 2 Nb 1 / 2 )-PbTiO3)、Pb(In 1 / 2 Nb 1 / 2 )-PbTiO3, Pb(Yb 1 / 2 Nb 1 / 2 )-PbTiO3, BaTiO3, BiFeO3, PbTiO3, SrTiO3, LiNbO3, LiTaO3, HfO2, ZrO2, Hf (1-x) Zr x O2, SiC, GaN, KNbO3, KH2PO4, Pb(Zr 1-x Ti x )O3, LiOsO3, CaTiO3, KTiO3, Ba x Sr 1-x TiO3 (BST), (Pb,La)TiO3 (PLT), LaTiO3, (BiLa)4Ti3O 12 (BLT), SrRuO3, BaHfO3, La 1-x Sr x MnO3, BaMnF4, BaNiF4, BaMgF4, BaCuF4, BaZnF4, BaCoF4, BaFeF4, BaMnF4, BiN, ZnO, Ba2PbCl4, PVDF, P(VDF-TrFE), C 13 H 14 Any one or more of ClN5O2Cd, TiO2.

4. The neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to claim 1, characterized in that: The thickness of the ferroelectric semi-metal layer (4) is 0.1 nm-100 nm.

5. The neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to claim 1, characterized in that: The material of the ferroelectric semimetal layer (4) is any one or more of α-In2Se3, β'-In2Se3, CuInP2S6, AgBiP2Se6, CuInP2Se6, MoS2, MoTe2, WS2, WSe2, WTe2, SnTe, SnSe, SnS, GeSe, GeS, GeTe, GaAs, P2O3, SiGe, SiTe, SiSn, GeSn, β-GeSe, PbTe, MoSe, GaTeCl, MAPbI3, MAPbBr3, Cu2O, SeO3, Sc2CO2, CrN, CrB2, g-C6N8H, and graphene, germanene, stanene, and disulfide modified with polar chemical groups -CH2F, -CHO, -COOH or -CONH2.

6. The neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to claim 1, characterized in that: The materials of the bottom electrode layer (2) and the top electrode layer (5) are graphene, graphite, carbon nanotubes, carbonyl compounds, conductive polymers, Pt, Au, Ag, Pd, Cu, Fe, Ni, Pb, Pt-Rh, Pt-Au, TiO2, SnO2, ZnO, CuO, Cu2O, Fe2O3, Fe3O4, MnO2, Co3O4, NiO, RuO2, IrO2, PbO2, WO3, MoO3, V2O5, Nb2O5, Al2O3, In2O3, Ga2O3, In2O3·SnO2 (ITO), ZnO:Al (AZO), ZnO:Ga (GZO), InGaZnO4 (IGZO), LiCoO2, LiMn2O4, LiFePO4, LiNi x Co_yMn_zO2 (NCM), LiNi x Co_yAl_zO2 (NCA), Li4Ti5O 12 (LTO), SnO, SnO2, Co3O4, Mn3O4, ZnCo2O4, CoFe2O4, SrRuO3 (SRO), La 1₋x Sr x MnO3 (LSMO), LaNiO3 (LNO), Nb:SrTiO3 (Nb:STO), La 1₋ x SrxCoO3 (LSCO), La 1₋x Ca x Any one or more of MnO3 (LCMO), SrVO3 (SVO), and VO2.

7. A control method for a neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction, characterized in that: The neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction as described in any one of claims 1 to 6 is used, and the specific steps are: data writing is achieved by applying an excitation voltage to the first contact surface or the third contact surface; and data reading is achieved by applying a detection voltage to the first contact surface or the third contact surface.

8. The control method of the neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to claim 7, characterized in that: The method comprises applying an excitation voltage and a detection voltage to the first contact surface, specifically: applying an excitation voltage flowing through the ferroelectric dielectric layer (3) and the ferroelectric semimetal layer (4) to the first contact surface of the bottom electrode layer (2) and grounding the top electrode to achieve data writing; and applying a detection voltage to the first contact surface of the bottom electrode layer (2) and grounding the top electrode layer (5) to achieve data reading; By applying the excitation voltage and the detection voltage to the third contact surface, specifically: Data writing is achieved by applying an excitation voltage flowing through the ferroelectric semimetal layer (4) and the ferroelectric dielectric layer (3) to the third contact surface of the top electrode (5) and grounding the bottom electrode layer (2); and data reading is achieved by applying a detection voltage to the third contact surface of the top electrode layer (5) and grounding the bottom electrode layer (2).

9. The neuromorphic in-memory computing device based on a double-layer ferroelectric heterojunction according to claim 8, characterized in that: The excitation voltage changes the ferroelectric polarization orientation, and the detection voltage is less than the excitation voltage and cannot change the polarization orientation; the excitation voltage regulates the polarization orientation of the ferroelectric dielectric layer (3), and regulates the polarization orientation of the ferroelectric semi-metal layer (4) in combination with the polarization reversal dynamics characteristics of the ferroelectric dielectric layer (3); When the excitation voltage is a single pulse voltage, dual-bit storage of data "0" and "1" is achieved; When the excitation voltage is a series of pulse voltage sequences, multi-state storage with multiple non-volatile conduction states is achieved; When the excitation voltage pulse sequence first forms a gradually increasing conductance state and then forms a gradually decreasing conductance state, a neuromorphic computing function of enhancing synaptic plasticity and weakening synaptic plasticity is achieved.

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