Intrinsic state current control circuit of flash FPGA

Abstract

The present invention discloses an eigenstate current control circuit for a flash-type FPGA, relating to the field of flash-type FPGAs. The eigenstate current control circuit comprises a conduction switch tube and a switch tube control logic designed using the intrinsic weak conduction state of a p_flash switch unit. The conduction switch tube is connected between a core ground and a chip ground of the flash-type FPGA. During the first power-on process of the flash-type FPGA, the switch tube control logic outputs an invalid level under the action of residual charge inside the p_flash switch unit to turn off the conduction switch tube, thereby placing the core ground in a floating state and preventing a large current from being generated from the core power supply to the core ground.

Description

Technical Field

[0001] The present invention relates to the field of flash type FPGA, in particular to an eigenstate current control circuit of the flash type FPGA. Background Art

[0002] Flash FPGAs utilize a programmable routing matrix composed of flash cells to select different signal paths to implement user logic functions. Because flash cells are non-volatile memory, information is not lost after a power outage. Therefore, flash FPGAs offer fast startup times, enabling circuits to quickly enter operational mode upon power-up. They are widely used in signal processing and control.

[0003] However, during the manufacturing process of flash FPGA chips, a small amount of electrons will be introduced into the floating gate of the flash cell. The internal residual charge e will cause the P-type flash cell to be in an intrinsic weak conduction state, and there will be a uA-level conduction current between the source and drain of each flash cell. Figure 1 In the circuit shown in the figure, due to the conduction current between the source and drain of cell1 and cell2, a conduction path I is formed as shown by the dotted line. leakage Flash FPGAs have several megabytes or even tens of megabytes of flash cells. The combined conduction currents between the source and drain of such a large number of flash cells result in a very large current when the flash FPGA chip is first powered on. Assuming a flash FPGA with a system equivalent gate count of 3 million, the current will exceed 10A. Solving this problem is one of the key core technologies in designing flash FPGA chips and is a prerequisite for testing and evaluation of flash FPGA chips after tape-out. Summary of the Invention

[0004] In response to the above problems and technical requirements, the inventors have proposed an eigenstate current control circuit for a flash FPGA. The technical solution of the present invention is as follows:

[0005] A flash-type FPGA intrinsic current control circuit includes a conducting switch and switch control logic. The conducting switch is connected to a path between a core power supply and a chip ground of the flash-type FPGA. The chip ground is a ground pin of the flash-type FPGA.

[0006] The switch control logic connects and controls the on and off of the conduction switch. The switch control logic is built based on the p_flash switch unit. During the first power-on process of the flash type FPGA, the switch control logic, under the action of the internal residual charge of the p_flash switch unit, outputs an invalid level to turn off the conduction switch, thereby disconnecting the path between the core power supply and the chip ground, and completing the first power-on of the flash type FPGA.

[0007] Its further technical solution is that the conduction switch tube is implemented by an NMOS tube, and the conduction switch tube is connected between the core ground and the chip ground of the flash type FPGA. The core ground is the ground potential of the core logic of the flash type FPGA. The drain of the conduction switch tube is connected to the core ground, the source is connected to the chip ground, and the gate is connected to the switch tube control logic. Under the action of the internal residual charge of the p_flash switch unit, the switch tube control logic outputs a low level to turn off the conduction switch tube.

[0008] Its further technical solution is that the switch tube control logic includes several parallel p_flash switch units, the source of each p_flash switch unit is connected to the output end of the switch tube control logic, the drain of each p_flash switch unit is connected to the chip ground GND, and the gate of each p_flash switch unit is connected to the chip ground GND through the pull-down resistor R0; the p_flash switch unit in the switch tube control logic pulls down the output end of the switch tube control logic to an output low level under the action of internal residual charge.

[0009] Its further technical solution is that after the flash type FPGA is successfully powered on for the first time and completes the erase operation, it outputs an erase signal of a valid level to the switch tube control logic. The switch tube control logic erases the p_flash switch unit inside the switch tube control logic according to the erase signal of the valid level, so that all p_flash switch units inside the switch tube control logic are turned off.

[0010] Its further technical solution is that, in the switch tube control logic, the input end of the positive high-voltage inverter I9 obtains the erase signal, the output end is connected to the gate of the PMOS tube MP0, the source of MP0 obtains the positive high voltage HV, and the drain is connected to the source of each p_flash switch unit; the input end of the negative high-voltage buffer I10 obtains the erase signal, the output end is connected to the gate of the NMOS tube MN1, the drain of MN1 obtains the negative high voltage LV, and the source is connected to the gate of each p_flash switch unit;

[0011] The erase signal is valid at a high level. Under the action of the high-level erase signal, MP0 and MN1 are both turned on, and a positive high voltage is applied to the drain of all p_flash switch units in the switch tube control logic, and a negative high voltage is applied to the gate of all p_flash switch units in the switch tube control logic, completing the erase operation of all p_flash switch units inside the switch tube control logic.

[0012] Its further technical solution is that when the flash type FPGA completes the erase operation and is powered on again, the switch tube control logic outputs a high level to turn on the switch tube, so that the core ground and the chip ground are connected to provide a ground potential for the core logic.

[0013] A further technical solution is that the switch tube control logic also includes a PMOS tube MP1, the source of MP1 is connected to the core power supply VDD, the drain and gate of MP1 are connected to the source of each p_flash switch unit, MP1 is an inverse ratio tube and uses a diode connection to form a pull-up resistor; when the flash type FPGA completes the erase operation and is powered on again, MP1 pulls up the output end of the switch tube control logic to an output high level to turn on the switch tube, so that the core ground and the chip ground are connected to provide a ground potential for the core logic.

[0014] Its further technical solution is that the flash type FPGA includes several groups of core grounds and chip grounds, and the intrinsic current control circuit includes several conduction switch tubes, each of which is connected between a group of core grounds and chip grounds, and each conduction switch tube is controlled by the switch tube control logic.

[0015] Its further technical solution is that the flash type FPGA includes an external ground ring surrounding the chip and an internal ground ring surrounding the core logic. The core ground connected to each conductive switch tube is evenly distributed on the internal ground ring, and the chip ground connected to each conductive switch tube is evenly distributed on the external ground ring.

[0016] A further technical solution is that the eigenstate current control circuit also includes several buffers, the output end of the switch tube control logic is cascaded to each buffer in sequence, and the output end of each buffer is connected to and controls the on and off of a conductive switch tube.

[0017] The beneficial technical effects of the present invention are:

[0018] This application discloses an eigenstate current control circuit for a flash-type FPGA. This circuit utilizes the intrinsic weak conduction state of the p_flash switch unit to design switch control logic to control the on / off of the conduction switch. This circuit closes the path between the core logic's core ground L_GND and the chip ground GND formed by the chip's ground pins when the flash-type FPGA is first powered on after leaving the factory, preventing the generation of large currents from the core power supply VDD to the core ground L_GND. Furthermore, the use of NMOS transistors to implement the conduction switch enhances the circuit's reliability.

[0019] In addition, after erasing the entire flash cell used as a wiring switch in the flash FPGA, it is placed in a closed state. At the same time, the p_flash switch unit in the switch tube control logic is erased, and the function of controlling the conduction switch tube is disabled. That is, the function of closing the path between the core ground L_GND and the chip ground GND is disabled. Then, during the subsequent power-on process of the flash FPGA, the path between the core ground L_GND and the chip ground GND is opened and no large current will exist. The corresponding EDA software of the flash FPGA can program the user's code points into the flash cell storage array in the flash FPGA, thereby realizing the user's function. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the conduction path formed due to the intrinsic weak conduction state of the P-type flash cell.

[0021] Figure 2 This is an implementation structure diagram of the eigenstate current control circuit.

[0022] Figure 3 This is another implementation structure diagram of the eigenstate current control circuit.

[0023] Figure 4 This is another implementation structure diagram of the eigenstate current control circuit.

[0024] Figure 5 is used Figure 2 、 Figure 3 、 Figure 4 Schematic comparison diagram of current and voltage when the structure is .

[0025] Figure 6 In one embodiment, based on Figure 2 The circuit structure diagram of the implementation structure shown.

[0026] Figure 7 FIG. 4 is a circuit diagram of the switch control logic in an embodiment. DETAILED DESCRIPTION

[0027] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0028] This application discloses an eigenstate current control circuit for a flash-type FPGA. The eigenstate current control circuit includes a conducting switch and switch control logic. The conducting switch is connected to the path between the flash-type FPGA's core power supply VDD and the chip ground GND. The chip ground GND is the flash-type FPGA's ground pin. The specific internal logic structure is set according to actual conditions and is not described in detail in this application. The switch control logic connects to and controls the on and off of the conducting switch. The switch control logic is constructed based on the p_flash switch unit. The p_flash switch unit within the switch control logic also has a small amount of electrons introduced to the floating gate during the chip manufacturing process, resulting in internal residual charge. During the first power-up of the flash-type FPGA, the switch control logic, under the influence of the internal residual charge of the p_flash switch unit, outputs an inactive level to turn off the conducting switch, thus disconnecting the path between the core power supply VDD and the chip ground GND. This prevents the core logic's core power supply VDD from generating a large current to the chip ground GND, thus completing the first power-up of the flash-type FPGA.

[0029] This application provides three connection methods for the conduction switch tube:

[0030] (1) The conduction switch tube K is implemented by an NMOS tube independent of the core logic, and the conduction switch tube is connected between the core ground L_GND of the flash type FPGA and the chip ground GND. Please refer to Figure 2 Core ground is the ground potential of the core logic in flash FPGAs. The core logic is powered by the core power supply VDD and the core ground L_GND. The drain of the on-state switch is connected to the core ground L_GND, the source is connected to the chip ground GND, and the gate is connected to the switch control logic. The switch control logic, influenced by the residual charge within the p_flash switch cell, outputs a low level, turning off the on-state switch.

[0031] (2) The on-state switch tube K is implemented using a PMOS tube independent of the core logic, and the on-state switch tube is connected between the core power supply VDD of the flash type FPGA and the logic working power supply L_VDD. The logic working power supply L_VDD is the power supply potential of the core logic of the flash type FPGA. Please refer to Figure 3 At this time, the core logic is powered by the logic operating power supply L_VDD and the chip ground GND. The source of the conduction switch is connected to the core power supply VDD, the drain is connected to the logic operating power supply L_VDD, and the gate is connected to the switch control logic. In response to the residual charge within the p_flash switch unit, the switch control logic outputs a high level, turning off the conduction switch.

[0032] (3) The conduction switch K is implemented by the flash switch unit in the core logic. Please refer to Figure 4 At this point, the core logic is powered by the core power supply VDD and the chip ground GND. The gate of the flash switch unit, implemented as the on-state switch tube K, is connected to the switch tube control logic. In response to the residual charge within the p_flash switch unit, the switch tube control logic outputs a high-level positive voltage, turning off the on-state switch tube.

[0033] In the above three cases, the present application uses an NMOS tube connected between the core ground L_GND and the chip ground GND to form a conductive switch tube K. During the first power-on process of the flash type FPGA, the switch tube control logic outputs a low level to turn off the conductive switch tube. Figure 3 or Figure 4 If the structure is realized, the switch control logic needs to output a high level to turn off the switch. Due to the competition between voltage and current during the power-on process, such as Figure 5 As shown, in use Figure 2 When the structure is realized, the current-voltage curve is as follows Figure 6 As shown in the solid line, 1.5V is the operating voltage, and the Figure 3 or Figure 4 When the structure is realized, the current-voltage curve may be as follows Figure 6 As shown by the dotted line, it is possible that high voltage cannot be applied, resulting in power-on failure. Therefore, this application adopts Figure 2 This structure, compared to Figure 3 and Figure 4 In terms of structure, reliability is higher.

[0034] based on Figure 2 The connection mode of the conducting switch tube shown in FIG. 1 is as follows: Figure 6 Optionally, the flash type FPGA includes several sets of core ground L_GND and chip ground GND, and the eigenstate current control circuit includes several conducting switch tubes, such as Figure 5 The chip comprises eight conducting switches, M0 to M7, each connected between a core ground and a chip ground. Each conducting switch M0 to M7 is controlled by the switch control logic.

[0035] In one embodiment, a flash FPGA includes an external ground ring surrounding the chip and an internal ground ring surrounding the core logic. All core grounds (L_GND) are located at several equal-level points on the internal ground ring, and all chip grounds (GND) are located at several equal-level points on the external ground ring. Optionally, the core grounds (L_GND) connected to each on-state switch are evenly distributed on the internal ground ring, and the chip grounds (GND) connected to each on-state switch are evenly distributed on the external ground ring.

[0036] In one embodiment, the eigenstate current control circuit further includes a plurality of buffers, such as Figure 6 It includes buffers I0~I7, and the output end of the switch tube control logic is cascaded with each buffer in sequence. The output end of each buffer is connected to and controls the on and off of a conductive switch tube, that is, connected to the gate of a conductive switch tube to achieve driving.

[0037] Please refer to Figure 7 The circuit diagram of the switch tube control logic shown is based on the use of the switch tube as shown in the figure. Figure 2 In the illustrated implementation, the switch control logic includes several parallel p_flash switch units, designated P0 through P7. The sources of each p_flash switch unit are connected to the output of the switch control logic and, in practice, to the output PEN of the switch control logic via buffer I8. The drains of each p_flash switch unit are connected to the chip ground GND. The gates of each p_flash switch unit are connected to the chip ground GND via pull-down resistor R0. The p_flash switch units in the switch control logic are in an intrinsic weak conduction state due to residual charge within them, thereby pulling the output PEN of the switch control logic down to a low output level. The low PEN output turns off the NMOS transistor, leaving the core ground L_GND floating, thus preventing the generation of high currents when the flash FPGA chip is first powered on after leaving the factory.

[0038] After the flash FPGA successfully powers up for the first time, it erases all flash switch cells used as wiring switches. After the erase operation is complete, it outputs an active erase signal, ERASE, to the switch control logic. The switch control logic erases the p_flash switch cells within the switch control logic in response to the active erase signal, turning off all p_flash switch cells within the switch control logic. This disables the switch control logic's ability to turn off the conductive switches. This allows the conductive switches to be turned on during the subsequent flash FPGA power-up, eliminating the need for high current flow.

[0039] Then Figure 7As shown, in the switch control logic, the input of the positive high-voltage inverter I9 receives the erase signal ERASE, and the output is connected to the gate of the PMOS transistor MP0. The source of MP0 receives the positive high voltage HV, and the drain is connected to the source of each p_flash switch unit. The input of the negative high-voltage buffer I10 receives the erase signal, and the output is connected to the gate of the NMOS transistor MN1. The drain of MN1 receives the negative high voltage LV, and the source is connected to the gate of each p_flash switch unit. The erase signal ERASE is active high. Under the action of the high erase signal ERASE, both MP0 and MN1 are turned on, and the positive high voltage HV is applied to the drains of all p_flash switch units in the switch control logic, while the negative high voltage LV is applied to the gates of all p_flash switch units in the switch control logic, completing the erase operation of all p_flash switch units within the switch control logic.

[0040] Furthermore, when the flash FPGA is powered on again after completing the erase operation, the switch control logic outputs a high level to turn on the switch, so that the core ground L_GND and the chip ground GND are connected to provide a ground potential for the core logic, and the core logic can work normally. Figure 4 As shown, the switch control logic also includes a PMOS transistor MP1. MP1's source is connected to the core power supply VDD, and its drain and gate are connected to the sources of each p_flash switch unit. MP1 is an inverse ratio transistor and uses a diode connection to form a pull-up resistor. When the flash FPGA completes an erase operation and is powered on again, MP1 pulls the output terminal PEN of the switch control logic to a high level, turning on the switch. This connects the core ground L_GND to the chip ground VDD, providing ground potential for the core logic.

[0041] The above description is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. An eigenstate current control circuit for a flash FPGA, characterized in that: The eigenstate current control circuit includes a conducting switch tube and a switch tube control logic, wherein the conducting switch tube is connected to a path between a core power supply of the flash type FPGA and a chip ground, and the chip ground is a ground pin of the flash type FPGA; The switch tube control logic is connected to and controls the on and off of the conduction switch tube. The switch tube control logic is constructed based on the p_flash switch unit. During the first power-on process of the flash type FPGA, the switch tube control logic outputs an invalid level under the action of the internal residual charge of the p_flash switch unit to turn off the conduction switch tube, thereby disconnecting the path between the core power supply and the chip ground, and completing the first power-on of the flash type FPGA.

2. The eigenstate current control circuit according to claim 1, characterized in that: The conduction switch tube is implemented using an NMOS tube, and the conduction switch tube is connected between the core ground and the chip ground of the flash type FPGA. The core ground is the ground potential of the core logic of the flash type FPGA. The drain of the conduction switch tube is connected to the core ground, the source is connected to the chip ground, and the gate is connected to the switch tube control logic. Under the action of the internal residual charge of the p_flash switch unit, the switch tube control logic outputs a low level to turn off the conduction switch tube.

3. The eigenstate current control circuit according to claim 2, characterized in that: The switch tube control logic includes several parallel p_flash switch units, the sources of each p_flash switch unit are connected to the output end of the switch tube control logic, the drains of each p_flash switch unit are connected to the chip ground GND, and the gates of each p_flash switch unit are connected to the chip ground GND through the pull-down resistor R0; the p_flash switch units in the switch tube control logic pull down the output end of the switch tube control logic to an output low level under the action of internal residual charge.

4. The eigenstate current control circuit according to claim 3, characterized in that: After the flash-type FPGA is successfully powered on for the first time and the erase operation is completed, an erase signal of a valid level is output to the switch tube control logic. The switch tube control logic erases the p_flash switch unit inside the switch tube control logic according to the erase signal of the valid level, so that all p_flash switch units inside the switch tube control logic are turned off.

5. The eigenstate current control circuit according to claim 4, characterized in that: In the switch control logic, the input end of the positive high-voltage inverter I9 obtains the erase signal, the output end is connected to the gate of the PMOS tube MP0, the source of MP0 obtains the positive high voltage HV, and the drain is connected to the source of each p_flash switch unit; the input end of the negative high-voltage buffer I10 obtains the erase signal, the output end is connected to the gate of the NMOS tube MN1, the drain of MN1 obtains the negative high voltage LV, and the source is connected to the gate of each p_flash switch unit; The erase signal is valid at a high level. Under the action of the high-level erase signal, MP0 and MN1 are both turned on, a positive high voltage is applied to the drain of all p_flash switch units in the switch tube control logic, and a negative high voltage is applied to the gate of all p_flash switch units in the switch tube control logic, completing the erase operation of all p_flash switch units inside the switch tube control logic.

6. The eigenstate current control circuit according to claim 5, characterized in that: When the flash FPGA completes the erase operation and is powered on again, the switch control logic outputs a high level to turn on the conduction switch, so that the core ground and the chip ground are connected to provide a ground potential for the core logic.

7. The eigenstate current control circuit according to claim 6, characterized in that: The switch tube control logic also includes a PMOS tube MP1, the source of which is connected to the core power supply VDD, the drain and gate of which are connected and connected to the sources of each p_flash switch unit. MP1 is an inverse ratio tube and uses a diode connection to form a pull-up resistor. When the flash type FPGA completes the erase operation and is powered on again, MP1 pulls up the output end of the switch tube control logic to an output high level to turn on the conduction switch tube, so that the core ground and the chip ground are connected to provide a ground potential for the core logic.

8. The eigenstate current control circuit according to any one of claims 2 to 7, characterized in that: The flash type FPGA includes several groups of core grounds and chip grounds, and the eigenstate current control circuit includes several conductive switching tubes, each conductive switching tube is respectively connected between a group of core grounds and chip grounds, and each conductive switching tube is controlled by the switching tube control logic.

9. The eigenstate current control circuit according to claim 8, characterized in that: The flash type FPGA includes an external ground ring surrounding the chip and an internal ground ring surrounding the core logic. The core grounds connected to each conductive switch tube are evenly distributed on the internal ground ring, and the chip grounds connected to each conductive switch tube are evenly distributed on the external ground ring.

10. The eigenstate current control circuit according to claim 8, characterized in that: The eigenstate current control circuit further includes a plurality of buffers. The output end of the switch tube control logic is sequentially cascaded to each buffer, and the output end of each buffer is respectively connected to and controls the on and off of a conductive switch tube.

Images