Scanning signal driving unit and display device including the same

Abstract

The present invention relates to a scanning signal driving unit that can reduce the RC delay of a scanning control line at an ultra-high resolution such as 8K UHD and a display device including the scanning signal driving unit. The scanning signal driving unit includes: a plurality of stages for sequentially outputting scanning signals; a first clock line to which a first clock signal is applied; and a second clock line to which a second clock signal is applied, wherein each of the first clock lines includes a 1-1 metal pattern and a 1-2 metal pattern disposed on the 1-1 metal pattern, and each of the second clock lines includes a 2-1 metal pattern disposed at the same level as one of the 1-1 metal pattern and the 1-2 metal pattern.

Description

Technical Field

[0001] The present disclosure relates to a scan signal driving unit and a display device including the scan signal driving unit. Background Art

[0002] With the progress of information society, more and more demands are put forward for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. Display devices can be flat panel display devices such as liquid crystal display devices, field emission display devices, and organic light emitting display devices.

[0003] The display device includes a display panel, a scan signal driving unit, and a data driver, the display panel includes data lines, scan signal lines, and a plurality of pixels connected to the data lines and the scan signal lines, the scan signal driving unit is used to supply scan signals to the scan signal lines, and the data driver is used to supply data voltages to the data lines. The scan signal driving unit may be formed in a non-display area of ​​the display panel.

[0004] Recently, ultra-high-resolution display devices such as 8K UHD with a resolution of 7680×4320 have been developed. Due to the increase in the resolution of the display device, the scan control lines for applying the scan control signal to the scan signal driving unit are overlapped, so that the parasitic capacitance of the scan control lines may increase. Therefore, it is difficult to reduce the RC delay of the scan control lines. Summary of the invention

[0005] Technical issues

[0006] Aspects of the present disclosure provide a scan signal driving unit capable of reducing an RC delay of a scan control line at an ultra-high resolution such as 8K UHD.

[0007] Aspects of the present disclosure also provide a display device capable of reducing an RC delay of a scan control line at an ultra-high resolution such as 8K UHD.

[0008] It should be noted that aspects of the present disclosure are not limited to the above-mentioned aspects, and other unmentioned aspects of the present disclosure will be clearly understood by those skilled in the art through the following description.

[0009] Technical Solution

[0010] According to an embodiment for solving the technical problem, a scan signal driving unit includes: a plurality of stages configured to sequentially output scan signals; a first clock line to which a first clock signal is applied; and a second clock line to which a second clock signal is applied. Each of the first clock lines includes a 1-1 metal pattern and a 1-2 metal pattern disposed on the 1-1 metal pattern. Each of the second clock lines includes a 2-1 metal pattern disposed on the same layer as one of the 1-1 metal pattern and the 1-2 metal pattern.

[0011] A minimum distance between one of the plurality of stages and one of the first clock lines may be greater than a minimum distance between one of the plurality of stages and one of the second clock lines.

[0012] The scan signal driving unit may further include: a first connection line configured to connect the plurality of stages and the first clock line; and a second connection line configured to connect the plurality of stages and the second clock line.

[0013] A length of one of the first connection lines may be longer than a length of one of the second connection lines.

[0014] One of the first connection lines may overlap the 1-2 metal pattern of one of the first clock lines, and may not overlap the 1-1 metal pattern of the first clock line.

[0015] Each of the first clock lines may include a 1-3th metal pattern disposed on a 1-1th metal pattern. Each of the second clock lines may include a 2-2th metal pattern disposed on the same layer as the 1-3th metal pattern.

[0016] One of the first connection lines may overlap the 1st to 3rd metal patterns of one of the first clock lines.

[0017] The scan signal driving unit may further include a third clock line to which the third clock signal is applied. Each of the third clock lines may include a 3-1st metal pattern disposed on the same layer as the 1-1st metal pattern and a 3-2nd metal pattern disposed on the same layer as the 1-2nd metal pattern.

[0018] A minimum distance between one of the plurality of stages and one of the third clock lines may be greater than a minimum distance between one of the plurality of stages and one of the second clock lines.

[0019] The scan signal driving unit may further include a third connection line configured to connect the plurality of stages and the third clock line.

[0020] A length of one of the third connection lines may be longer than a length of the second connection line.

[0021] One of the third connection lines may overlap the 3-2 metal pattern of one of the third clock lines, and may not overlap the 3-1 metal pattern of the third clock line.

[0022] Each of the third clock lines may include a 3-3rd metal pattern disposed on a 3-1st metal pattern.

[0023] One of the third connection lines may overlap the 3-3 metal pattern of one of the third clock lines.

[0024] According to an embodiment for solving the technical problem, a display device includes: a display panel including data lines, scanning signal lines and sensing signal lines crossing the data lines, and pixels connected to the data lines, the scanning signal lines and the sensing signal lines; a data driver configured to apply a data voltage to the data lines; and a scanning signal driving unit including a plurality of stages configured to sequentially apply scanning signals to the scanning signal lines and sequentially apply sensing signals to the sensing signal lines. The scanning signal driving unit also includes: a first clock line to which a first clock signal is applied; and a second clock line to which a second clock signal is applied. Each of the first clock lines includes a 1-1 metal pattern and a 1-2 metal pattern disposed on the 1-1 metal pattern. Each of the second clock lines includes a 2-1 metal pattern disposed on the same layer as the 1-1 metal pattern and one of the 1-2 metal patterns.

[0025] Each of the pixels may include at least one thin film transistor. The thin film transistor may include: a light blocking layer; an active layer disposed on the light blocking layer and including an active region, a source region, and a drain region; a gate electrode disposed on the active layer; a source electrode disposed on the gate electrode and connected to the source region; and a drain electrode disposed on the gate electrode and connected to the drain region.

[0026] The 1-1st metal pattern may be disposed at the same layer as the gate electrode. The 1-2nd metal pattern may be disposed at the same layer as the source electrode.

[0027] The 1-1 th metal pattern may be disposed at the same layer as the gate electrode, and the 1-2 th metal pattern may be disposed between the gate electrode and the source electrode.

[0028] Each of the pixels may include at least one thin film transistor. The thin film transistor may include: a source electrode and a drain electrode; an active layer disposed on the source electrode and the drain electrode, the active layer including an active region, a source region and a drain region; and a gate electrode disposed on the active layer.

[0029] The 1-1 th metal pattern may be disposed at the same layer as the source electrode and the drain electrode, and the 1-2 th metal pattern may be disposed at the same layer as the gate electrode.

[0030] Beneficial Effects

[0031] According to the scan signal driving unit and the display device according to the embodiment, among the scan control lines, each of the carry clock line, the sense clock line, and the scan clock line is formed as a three-layer structure including three metal patterns. In addition, among the scan control lines, each of the sense control line, the control clock line, the gate-on voltage line, the first gate-off voltage line, and the second gate-off voltage line is formed as a double-layer structure including two metal patterns. As a result, the resistance value of each of the scan control lines can be reduced at ultra-high resolutions such as 8K UHD, so that the RC delay of the scan control lines can be reduced.

[0032] The advantageous effects according to the present disclosure are not limited to the above-mentioned effects, and various other advantageous effects are included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a perspective view showing a display device according to an embodiment.

[0034] Figure 2 is a plan view showing a display device according to an embodiment.

[0035] Figure 3 is a block diagram showing a display device according to an embodiment.

[0036] Figure 4 is a circuit diagram specifically showing a sub-pixel according to an embodiment.

[0037] Figure 5 An example of the driving timing of the sub-pixels in the Nth frame period and the N+1th frame period is shown.

[0038] Figure 6 is a waveform diagram showing kth to k+2th scanning signals and kth to k+2th sensing signals during an effective period of an Nth frame period.

[0039] Figure 7 is a waveform diagram showing kth to k+2th scanning signals and kth to k+2th sensing signals during a vertical blanking period of an Nth frame period.

[0040] Figure 8 An example of a scan signal driving unit according to one embodiment is shown.

[0041] Fig. 9 is a circuit diagram showing a k-th stage of a scan signal driving unit according to one embodiment.

[0042] Fig.10 It specifically shows Figure 8 An example plan view of area A.

[0043] Fig.11 It specifically shows Fig.10 An enlarged plan view of a first carry clock line and a first carry connection line.

[0044] Fig.12 It specifically shows Fig.10 An enlarged plan view of the sensing control lines and the sensing control connecting lines.

[0045] Fig.13 It specifically shows Fig.10 An enlarged plan view of a third scan clock line and a scan connection line.

[0046] Fig.14 It specifically shows Fig.10 An enlarged plan view of a third sensing clock line and a sensing connection line.

[0047] Fig.15 It specifically shows Figure 4 A cross-sectional view of an example of a sub-pixel.

[0048] Fig.16 It shows that along Fig.11 A cross-sectional view of the example taken along line II'.

[0049] Fig.17 It shows that along Fig.12 A cross-sectional view of the example taken along line II-II'.

[0050] Fig.18 It shows that along Fig.13 A cross-sectional view of the example taken along line III-III'.

[0051] Fig.19 It shows that along Fig.14 A cross-sectional view of the example taken along line IV-IV'.

[0052] Fig. 20 It shows that along Fig.11 A cross-sectional view of the example taken along line II'.

[0053] Fig.21 It shows that along Fig.12 A cross-sectional view of the example taken along line II-II'.

[0054] Fig. 22 It shows that along Fig.13 A cross-sectional view of the example taken along line III-III'.

[0055] Fig.23 It shows that along Fig.14 A cross-sectional view of the example taken along line IV-IV'.

[0056] Fig.24 It specifically shows Fig.10 An enlarged plan view of a third scan clock line and a scan connection line.

[0057] Fig.25 It specifically shows Fig.10 An enlarged plan view of a third sensing clock line and a sensing connection line.

[0058] Fig.26 It specifically shows Fig.10 An enlarged plan view of a first carry clock line and a first carry connection line.

[0059] Fig. 27 It specifically shows Fig.10 An enlarged plan view of the sensing control lines and sensing connection lines.

[0060] Fig.28 It specifically shows Fig.10 An enlarged plan view of a third scan clock line and a scan connection line.

[0061] Fig.29 It specifically shows Fig.10 An enlarged plan view of a third sensing clock line and a sensing connection line.

[0062] Fig.30 It shows in detail Figure 4 A cross-sectional view of an example of a sub-pixel.

[0063] Fig.31 It shows that along Fig.26 A cross-sectional view of the example taken along line II'.

[0064] Fig.32 It shows that along Fig. 27 A cross-sectional view of the example taken along line II-II'.

[0065] Fig.33 It shows that along Fig.28 A cross-sectional view of the example taken along line III-III'.

[0066] Fig.34 It shows that along Fig.29 A cross-sectional view of the example taken along line IV-IV'. DETAILED DESCRIPTION

[0067] The advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and the common knowledge in the technical field to which the present invention belongs is provided to fully inform the owner of the scope of the invention, and the present invention is limited only by the scope of the claims.

[0068] Reference to an element or layer "on" another element or layer includes any intermediate layers or other elements directly on or between the other element or layer. The same reference numerals refer to the same elements throughout. The shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings used to explain the embodiments are exemplary, and therefore the present invention is not limited to what is shown.

[0069] Although first, second, etc. are used to describe various elements, these elements are certainly not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, it goes without saying that within the spirit of the present invention, the first component mentioned below can be the second component.

[0070] Each feature of the various embodiments of the present invention may be combined partially or entirely or in combination with each other, various interlocks and drives are technically possible, and each of the embodiments may be implemented independently relative to each other or together in a related relationship.

[0071] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0072] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 is a plan view showing a display device according to an embodiment. Figure 3 is a block diagram showing a display device according to an embodiment.

[0073] The terms "above...", "top", and "upper surface" used herein refer to the upward direction relative to the display panel 110 (i.e., the Z-axis direction). The terms "below...", "bottom", and "lower surface" used herein refer to the downward direction relative to the display panel 110 (i.e., the direction opposite to the Z-axis direction). In addition, "left", "right", "upper", and "lower surface" represent directions when the display panel 110 is viewed from above. For example, the term "left" represents the direction opposite to the X-axis direction, the term "right" represents the X-axis direction, the term "upper" represents the Y-axis direction, and the term "lower" represents the direction opposite to the Y-axis direction.

[0074] In this specification, the display device 10 according to one embodiment is a device for displaying a moving image or a static image. The display device 10 can be used as a display screen of various devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IOT) device, and a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC). In the following description, it is shown that the display device 10 according to one embodiment is a medium-to-large display device including a plurality of source drivers 121, but the present disclosure is not limited thereto. The display device 10 according to one embodiment may be a small display device including one source driver 121, and the flexible film 122, the source circuit board 140, and the first cable 150 may be omitted. In addition, when the display device 10 according to one embodiment is a small display device, the source driver 121 and the timing controller 170 may be integrated into one integrated circuit and disposed on one circuit board, or may be adhered to the first substrate 111 of the display panel 110. For example, the medium or large display device may be a television, a monitor, or the like, and the small display device may be a smartphone, a tablet PC, or the like.

[0075] Reference Figure 1 , Figure 2 and Figure 3 The display device 10 includes a display panel 110, a data driver 120 including a source driver 121, a flexible film 122, a source circuit board 140, a first cable 150, a control circuit board 160, a timing controller 170, a power supply unit 171 and a scan signal driving unit 200.

[0076] The display panel 110 may have a rectangular shape in a plan view. Figure 2 As shown in , the display panel 110 may have a rectangular shape including a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction) in a plan view. The angle formed by the long side in the first direction (X-axis direction) and the short side in the second direction (Y-axis direction) may be a right angle or a circle with a predetermined curvature. The planar shape of the display panel 110 is not limited to a rectangular shape, and may be formed into other polygonal shapes, a circular shape, or an elliptical shape. In addition, although Figure 2 It is shown that the display panel 110 is formed to be flat, but the present disclosure is not limited thereto. The display panel 110 may include a curved portion curved with a predetermined curvature.

[0077] The display panel 110 may include a first substrate 111 and a second substrate 112. The second substrate 112 may be disposed to face a first surface of the first substrate 111. The first substrate 111 and the second substrate 112 may be formed to be rigid or flexible. The first substrate 111 may be made of glass or plastic. The second substrate 112 may be made of glass, plastic, an encapsulation film, or a barrier film. Optionally, the second substrate 112 may be omitted.

[0078] In addition, the display panel 110 may be an organic light-emitting display panel using an organic light-emitting diode, a quantum dot light-emitting display panel including a quantum dot light-emitting layer, an inorganic light-emitting display panel including an inorganic semiconductor, or a micro light-emitting display panel using a micro light-emitting diode (LED). In the following description, it is assumed that the display panel 110 is an organic light-emitting display panel, but the present disclosure is not limited thereto.

[0079] The display panel 110 may include a display area DA in which sub-pixels SP are formed to display an image and a non-display area NDA as a peripheral area of ​​the display area DA. In the display area DA, not only sub-pixels SP but also scan signal lines SCL, sense signal lines SSL, data lines DL, and first drive voltage lines VDDL connected to the sub-pixels SP may be provided. The scan signal lines SCL and the sense signal lines SSL may extend in a first direction (X-axis direction) in the display area DA. The data lines DL may extend in a second direction (Y-axis direction) intersecting the first direction (X-axis direction) in the display area DA. The first drive voltage line VDDL may extend in a second direction (Y-axis direction) in the display area DA.

[0080] Each of the sub-pixels SP may be connected to any one of the scan signal lines SCL, any one of the data lines DL, and any one of the sensing signal lines SSL. Figure 3 It is shown that each of the sub-pixels SP is connected to one scan signal line SCL, one data line DL, and one sensing signal line SSL, but the present disclosure is not limited thereto. The sub-pixels SP may be commonly connected to a first driving voltage line VDDL.

[0081] Each of the sub-pixels SP may include a driving transistor DT, at least one switching transistor, a light emitting element, and a capacitor. When a scan signal is applied from a scan signal line SCL, the switching transistor may be turned on, so that the data voltage of the data line DL may be applied to the gate electrode of the driving transistor DT. The driving transistor DT may emit light by supplying a driving current to the light emitting element according to the data voltage applied to the gate electrode. The driving transistor DT and at least one switching transistor may be a thin film switching transistor. The light emitting element may emit light according to the driving current of the driving transistor DT. The light emitting element may be an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The capacitor may be used to keep the data voltage applied to the gate electrode of the driving transistor DT constant.

[0082] The non-display area NDA may be defined as a region from a boundary of the display area DA to an edge of the display panel 110. A scan signal driving unit 200 for applying scan signals to the scan signal lines SCL and sensing signals to the sensing signal lines SSL may be disposed in the non-display area NDA.

[0083] The scan signal driving unit 200 may be connected to the flexible film 122 through a plurality of scan control lines. The scan signal driving unit 200 may receive a scan control signal SCS from the timing controller 170 through a plurality of scan control lines. The scan control signal SCS may include a plurality of clock signals, a sensing control signal, a gate-on voltage, and a gate-off voltage. The scan signal driving unit 200 may generate a scan signal and a sensing signal in response to the scan control signal SCS, and output the scan signal and the sensing signal to the scan signal line SCL and the sensing signal line SSL. Although Figure 2 It is shown that the scan signal driving unit 200 is formed on both sides of the display area DA (e.g., in the non-display area NDA on the left and right sides of the display area DA), but the present disclosure is not limited thereto. For example, the scan signal driving unit 200 may be formed on one side of the display area DA (e.g., in the non-display area NDA on the left or right sides of the display area DA).

[0084] One side of the flexible film 122 may be attached to the first surface of the first substrate 111 of the display panel 110, and the other side of the flexible film 122 may be attached to one surface of the source circuit board 140. Specifically, the size of the second substrate 112 is smaller than that of the first substrate 111, so that one side of the first substrate 111 may be exposed without being covered by the second substrate 112. The flexible film 122 may be attached to the side of the first substrate 111 that is exposed without being covered by the second substrate 112. Each of the flexible films 122 may be attached to the first surface of the first substrate 111 and one surface of the source circuit board 140 using an anisotropic conductive film.

[0085] Each of the flexible films 122 may be a flexible film such as a chip on film or a tape carrier package. The flexible film 122 may be bent to a position below the first substrate 111. In this case, the source circuit board 140, the first cable 150, and the control circuit board 160 may be disposed on the bottom surface of the display panel 110. Figure 1 and Figure 2 It is shown that eight flexible films 122 are attached to the first substrate 111 of the display panel 110 , but the number of the flexible films 122 is not limited thereto in this specification.

[0086] The source drivers 121 of the data driver 120 may be respectively disposed on one surface of the flexible film 122. The source drivers 121 may be formed as an integrated circuit (IC). The data driver 120 converts the digital video data DATA into an analog data voltage in response to the source control signal DCS of the timing controller 170, and supplies the analog data voltage to the data line of the display panel 110 through the flexible film 122.

[0087] Each of the source circuit boards 140 may be connected to the control circuit board 160 through the first cable 150. Each of the source circuit boards 140 may include a first connector 151 to be connected to the first cable 150. The source circuit board 140 may be a flexible printed circuit board or a printed circuit board. The first cable 150 may be a flexible cable.

[0088] The control circuit board 160 may be connected to the source circuit board 140 through the first cable 150. To this end, the control circuit board 160 may include a second connector 152 to be connected to the first cable 150. The control circuit board 160 may be a flexible printed circuit board or a printed circuit board.

[0089] Although Figure 1 and Figure 2 Four first cables 150 are shown connecting the source circuit board 140 and the control circuit board 160, but the number of the first cables 150 is not limited thereto in the present specification. Figure 1 and Figure 2 Two source circuit boards 140 are shown, but the number of the source circuit boards 140 is not limited thereto in this specification.

[0090] In addition, when the number of the flexible films 122 is small, the source circuit board 140 may be omitted. In this case, the flexible film 122 may be directly connected to the control circuit board 160.

[0091] The timing controller 170 may be disposed on one surface of the control circuit board 160. The timing controller 170 may be formed as an integrated circuit. The timing controller 170 receives digital video data and a timing signal from a system on chip of a system circuit board. The timing controller 170 may generate a source control signal DCS for controlling the timing of a source driver 121 of the data driver 120 and a scan control signal SCS for controlling the timing of a scan signal driving unit 200 in response to the timing signal. The timing controller 170 may output the scan control signal SCS to the scan signal driving unit 200, and output the digital video data DATA and the source control signal DCS to the data driver 120.

[0092] The power supply unit 171 may generate a first driving voltage and supply the first driving voltage to a first driving voltage line VDDL. In addition, the power supply unit 171 may generate a second driving voltage and supply the second driving voltage to a cathode electrode of an organic light emitting diode of each of the sub-pixels SP. The first driving voltage may be a high potential voltage for driving an organic light emitting diode, and the second driving voltage may be a low potential voltage for driving an organic light emitting diode. That is, the first driving voltage may have a higher potential than the second driving voltage. In addition, the power supply unit 171 may generate a reference voltage and supply the reference voltage to a reference voltage line connected to each of the sub-pixels SP.

[0093] Figure 4 is a circuit diagram specifically showing a sub-pixel according to one embodiment.

[0094] Reference Figure 4 , the sub-pixel SP may include a light emitting element EL, a driving transistor DT, a first switching transistor ST1 , a second switching transistor ST2 , and a capacitor Cst.

[0095] The light emitting element EL emits light according to the current supplied by the driving transistor DT. The light emitting element EL may be an organic light emitting diode, but is not limited thereto. For example, the light emitting element EL may be a quantum dot light emitting diode, an inorganic light emitting diode, or a micro light emitting diode. In this case, when the light emitting element EL is an organic light emitting diode, the light emitting element EL may include an anode electrode, a hole transport layer, an organic light emitting layer, an electron transport layer, and a cathode electrode. In the light emitting element EL, when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light. The anode electrode of the light emitting element EL may be connected to the source electrode of the driving transistor DT, and the cathode electrode may be connected to a second driving voltage line VSSL, and a low potential voltage lower than the high potential voltage is supplied to the second driving voltage line VSSL.

[0096] The driving transistor DT adjusts the current flowing from the first driving voltage line VDDL to which the first source voltage is applied to the light emitting element EL according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT may be connected to the first electrode of the first switching transistor ST1, the source electrode of the driving transistor DT may be connected to the anode electrode of the light emitting element EL, and the drain electrode of the driving transistor DT may be connected to the first driving voltage line VDDL to which the high potential voltage is applied.

[0097] The first switching transistor ST1 is turned on by a scanning signal applied from the scanning signal line SCL to connect the data line DL to the gate electrode of the driving transistor DT. The gate electrode of the first switching transistor ST1 may be connected to the scanning signal line SCL, the first electrode of the first switching transistor ST1 may be connected to the gate electrode of the driving transistor DT, and the second electrode of the first switching transistor ST1 may be connected to the data line DL.

[0098] The second switch transistor ST2 is turned on by the sensing signal of the sensing signal line SSL to connect the reference voltage line RVL to the source electrode of the driving transistor DT. The gate electrode of the second switch transistor ST2 may be connected to the sensing signal line SSL, the first electrode of the second switch transistor ST2 may be connected to the reference voltage line RVL, and the second electrode of the second switch transistor ST2 may be connected to the source electrode of the driving transistor DT.

[0099] One of the first electrode and the second electrode of each of the first switching transistor ST1 and the second switching transistor ST2 may be a source electrode, and the other may be a drain electrode.

[0100] The capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The capacitor Cst stores a voltage difference between the gate voltage and the source voltage of the driving transistor DT.

[0101] The driving transistor DT, the first switching transistor ST1 and the second switching transistor ST2 may be formed as thin film transistors. Figure 4 The case where the driving transistor DT and the first and second switching transistors ST1 and ST2 are formed as N-type metal oxide semiconductor field effect transistors (MOSFETs) is mainly described, but the present disclosure is not limited thereto. The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed as P-type MOSFETs.

[0102] Figure 5 An example of the driving timing of the sub-pixels in the Nth frame period and the N+1th frame period is shown. Figure 6is a waveform diagram showing kth to k+2th scanning signals and kth to k+2th sensing signals during an effective period of an Nth frame period. Figure 7 is a waveform diagram showing kth to k+2th scanning signals and kth to k+2th sensing signals during a vertical blanking period of an Nth frame period.

[0103] Reference Figures 5 to 7 , each of the N-th frame period (N is a positive integer) and the N+1-th frame period includes an effective period ACT and a vertical blanking period VB. The effective period ACT is a period in which a data voltage is applied to each of the sub-pixels SP. The vertical blanking period VB, which is an idle period, is a period in which a source voltage of a driving transistor DT of each of the sub-pixels SP connected to at least one scanning signal line SCL is sensed through a reference voltage line RVL.

[0104] The data driver 120 may apply a compensation data voltage compensating for the electron mobility of the driving transistor DT of each of the sub-pixels SP to the data line DL during the active period ACT. The data driver 120 may apply a sensing data voltage for compensating for the electron mobility of the driving transistor DT of each of the sub-pixels SP to the data line DL during the vertical blanking period VB.

[0105] In addition, during the active period ACT, a reference voltage may be applied to the reference voltage line RVL. During the vertical blanking period VB, the reference voltage line RVL may be connected to the analog-to-digital converter, and the source voltage of the driving transistor DT of each of the sub-pixels SP may be converted into sensing data as digital data by the analog-to-digital converter through the reference voltage line RVL and output to the timing controller 170.

[0106] The length of the active period ACT may be longer than the length of the vertical blanking period VB. The vertical blanking period VB of the Nth frame period may be disposed between the active period ACT of the Nth frame period and the active period ACT of the N+1th frame period.

[0107] The scan signal driving unit 200 may sequentially apply scan signals to the scan signal lines SCL during the active period ACT. Figure 5 As shown in , when the display panel 110 includes first to nth (n is a positive integer) scan signal lines SCL1 to SCLn, the scan signal driving unit 200 may sequentially apply scan signals to the first to nth scan signal lines SCL1 to SCLn. Figure 6As shown in , the scan signal driving unit 200 can apply the first scan signal SC1 of the gate-on voltage Von to the first scan signal line SCL1, and then can apply the second scan signal SC2 of the gate-on voltage Von to the second scan signal line SCL2, and then can apply the third scan signal SC3 of the gate-on voltage Von to the third scan signal line SCL3.

[0108] In addition, the scan signal driving unit 200 may sequentially apply the sensing signal to the sensing signal line SSL during the effective period ACT. When the display panel 110 includes first to n-th sensing signal lines, the sensing signal may be sequentially applied to the first to n-th sensing signal lines. For example, Figure 6 As shown in , the scan signal driving unit 200 can apply the first sensing signal SS1 of the gate-on voltage Von to the first sensing signal line, and then can apply the second sensing signal SS2 of the gate-on voltage Von to the second sensing signal line, and then can apply the third sensing signal SS3 of the gate-on voltage Von to the third sensing signal line.

[0109] On the contrary, the scan signal driving unit 200 may apply the scan signal to at least one scan signal line SCL and apply the sensing signal to at least one sensing signal line SSL during the vertical blanking period VB. Figure 5 and Figure 7 As shown in , during the vertical blanking period VB of the Nth frame period, the scan signal driving unit 200 may apply the first scan signal SC1 of the gate-on voltage Von to the first scan signal line SCL1, and may not apply the scan signal of the gate-on voltage Von to the second scan signal line SCL2 to the nth scan signal line SCLn. That is, the first gate-off voltage Voff1 may be applied to the second scan signal line SCL2 to the nth scan signal line SCLn. In addition, as Figure 5 As shown in , during the vertical blanking period VB of the N+1th frame period, the scan signal driving unit 200 may apply the first scan signal SC1 of the gate-on voltage Von to the second scan signal line SCL2, and may not apply the scan signal of the gate-on voltage Von to the first scan signal line SCL1 and the third scan signal line SCL3 to the nth scan signal line SCLn. That is, the first gate-off voltage Voff1 may be applied to the first scan signal line SCL1 and the third scan signal line SCL3 to the nth scan signal line SCLn.

[0110] like Figures 5 to 7As shown in , the pulse width PW1 of the scanning signal during the effective period ACT is different from the pulse width PW3 of the scanning signal during the vertical blanking period VB. The pulse width of the scanning signal represents the length of the period in which the scanning signal is output as the gate-on voltage. In addition, the pulse width PW2 of the sensing signal during the effective period ACT is different from the pulse width PW4 of the sensing signal during the vertical blanking period VB. The pulse width of the sensing signal represents the length of the period in which the sensing signal is output as the gate-on voltage.

[0111] In the following description, we will combine Figure 8 and Fig. 9 The scan signal driving unit 200 is described in detail, and the scan signal driving unit 200 is capable of simultaneously outputting the kth (k is an integer satisfying 1≤k≤n) scan signal and the kth sensing signal to reduce the area of ​​the scan signal driving unit 200, and outputting different scan signals and different sensing signals in the effective period ACT and the vertical blanking period VB.

[0112] Figure 8 FIG. 2 shows an example of a scanning signal driving unit according to an embodiment. To simplify the description, Figure 8 Only the k-2th stage STk-2 to the k+2th stage STk+2 are shown.

[0113] In the following description, a "previous stage" refers to a stage located before a reference stage. A "latter stage" refers to a stage located behind a reference stage. For example, a previous stage of a k-th stage STk refers to a first stage ST1 to a k-1-th stage STk-1, and a later stage of a k-th stage STk refers to a k+1-th stage STk+1 to an n-th stage STn.

[0114] Reference Figure 8 , the scan signal driving unit 200 includes a stage area STA in which a plurality of stages STk-2 to STk+2 are arranged and a line area LA in which a plurality of lines connected to the plurality of stages STk-2 to STk+2 to apply signals to the plurality of stages STk-2 to STk+2 are arranged. In the line area LA, carry clock lines CRC1 to CRC3 to which carry clock signals whose phases are sequentially delayed are applied, sense clock lines SEC1 to SEC4 to which sense clock signals whose phases are sequentially delayed are applied, scan clock lines SCC1 to SCC4 to which scan clock signals whose phases are sequentially delayed are applied, sense control lines SES to which sense control signals are applied, and control clock lines SCK to which control clock signals are applied may be arranged. The carry clock lines CRC1 to CRC3, the sense clock lines SEC1 to SEC4, the scan clock lines SCC1 to SCC4, the sense control lines SES, and the control clock lines SCK may be defined in combination. Figure 3 1 and 2. The scanning control line to which the scanning control signal SCS is applied is described.

[0115] Although Figure 8 Three carry clock lines CRC1 to CRC3, four sense clock lines SEC1 to SEC4, and four scan clock lines SCC1 to SCC4 are shown, but the number of carry clock lines CRC1 to CRC3, the number of sense clock lines SEC1 to SEC4, and the number of scan clock lines SCC1 to SCC4 are not limited thereto.

[0116] The scan signal driving unit 200 includes a plurality of stages STk-2 to STk+2 respectively connected to the scan signal lines SCLk-2 to SCLk+2 and the sensing signal lines SSLk-2 to SSLk+2. The k-2th stage STk-2 outputs the k-2th scan signal to the k-2th scan signal line SCLk-2, and outputs the k-2th sensing signal to the k-2th sensing signal line SSLk-2. The k-1th stage STk-1 outputs the k-1th scan signal to the k-1th scan signal line SCLk-1, and outputs the k-1th sensing signal to the k-1th sensing signal line SSLk-1. The kth stage STk outputs the kth scan signal to the kth scan signal line SCLk, and outputs the kth sensing signal to the kth sensing signal line SSLk. The k+1th stage STk+1 outputs the k+1th scan signal to the k+1th scan signal line SCLk+1, and outputs the k+1th sensing signal to the k+1th sensing signal line SSLk+1. The k+2th stage STk+2 outputs the k+2th scan signal to the k+2th scan signal line SCLk+2, and outputs the k+2th sensing signal to the k+2th sensing signal line SSLk+2.

[0117] Each of stages STk-2 to STk+2 includes a start terminal CPI, a carry terminal CNI, a scan clock terminal SCI, a sense clock terminal SSI, a first carry clock terminal CRI1, a second carry clock terminal CRI2, a sense control terminal SEI, a first control clock terminal CCI1, a carry output terminal CO, a scan output terminal SCO and a sense output terminal SSO.

[0118] The start terminal CPI can be connected to the start signal line or the carry output terminal CO of the previous stage. Figure 8 As shown in , the start terminal CPI of the kth stage STk can be connected to the start signal line or the carry output terminal CO of the k-2th stage STk-2. In this case, the start signal of the start signal line or the k-2th carry signal of the k-2th stage STk-2 can be input to the start terminal CPI of the kth stage STk.

[0119] The rear carry terminal CNI of each of the stages STk-2 to STk+2 may be connected to the carry output terminal CO of the rear stage. Figure 8As shown in , the rear carry terminal CNI of the kth stage STk may be connected to the carry output terminal CO of the k+2th stage STk+2. In this case, the k+2th carry signal of the k+2th stage STk+2 may be input to the rear carry terminal CNI of the kth stage STk.

[0120] The scan clock terminal SCI of each of the stages STk-2 to STk+2 may be connected to any one of the scan clock lines SCC1 to SCC4. The scan clock lines SCC1 to SCC4 may be sequentially connected to the scan clock terminals SCI of the stages STk-2 to STk+2. Figure 8 As shown in , the first scan clock line SCC1 can be connected to the scan clock terminal SCI of the k-2th stage STk-2, and the second scan clock line SCC2 can be connected to the scan clock terminal SCI of the k-1th stage STk-1. The third scan clock line SCC3 can be connected to the scan clock terminal SCI of the kth stage STk, the fourth scan clock line SCC4 can be connected to the scan clock terminal SCI of the k+1th stage STk+1, and the first scan clock line SCC1 can be connected to the scan clock terminal SCI of the k+2th stage STk+2.

[0121] The sensing clock terminal SSI of each of the stages STk-2 to STk+2 may be connected to any one of the sensing clock lines SEC1 to SEC4. The sensing clock lines SEC1 to SEC4 may be sequentially connected to the sensing clock terminals SSI of the stages STk-2 to STk+2. Figure 8 As shown in , the first sensing clock line SEC1 can be connected to the sensing clock terminal SSI of the k-2th stage STk-2, and the second sensing clock line SEC2 can be connected to the sensing clock terminal SSI of the k-1th stage STk-1. The third sensing clock line SEC3 can be connected to the sensing clock terminal SSI of the kth stage STk, the fourth sensing clock line SEC4 can be connected to the sensing clock terminal SSI of the k+1th stage STk+1, and the first sensing clock line SEC1 can be connected to the sensing clock terminal SSI of the k+2th stage STk+2.

[0122] Each of the first carry clock terminal CRI1 and the second carry clock terminal CRI2 of each of the stages STk-2 to STk+2 may be connected to any one of the carry clock lines CRC1 to CRC3. The carry clock lines CRC1 to CRC3 may be sequentially connected to the first carry clock terminal CRI1 and the second carry clock terminal CRI2 of the stages STk-2 to STk+2. For example, Figure 8As shown in, the first carry clock line CRC1 can be connected to the first carry clock terminal CRI1 of the k-2th stage STk-2, and the second carry clock line CRC2 can be connected to the second carry clock terminal CRI2. The second carry clock line CRC2 can be connected to the first carry clock terminal CRI1 of the k-1th stage STk-1, and the third carry clock line CRC3 can be connected to the second carry clock terminal CRI2. The third carry clock line CRC3 can be connected to the first carry clock terminal CRI1 of the kth stage STk, and the first carry clock line CRC1 can be connected to the second carry clock terminal CRI2. The first carry clock line CRC1 can be connected to the first carry clock terminal CRI1 of the k+1th stage STk+1, and the second carry clock line CRC2 can be connected to the second carry clock terminal CRI2. The second carry clock line CRC2 can be connected to the first carry clock terminal CRI1 of the k+2th stage STk+2, and the third carry clock line CRC3 can be connected to the second carry clock terminal CRI2.

[0123] The sensing control terminal SEI of each of the stages STk-2 to STk+2 may be connected to the sensing control line SES. A sensing control signal may be input to the sensing control terminal SEI of each of the stages STk-2 to STk+2.

[0124] The first control clock terminal CCI1 of each of the stages STk-2 to STk+2 may be connected to the control clock line SCK. The first control clock signal may be input to the first control clock terminal CCI1 of each of the stages STk-2 to STk+2.

[0125] The carry output terminal CO of each of the stages STk-2 to STk+2 outputs a carry signal. The carry output terminal CO of each of the stages STk-2 to STk+2 can be connected to the rear carry terminal CNI of the previous stage and the start terminal CPI of the next stage. Figure 8 As shown in , the carry output terminal CO of the kth stage STk can be connected to the rear carry terminal CNI of the k-2th stage STk-2 and the start terminal CPI of the k+2th stage STk+2.

[0126] The scan output terminal SCO of each of the stages STk-2 to STk+2 is connected to the scan signal line to output the scan signal. Figure 8As shown in , the scan output terminal SCO of the k-2th stage STk-2 can be connected to the k-2th scan signal line SCLk-2 to output the k-2th scan signal, and the scan output terminal SCO of the k-1th stage STk-1 can be connected to the k-1th scan signal line SCLk-1 to output the k-1th scan signal. The scan output terminal SCO of the kth stage STk can be connected to the kth scan signal line SCLk to output the kth scan signal, and the scan output terminal SCO of the k+1th stage STk+1 can be connected to the k+1th scan signal line SCLk+1 to output the k+1th scan signal. The scan output terminal SCO of the k+2th stage STk+2 can be connected to the k+2th scan signal line SCLk+2 to output the k+2th scan signal.

[0127] The sensing output terminal SSO of each of the stages STk-2 to STk+2 is connected to the sensing signal line to output a sensing signal. Figure 8 As shown in , the sensing output terminal SSO of the k-2th stage STk-2 can be connected to the k-2th sensing signal line SSLk-2 to output the k-2th sensing signal, and the sensing output terminal SSO of the k-1th stage STk-1 can be connected to the k-1th sensing signal line SSLk-1 to output the k-1th sensing signal. The sensing output terminal SSO of the kth stage STk can be connected to the kth sensing signal line SSLk to output the kth sensing signal, and the sensing output terminal SSO of the k+1th stage STk+1 can be connected to the k+1th sensing signal line SSLk+1 to output the k+1th sensing signal. The sensing output terminal SSO of the k+2th stage STk+2 can be connected to the k+2th sensing signal line SSLk+2 to output the k+2th sensing signal.

[0128] like Figure 8 As shown in , since the scan signal driving unit 200 includes only one stage for simultaneously outputting the scan signal and the sensing signal, the area of ​​the scan signal driving unit 200 can be reduced compared with a case in which a stage for outputting the scan signal and a stage for outputting the sensing signal are separately provided.

[0129] Fig. 9 is a circuit diagram showing a k-th stage of a scan signal driving unit according to one embodiment.

[0130] Reference Fig. 9, the k-th stage STk includes a first output unit 210, a second output unit 220, a sensing controller 230, a first pull-up node controller 240, a second pull-up node controller 250, a third pull-up node controller 260, and an inverter unit 270. The k-th stage STk may also include a start terminal CPI, a carry terminal CNI, a first carry clock terminal CRI1, a second carry clock terminal CRI2, a sensing control terminal SEI, a first control clock terminal CCI1, a carry output terminal CO, a scan output terminal SCO, and a sensing output terminal SSO. The k-th stage STk may also include a first gate-off terminal VOF1, a second gate-off terminal VOF2, and a gate-on terminal VON. A gate-on voltage may be applied to the gate-on terminal VON, a first gate-off voltage may be applied to the first gate-off terminal VOF1, and a second gate-off voltage may be applied to the second gate-off terminal VOF2. The gate-on voltage may be higher than 0V, and the first gate-off voltage and the second gate-off voltage may be lower than or equal to 0V. The first gate-off voltage may be higher than the second gate-off voltage.

[0131] Fig. 9 A case is mainly described in which the third carry clock signal of the third carry clock line CRC3 is applied to the first carry clock terminal CRI1, the first carry clock signal of the first carry clock line CRC1 is applied to the second carry clock terminal CRI2, the third scan clock signal of the third scan clock line SCC3 is applied to the scan clock terminal SCI, and the third sense clock signal of the third sense clock line SEC3 is applied to the sense clock terminal SSI. In addition, Fig. 9 A case is mainly described in which the carry signal of the k-2th stage STk-2 is applied to the start terminal CPI, and the carry signal of the k+2th stage STk+2 is applied to the rear carry terminal CNI.

[0132] Fig. 9It is shown that the first scan pull-up transistor SCU1, the first scan pull-down transistor SCD1, the first sense pull-up transistor SSU1, the first sense pull-down transistor SSD1, the first transistor T1 to the third transistor T3, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10 to the thirteenth transistor T13 are formed as an N-type metal oxide semiconductor field effect transistor (MOSFET). In this case, when a gate high voltage is applied, the first scan pull-up transistor SCU1, the first scan pull-down transistor SCD1, the first sense pull-up transistor SSU1, the first sense pull-down transistor SSD1, the first transistor T1 to the third transistor T3, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10 to the thirteenth transistor T13 are turned on. Therefore, the gate-on voltage may be a gate high voltage, the first gate-off voltage may be a first gate low voltage, and the second gate-off voltage may be a second gate low voltage.

[0133] When the pull-up node Q has a gate-on voltage, the first output unit 210 outputs the third scan clock signal input to the scan clock terminal SCI to the scan output terminal SCO, and outputs the third sense clock signal input to the sense clock terminal SSI to the sense output terminal SSO. When the pull-down node QB has a gate-on voltage, the first output unit 210 outputs a first gate-off voltage to the scan output terminal SCO and the sense output terminal SSO.

[0134] The first output unit 210 may include a first scan pull-up transistor SCU1 , a first scan pull-down transistor SCD1 , a first sense pull-up transistor SSU1 , a first sense pull-down transistor SSD1 , a first capacitor C1 , and a second capacitor C2 .

[0135] The first scan pull-up transistor SCU1 is turned on by the gate-on voltage of the pull-up node Q to output the third scan clock signal input to the scan clock terminal SCI to the scan output terminal SCO. A gate electrode of the first scan pull-up transistor SCU1 may be connected to the pull-up node Q, a first electrode of the first scan pull-up transistor SCU1 may be connected to the scan output terminal SCO, and a second electrode of the first scan pull-up transistor SCU1 may be connected to the scan clock terminal SCI.

[0136] In order to increase the amount of current flowing through the channel when the first scan pull-up transistor SCU1 is turned on, the first scan pull-up transistor SCU1 may further include a second gate electrode electrically connected to the pull-up node Q. In this case, the first scan pull-up transistor SCU1 may be formed in a double-gate structure including a gate electrode corresponding to an upper gate electrode and a second gate electrode corresponding to a lower gate electrode.

[0137] The first scan pull-down transistor SCD1 is turned on by the gate-on voltage of the pull-down node QB to output the first gate-off voltage input to the first gate-off terminal VOF1 to the scan output terminal SCO. A gate electrode of the first scan pull-down transistor SCD1 may be connected to the pull-down node QB, a first electrode of the first scan pull-down transistor SCD1 may be connected to the first gate-off terminal VOF1, and a second electrode of the first scan pull-down transistor SCD1 may be connected to the scan output terminal SCO.

[0138] In order to prevent or reduce leakage current flowing through the first scan pull-down transistor SCD1, the first scan pull-down transistor SCD1 may further include a second gate electrode connected to the pull-down node QB. In this case, the first scan pull-down transistor SCD1 may be formed into a double-gate structure including a gate electrode corresponding to the upper gate electrode and a second gate electrode corresponding to the lower gate electrode.

[0139] In order to increase the amount of current flowing through the channel when the first sensing pull-up transistor SSU1 is turned on, the first sensing pull-up transistor SSU1 is turned on by the gate-on voltage of the pull-up node Q to output the third sensing clock signal input to the sensing clock terminal SSI to the sensing output terminal SSO. A gate electrode of the first sensing pull-up transistor SSU1 may be connected to the pull-up node Q, a first electrode of the first sensing pull-up transistor SSU1 may be connected to the sensing output terminal SSO, and a second electrode of the first sensing pull-up transistor SSU1 may be connected to the sensing clock terminal SSI.

[0140] The first sensing pull-up transistor SSU1 may further include a second gate electrode electrically connected to the pull-up node Q. In this case, the first sensing pull-up transistor SSU1 may be formed in a double gate structure including a gate electrode corresponding to an upper gate electrode and a second gate electrode corresponding to a lower gate electrode.

[0141] The first sensing pull-down transistor SSD1 is turned on by the gate-on voltage of the pull-down node QB to output the first gate-off voltage input to the first gate-off terminal VOF1 to the sensing output terminal SSO. A gate electrode of the first sensing pull-down transistor SSD1 may be connected to the pull-down node QB, a first electrode of the first sensing pull-down transistor SSD1 may be connected to the first gate-off terminal VOF1, and a second electrode of the first sensing pull-down transistor SSD1 may be connected to the sensing output terminal SSO.

[0142] In order to prevent or reduce leakage current flowing through the first sensing pull-down transistor SSD1, the first sensing pull-down transistor SSD1 may further include a second gate electrode connected to the pull-down node QB. In this case, the first sensing pull-down transistor SSD1 may be formed as a double-gate structure including a gate electrode corresponding to the upper gate electrode and a second gate electrode corresponding to the lower gate electrode.

[0143] The first capacitor C1 is provided between the pull-up node Q and the scan output terminal SCO. One electrode of the first capacitor C1 may be connected to the pull-up node Q, and the other electrode may be connected to the scan output terminal SCO. Since the first capacitor C1 stores the voltage difference between the pull-up node Q and the scan output terminal SCO, the voltage difference between the pull-up node Q and the scan output terminal SCO may be maintained at a constant level by the first capacitor C1.

[0144] The second capacitor C2 is provided between the pull-up node Q and the sensing output terminal SSO. One electrode of the second capacitor C2 may be connected to the pull-up node Q, and the other electrode may be connected to the sensing output terminal SSO. Since the second capacitor C2 stores the voltage difference between the pull-up node Q and the sensing output terminal SSO, the voltage difference between the pull-up node Q and the sensing output terminal SSO may be maintained at a constant level by the second capacitor C2.

[0145] When the pull-up node Q has the gate-on voltage, the second output unit 220 outputs the third carry clock signal input to the first carry clock terminal CRI1 to the carry output terminal CO. When the pull-down node QB has the gate-on voltage, the second output unit 220 outputs the first gate-off voltage to the carry output terminal CO.

[0146] The second output unit 220 may include a carry pull-up transistor CU1 , a carry pull-down transistor CU2 , and a third capacitor C3 .

[0147] The carry pull-up transistor CU1 is turned on by the gate-on voltage of the pull-up node Q to output the third carry clock signal input to the first carry clock terminal CRI1 to the carry output terminal CO. A gate electrode of the carry pull-up transistor CU1 may be connected to the pull-up node Q, a first electrode of the carry pull-up transistor CU1 may be connected to the carry output terminal CO, and a second electrode of the carry pull-up transistor CU1 may be connected to the first carry clock terminal CRI1.

[0148] The carry pull-down transistor CU2 is turned on by the gate-on voltage of the pull-down node QB to output the first gate-off voltage input to the second gate-off terminal VOF2 to the carry output terminal CO. A gate electrode of the carry pull-down transistor CU2 may be connected to the pull-down node QB, a first electrode of the carry pull-down transistor CU2 may be connected to the second gate-off terminal VOF2, and a second electrode of the carry pull-down transistor CU2 may be connected to the carry output terminal CO.

[0149] The third capacitor C3 is provided between the pull-down node QB and the first gate-off terminal VOF1. One electrode of the third capacitor C3 may be connected to the pull-down node QB, and the other electrode may be connected to the first gate-off terminal VOF1. Since the third capacitor C3 stores the voltage difference between the pull-down node QB and the first gate-off terminal VOF1, the voltage difference between the pull-down node QB and the first gate-off terminal VOF1 may be maintained at a constant level by the third capacitor C3.

[0150] When the sensing control signal of the gate-on voltage is input to the sensing control terminal SEI during the effective period of the N-th frame period, the sensing controller 230 applies the gate-on voltage to the pull-up node during the vertical blanking period of the N-th frame period. Therefore, the first scanning pull-up transistor SCU1 and the first sensing pull-up transistor SSU1 are turned on during the vertical blanking period of the N-th frame period, so that the first output unit 210 can output the third scanning clock signal input to the scanning clock terminal SCI to the scanning output terminal SCO, and can output the third sensing clock signal input to the sensing clock terminal SSI to the sensing output terminal SSO.

[0151] The sensing controller 230 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , and a fourth capacitor C4 .

[0152] The first transistor T1 is turned on by the gate-on voltage of the sense control signal input to the sense control terminal SEI to apply the carry signal of the k+2th stage STk+2 input to the rear carry terminal CNI to the sense control node S. That is, when the carry signal of the k+2th stage STk+2 of the gate-on voltage is input during the period in which the first transistor T1 is turned on, the sense control node S has the gate-on voltage.

[0153] The first transistor T1 may include a 1-1th transistor T1 - 1 and a 1-2th transistor T1 - 2 .

[0154] The 1-1 transistor T1-1 is turned on by the gate-on voltage of the sense control signal input to the sense control terminal SEI so that the back-carry terminal CNI is connected to the second electrode of the 1-2 transistor T1-2. The gate electrode of the 1-1 transistor T1-1 may be connected to the sense control terminal SEI, the first electrode of the 1-1 transistor T1-1 may be connected to the second electrode of the 1-2 transistor T1-2, and the second electrode of the 1-1 transistor T1-1 may be connected to the back-carry terminal CNI.

[0155] The 1-2 transistor T1-2 is turned on by the gate-on voltage of the sensing control signal input to the sensing control terminal SEI so that the sensing control node S is connected to the first electrode of the 1-1 transistor T1-1. The gate electrode of the 1-2 transistor T1-2 may be connected to the sensing control terminal SEI, the first electrode of the 1-2 transistor T1-2 may be connected to the sensing control node S, and the second electrode of the 1-2 transistor T1-2 may be connected to the first electrode of the 1-1 transistor T1-1.

[0156] The second transistor T2 and the third transistor T3 are turned on by the gate-on voltage of the sensing control node S to apply the first control clock signal input to the first control clock terminal CCI1 to the pull-up node Q. That is, the second transistor T2 and the third transistor T3 are turned on by the gate-on voltage of the sensing control node S to connect the first control clock terminal CCI1 to the pull-up node Q. The gate electrode of the second transistor T2 may be connected to the sensing control node S, the first electrode of the second transistor T2 may be connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 may be connected to the first control clock terminal CCI1. The gate electrode of the third transistor T3 may be connected to the sensing control node S, the first electrode of the third transistor T3 may be connected to the pull-up node Q, and the second electrode of the third transistor T3 may be connected to the first electrode of the second transistor T2.

[0157] The fourth capacitor C4 is provided between the sensing control node S and the second gate-off terminal VOF2. One electrode of the fourth capacitor C4 may be connected to the sensing control node S, and the other electrode may be connected to the second gate-off terminal VOF2. Since the fourth capacitor C4 stores the voltage difference between the sensing control node S and the second gate-off terminal VOF2, the voltage difference between the sensing control node S and the second gate-off terminal VOF2 may be maintained at a constant level by the fourth capacitor C4.

[0158] When the carry signal of the k-2th stage STk-2 applied to the start terminal CPI has the gate-on voltage, the first pull-up node controller 240 applies the gate-on voltage to the pull-up node Q. The first pull-up node controller 240 may include a sixth transistor T6.

[0159] The sixth transistor T6 is turned on by the carry signal of the k-2th stage STk-2 of the gate-on voltage to connect the pull-up node Q to the gate-on terminal VON, so that the gate-on voltage can be applied to the pull-up node Q. A gate electrode of the sixth transistor T6 can be connected to the starting terminal CPI, a first electrode of the sixth transistor T6 can be connected to the pull-up node Q, and a second electrode of the sixth transistor T6 can be connected to the gate-on terminal VON.

[0160] When the carry signal of the k+2th stage STk+2 input to the rear carry terminal CNI has the gate-on voltage, the second pull-up node controller 250 applies the second gate-off voltage to the pull-up node Q. The second pull-up node controller 250 may include an eighth transistor T8.

[0161] The eighth transistor T8 is turned on by the carry signal of the k+2th stage STk+2 of the gate-on voltage to connect the pull-up node Q to the carry output terminal CO, so that the second gate-off voltage can be applied to the pull-up node Q. The gate electrode of the eighth transistor T8 can be connected to the rear carry terminal CNI, the first electrode of the eighth transistor T8 can be connected to the carry output terminal CO, and the second electrode of the eighth transistor T8 can be connected to the pull-up node Q.

[0162] When the third scan clock signal input to the scan clock terminal SCI or the third sensing clock signal input to the sensing clock terminal SSI has a gate-on voltage and the pull-down node QB has a gate-on voltage, the third pull-up node controller 260 applies the second gate-off voltage to the pull-up node Q. The third pull-up node controller 260 may include a tenth transistor T10. The tenth transistor T10 may include a tenth-first transistor T10-1 and a tenth-second transistor T10-2.

[0163] The tenth-first transistor T10-1 may be turned on by the third scan clock signal or the third sensing clock signal of the gate-on voltage to connect the pull-up node Q to the second electrode of the tenth-second transistor T10-2. The gate electrode of the tenth-first transistor T10-1 may be connected to the scan clock terminal SCI or the sensing clock terminal SSI, the first electrode of the tenth-first transistor T10-1 may be connected to the second electrode of the tenth-second transistor T10-2, and the second electrode of the tenth-first transistor T10-1 may be connected to the pull-up node Q.

[0164] The tenth-second transistor T10-2 may be turned on by the gate-on voltage of the pull-down node QB to connect the carry output terminal CO to the first electrode of the tenth-first transistor T10-1. The gate electrode of the tenth-second transistor T10-2 may be connected to the pull-down node QB, the first electrode of the tenth-second transistor T10-2 may be connected to the carry output terminal CO, and the second electrode of the tenth-second transistor T10-2 may be connected to the first electrode of the tenth-first transistor T10-1.

[0165] When the pull-up node Q has the gate-on voltage, the inverter unit 270 applies the first gate-off voltage to the pull-down node QB. Also, when the pull-up node Q has the second gate-off voltage, the inverter unit 270 may apply the gate-on voltage to the pull-down node QB.

[0166] The inverter unit 270 may include an eleventh transistor T11 , a twelfth transistor T12 , and a thirteenth transistor T13 .

[0167] The eleventh transistor T11 is turned on by the gate-on voltage of the pull-up node Q to apply the first carry clock signal of the second carry clock terminal CRI2 to the pull-down node QB. During a period in which the pull-up node Q has a voltage higher than or equal to the gate-on voltage, the first carry clock signal input to the second carry clock terminal CRI2 may have a first gate-off voltage. The eleventh transistor T11 may include an eleventh-first transistor T11-1 and an eleventh-second transistor T11-2.

[0168] The eleventh-first transistor T11-1 may be turned on by the gate-on voltage of the pull-up node Q to connect the second carry clock terminal CRI2 to the second electrode of the eleventh-second transistor T11-2. The gate electrode of the eleventh-first transistor T11-1 may be connected to the pull-up node Q, the first electrode of the eleventh-first transistor T11-1 may be connected to the second electrode of the eleventh-second transistor T11-2, and the second electrode of the eleventh-first transistor T11-1 may be connected to the second carry clock terminal CRI2.

[0169] The eleventh-second transistor T11-2 may be turned on by the gate-on voltage of the pull-up node Q to connect the pull-down node QB to the first electrode of the eleventh-first transistor T11-1. The gate electrode of the eleventh-second transistor T11-2 may be connected to the pull-up node Q, the first electrode of the eleventh-second transistor T11-2 may be connected to the pull-down node QB, and the second electrode of the eleventh-second transistor T11-2 may be connected to the first electrode of the eleventh-second transistor T11-2.

[0170] The twelfth transistor T12 may be turned on by the gate-on voltage of the first carry clock signal of the second carry clock terminal CRI2 to connect the pull-down node QB to the gate-on terminal VON so that the gate-on voltage may be applied to the pull-down node QB. A gate electrode of the twelfth transistor T12 may be connected to the second carry clock terminal CRI2, a first electrode of the twelfth transistor T12 may be connected to the pull-down node QB, and a second electrode of the twelfth transistor T12 may be connected to the gate-on terminal VON.

[0171] The thirteenth transistor T13 may be turned on by the gate-on voltage of the pull-down node QB to connect the pull-down node QB to the gate-on terminal VON so that the gate-on voltage may be applied to the pull-down node QB. The gate electrode and the first electrode of the thirteenth transistor T13 may be connected to the pull-down node QB, and the second electrode of the thirteenth transistor T13 may be connected to the gate-on terminal VON. The channel width of the thirteenth transistor T13 may be greater than the channel width of the eleventh transistor T11.

[0172] One of the first and second electrodes of each of the first scan pull-up transistor SCU1, the first scan pull-down transistor SCD1, the first sense pull-up transistor SSU1, the first sense pull-down transistor SSD1, the first to third transistors T1 to T3, the sixth transistor T6, the eighth transistor T8, and the tenth to thirteenth transistors T10 to T13 may be a source electrode, and the other may be a drain electrode.

[0173] In addition, the semiconductor layer of each of the first scanning pull-up transistor SCU1, the first scanning pull-down transistor SCD1, the first sensing pull-up transistor SSU1, the first sensing pull-down transistor SSD1, the first transistor T1 to the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 to the thirteenth transistor T13 can be made of amorphous silicon (a-Si), polycrystalline silicon (Poly-Si) or an oxide semiconductor.

[0174] Fig.10 It specifically shows Figure 8 An example plan view of area A.

[0175] Fig.10 The first carry connection line CRB1, the second carry connection line CRB2, the sensing connection line SEB, the scanning connection line SCB, the sensing control connection line SESB, the control connection line SCKB, the gate turn-on connection line VOB, the first gate turn-off connection line VFB1 and the second gate turn-off connection line VFB2 connected to the kth stage STk in the line area LA of the scan signal driving unit 200 are shown. In addition, Fig.10 Carry clock lines CRC1 to CRC3, sensing clock lines SEC1 to SEC4, scanning clock lines SCC1 to SCC4, sensing control line SES, control clock line SCK, gate-on voltage line VOL, first gate-off voltage line VFL1, and second gate-off voltage line VFL2 in the line area LA of the scan signal driving unit 200 are shown.

[0176] like Fig.10As shown in , the carry clock lines CRC1 to CRC3 can be set to be farthest from the kth stage STk in one direction DR2, and the sense clock lines SEC1 to SEC4 can be set to be the second farthest from the kth stage STk. In addition, the scan clock lines SCC1 to SCC4 can be set to be the third farthest from the kth stage STk, and the global signal lines such as the sense control line SES, the control clock line SCK, the gate turn-on voltage line VOL, the first gate turn-off voltage line VFL1 and the second gate turn-off voltage line VFL2 can be set to be closest to the kth stage STk. The global signal line refers to the line to which the signals commonly applied to the multiple stages STk-2 to STk+2 are applied.

[0177] Meanwhile, in this specification, in order to simplify the description, the carry clock lines CRC1 to CRC3 are defined as the first clock lines, and the global signal lines such as the sensing control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1 and the second gate-off voltage line VFL2 are defined as the second clock lines. In addition, the scan clock lines SCC1 to SCC4 are defined as the third clock lines, and the sensing clock lines SEC1 to SEC4 are defined as the fourth clock lines.

[0178] In addition, in this specification, in order to simplify the description, the first carry connection line CRB1 and the second carry connection line CRB2 are defined as the first connection line, and the global connection lines such as the sensing control connection line SESB, the control connection line SCKB, the gate turn-on connection line VOB, the first gate turn-off connection line VFB1 and the second gate turn-off connection line VFB2 are defined as the second connection line. In addition, the scan connection line SCB is defined as the third connection line, and the sensing connection line SEB is defined as the fourth connection line.

[0179] Reference Fig.10 , the carry clock lines CRC1 to CRC3, the sense clock lines SEC1 to SEC4, the scan clock lines SCC1 to SCC4, the sense control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2 may extend in one direction DR1. The first carry connection line CRB1, the second carry connection line CRB2, the sense connection line SEB, the scan connection line SCB, the sense control connection line SESB, the control connection line SCKB, the gate-on connection line VOB, the first gate-off connection line VFB1, and the second gate-off connection line VFB2 may extend in another direction DR2 crossing the one direction DR1.

[0180] Two of the carry clock lines CRC1 to CRC3 may be electrically connected to the kth stage STk. Fig.10As shown in, the first carry clock line CRC1 can be connected to the kth stage STk through the first carry connection line CRB1. The first carry clock line CRC1 can be connected to the first carry connection line CRB1 through the first carry contact hole CRT1. In addition, the third carry clock line CRC3 can be connected to the kth stage STk through the second carry connection line CRB2. The third carry clock line CRC3 can be connected to the second carry connection line CRB2 through the second carry contact hole CRT2. The first carry connection line CRB1 and the second carry connection line CRB2 can intersect with the sensing clock lines SEC1 to SEC4, the scanning clock lines SCC1 to SCC4, the sensing control line SES, the control clock line SCK, the gate turn-on voltage line VOL, the first gate turn-off voltage line VFL1 and the second gate turn-off voltage line VFL2.

[0181] At least one of the sensing clock lines SEC1 to SEC4 may be electrically connected to the kth stage STk. Fig.10 As shown in , the third sensing clock line SEC3 can be connected to the kth stage STk through the sensing connection line SEB. The third sensing clock line SEC3 can be connected to the sensing connection line SEB through the sensing contact hole SET. The sensing connection line SEB can cross the scan clock lines SCC1 to SCC4, the sensing control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2.

[0182] At least one of the scan clock lines SCC1 to SCC4 may be electrically connected to the kth stage STk. Fig.10 As shown in , the third scan clock line SCC3 can be connected to the kth stage STk through the scan connection line SCB. The third scan clock line SCC3 can be connected to the scan connection line SCB through the scan contact hole SCT. The scan connection line SCB can cross the sensing control line SES, the control clock line SCK, the gate turn-on voltage line VOL, the first gate turn-off voltage line VFL1 and the second gate turn-off voltage line VFL2.

[0183] The sensing control line SES may be connected to the kth stage STk through the sensing control connection line SESB. The sensing control line SES may be connected to the sensing control connection line SESB through the sensing control contact hole SEST. The sensing control connection line SESB may cross the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2.

[0184] The control clock line SCK may be connected to the kth stage STk through the control connection line SCKB. The control clock line SCK may be connected to the control connection line SCKB through the control clock contact hole SCKT. The control connection line SCKB may cross the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2.

[0185] The gate-on voltage line VOL may be connected to the kth stage STk through the gate-on connection line VOB. The gate-on voltage line VOL may be connected to the gate-on connection line VOB through the conduction contact hole VOT. The gate-on connection line VOB may cross the first gate-off voltage line VFL1 and the second gate-off voltage line VFL2.

[0186] The first gate-off voltage line VFL1 may be connected to the kth stage STk through the first gate-off link line VFB1. The first gate-off voltage line VFL1 may be connected to the first gate-off link line VFB1 through the first cut-off contact hole VFT1. The first gate-off link line VFB1 may cross the second gate-off voltage line VFL2.

[0187] The second gate-off voltage line VFL2 may be connected to the kth stage STk through the second gate-off link line VFB2. The second gate-off voltage line VFL2 may be connected to the second gate-off link line VFB2 through the second cutting contact hole VFT2.

[0188] Fig.11 It specifically shows Fig.10 An enlarged plan view of a first carry clock line and a first carry connection line. Fig.12 It specifically shows Fig.10 An enlarged plan view of the sensing control lines and the sensing control connecting lines. Fig.13 It specifically shows Fig.10 An enlarged plan view of a third scan clock line and a scan connection line. Fig.14 It specifically shows Fig.10 An enlarged plan view of a third sensing clock line and a sensing connection line.

[0189] Reference Fig.11 The first carry clock line CRC1 may include a plurality of metal patterns. For example, the first carry clock line CRC1 may have a three-layer structure including a 1-1th metal pattern MP11, a 1-2nd metal pattern MP12, and a 1-3rd metal pattern MP13 overlapped with each other.

[0190] The 1-2 metal pattern MP12 may be disposed on the 1-1 metal pattern MP11, and the 1-3 metal pattern MP13 may be disposed on the 1-2 metal pattern MP12. The 1-1 metal pattern MP11 may be connected to the 1-2 metal pattern MP12 through the first contact hole CT1, and the 1-2 metal pattern MP12 may be connected to the 1-3 metal pattern MP13 through the second contact hole CT2. The 1-2 metal pattern MP12 may be connected to the first carry connection wire CRB1 through the first carry contact hole CRT1. The 1-1 metal pattern MP11 may not overlap the first carry connection wire CRB1.

[0191] Although Fig.11 It is shown that the width W11 of the 1-1st metal pattern MP11 is greater than the width W12 of the 1-2nd metal pattern MP12, and the width W12 of the 1-2nd metal pattern MP12 is greater than the width W13 of the 1-3rd metal pattern MP13, but the present disclosure is not limited thereto. The width W11 of the 1-1st metal pattern MP11 may be substantially the same as the width W12 of the 1-2nd metal pattern MP12, and the width W12 of the 1-2nd metal pattern MP12 may be substantially the same as the width W13 of the 1-3rd metal pattern MP13.

[0192] Fig.10 The third carry clock line CRC3 and the second carry connection line CRB2 shown in FIG. Fig.11 The first carry clock line CRC1 and the first carry link line CRB1 are described to be substantially the same.

[0193] Reference Fig.12 The sensing control line SES may include a plurality of metal patterns. For example, the sensing control line SES may have a double-layered structure including a 2-1st metal pattern MP21 and a 2-2nd metal pattern MP22 overlapped with each other.

[0194] The 2-2nd metal pattern MP22 may be disposed on the 2-1st metal pattern MP21. The 2-1st metal pattern MP21 may be connected to the 2-2nd metal pattern MP12 through the third contact hole CT3. The 2-1st metal pattern MP21 may be connected to the sensing control connection line SESB through the sensing control contact hole SEST.

[0195] Although Fig.12 It is shown that the width W21 of the 2-1st metal pattern MP21 is greater than the width W22 of the 2-2nd metal pattern MP22, but the present disclosure is not limited thereto. The width W21 of the 2-1st metal pattern MP21 may be substantially the same as the width W22 of the 2-2nd metal pattern MP22.

[0196] Fig.10The control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1 and the second gate-off voltage line VFL2 shown in FIG. Fig.12 The sensing control line SES described is substantially the same. In addition, Fig.10 The control connection line SCKB, the gate turn-on connection line VOB, the first gate turn-off connection line VFB1 and the second gate turn-off connection line VFB2 shown in FIG. Fig.12 The sensing control connection lines SESB described are substantially the same.

[0197] Reference Fig.13 The third scan clock line SCC3 may include a plurality of metal patterns. For example, the third scan clock line SCC3 may have a three-layer structure including a 3-1st metal pattern MP31, a 3-2nd metal pattern MP32, and a 3-3rd metal pattern MP33 overlapped with each other.

[0198] The 3-2nd metal pattern MP32 may be disposed on the 3-1st metal pattern MP31, and the 3-3rd metal pattern MP33 may be disposed on the 3-2nd metal pattern MP32. The 3-1st metal pattern MP31 may be connected to the 3-2nd metal pattern MP32 through the fourth contact hole CT4, and the 3-2nd metal pattern MP32 may be connected to the 3-3rd metal pattern MP33 through the fifth contact hole CT5. The 3-2nd metal pattern MP32 may be connected to the scan connection line SCB through the scan contact hole SCT. The 3-1st metal pattern MP31 may not overlap the scan connection line SCB.

[0199] Although Fig.13 It is shown that the width W31 of the 3-1st metal pattern MP31 is wider than the width W32 of the 3-2nd metal pattern MP32, and the width W32 of the 3-2nd metal pattern MP32 is wider than the width W33 of the 3-3rd metal pattern MP33, but the present disclosure is not limited thereto. The width W31 of the 3-1st metal pattern MP31 may be substantially the same as the width W32 of the 3-2nd metal pattern MP32, and the width W32 of the 3-2nd metal pattern MP32 may be substantially the same as the width W33 of the 3-3rd metal pattern MP33.

[0200] Reference Fig.14 The third sensing clock line SEC3 may include a plurality of metal patterns. For example, the third sensing clock line SEC3 may have a three-layer structure including a 4-1st metal pattern MP41, a 4-2nd metal pattern MP42, and a 4-3rd metal pattern MP43 overlapped with each other.

[0201] The 4-2nd metal pattern MP42 may be disposed on the 4-1st metal pattern MP41, and the 4-3rd metal pattern MP43 may be disposed on the 4-2nd metal pattern MP42. The 4-1st metal pattern MP41 may be connected to the 4-2nd metal pattern MP42 through the sixth contact hole CT6, and the 4-2nd metal pattern MP42 may be connected to the 4-3rd metal pattern MP43 through the seventh contact hole CT7. The 4-2nd metal pattern MP42 may be connected to the sensing connection line SEB through the sensing contact hole SET. The 4-1st metal pattern MP41 may not overlap the sensing connection line SEB.

[0202] Although Fig.14 It is shown that the width W41 of the 4-1st metal pattern MP41 is wider than the width W42 of the 4-2nd metal pattern MP42, and the width W42 of the 4-2nd metal pattern MP42 is wider than the width W43 of the 4-3rd metal pattern MP43, but the present disclosure is not limited thereto. The width W41 of the 4-1st metal pattern MP41 may be substantially the same as the width W42 of the 4-2nd metal pattern MP42, and the width W42 of the 4-2nd metal pattern MP42 may be substantially the same as the width W43 of the 4-3rd metal pattern MP43.

[0203] according to Figures 11 to 14 In an embodiment, each of the carry clock lines CRC1 to CRC3, the sense clock lines SEC1 to SEC4, and the scan clock lines SCC1 to SCC4 may be formed as a three-layer structure including three metal patterns, and each of the sense control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2 may be formed as a two-layer structure including two metal patterns. As a result, the resistance value of each of the scan control lines may be reduced at ultra-high resolutions such as 8K UHD, which makes it possible to reduce the RC delay of the scan control lines.

[0204] Fig.15 It specifically shows Figure 4 A cross-sectional view of an example of a sub-pixel. Fig.16 It shows that along Fig.11 A cross-sectional view of the example taken along line II'. Fig.17 It shows that along Fig.12 A cross-sectional view of the example taken along line II-II'. Fig.18 It shows that along Fig.13 A cross-sectional view of the example taken along line III-III'. Fig.19 It shows that along Fig.14 A cross-sectional view of the example taken along line IV-IV'.

[0205] Reference Figures 15 to 19The substrate SUB may be made of an insulating material such as glass, quartz or polymer resin. The substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded or rolled.

[0206] A light blocking layer BML, a first carry link line CRB1 and a second carry link line CRB2, a scan link line SCB, a sensing link line SEB, a sensing control link line SESB, a control link line SCKB, a gate turn-on link line VOB, a first gate turn-off link line VFB1 and a second gate turn-off link line VFB2 may be formed on one surface of the substrate SUB. The light blocking layer BML as a layer for blocking light incident on the active area ACTA of the active layer DT_ACT of the driving transistor DT may overlap the active area ACTA of the active layer DT_ACT. The light blocking layer BML, the first carry connection line CRB1 and the second carry connection line CRB2, the scan connection line SCB, the sensing connection line SEB, the sensing control connection line SESB, the control connection line SCKB, the gate turn-on connection line VOB, the first gate turn-off connection line VFB1 and the second gate turn-off connection line VFB2 can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0207] The buffer layer BF may be formed on the light blocking layer BML. The buffer layer BF may be formed on one surface of the substrate SUB to protect the thin film transistor including the driving transistor DT and the organic light emitting layer 172 from moisture penetrating through the substrate SUB, which is susceptible to moisture penetration. The buffer layer BF may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be formed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer layer BF may be omitted.

[0208] The thin film transistor including the driving transistor DT is formed on the buffer layer BF. To simplify the description, Fig.15 Only the driving transistor DT among the thin film transistors is shown. The driving transistor DT includes an active layer DT_ACT, a gate electrode DT_G, a source electrode DT_S, and a drain electrode DT_D. Fig.15 It is exemplarily shown that the driving transistor DT is constructed as a top gate type in which the gate electrode DT_G is located on the top of the active layer DT_ACT, but it should be noted that the present disclosure is not limited thereto. That is, the driving transistor DT may be constructed as a bottom gate type in which the gate electrode DT_G is located below the active layer DT_ACT, or a dual gate type in which the gate electrode DT_G is located above and below the active layer DT_ACT.

[0209] The active layer DT_ACT is formed on the buffer layer BF. The active layer DT_ACT may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. For example, the oxide semiconductor may include a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D z ). For example, the active layer DT_ACT may include ITZO (oxide including indium, tin, and titanium) or IGZO (oxide including indium, gallium, and tin).

[0210] The active layer DT_ACT may include an active area ACTA, a source area SA, and a drain area DA. The active area ACTA as a semiconductor area serves as a channel of the driving transistor DT. The source area SA and the drain area DA as conductive areas may have conductivity.

[0211] The gate insulating layer 130 may be formed on a portion of the active layer DT_ACT and a portion of the buffer layer BF. The gate insulating layer 130 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The gate insulating layer 130 may be formed only in a region overlapping the gate electrode DT_G, the first capacitor electrode CE1, the 1-1st metal pattern MP11, the 3-1st metal pattern MP31, and the 4-1st metal pattern MP41.

[0212] The gate electrode DT_G, the first capacitor electrode CE1, the 1-1st metal pattern MP11 of each of the carry clock lines CRC1 to CRC3, the 3-1st metal pattern MP31 of each of the scan clock lines SCC1 to SCC4, and the 4-1st metal pattern MP41 of each of the sense clock lines SEC1 to SEC4 may be formed on the gate insulating layer 130. The gate electrode DT_G, the first capacitor electrode CE1, the 1-1st metal pattern MP11, the 3-1st metal pattern MP31, and the 4-1st metal pattern MP41 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0213] The interlayer insulating layer 140 may be formed on the gate electrode DT_G, the first capacitor electrode CE1, the 1-1st metal pattern MP11 of each of the carry clock lines CRC1 to CRC3, the 3-1st metal pattern MP31 of each of the scan clock lines SCC1 to SCC4, and the 4-1st metal pattern MP41 of each of the sense clock lines SEC1 to SEC4. The interlayer insulating layer 140 may include a first interlayer insulating layer 141 and a second interlayer insulating layer 142. The first interlayer insulating layer 141 and the second interlayer insulating layer 142 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0214] The source electrode DT_S, the drain electrode DT_D, and the second capacitor electrode CE2 may be formed on the interlayer insulating layer 140. In addition, the 1st-2nd metal pattern MP12 of each of the carry clock lines CRC1 to CRC3, the 3rd-2nd metal pattern MP32 of each of the scan clock lines SCC1 to SCC4, and the 4th-2nd metal pattern MP42 of each of the sensing clock lines SEC1 to SEC4 may be formed on the interlayer insulating layer 140. In addition, the 2nd-1st metal pattern MP21 of each of the sensing control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2 may be formed on the interlayer insulating layer 140. The source electrode DT_S, the drain electrode DT_D, the 1st-2nd metal pattern MP12, the 3rd-2nd metal pattern MP32, the 4th-2nd metal pattern MP42 and the 2nd-1st metal pattern MP21 can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0215] like Fig.15 As shown in FIG. 1 , the source electrode DT_S may be connected to the source area SA of the active layer DT_ACT through a contact hole penetrating the interlayer insulating layer 140 . The drain electrode DT_D may be connected to the drain area DA of the active layer DT_ACT through a contact hole penetrating the interlayer insulating layer 140 .

[0216] like Fig.16 As shown in FIG, the 1-2 metal pattern MP12 of the first carry clock line CRC1 may be connected to the first carry connection line CRB1 through a first carry contact hole CRT1 penetrating the buffer layer BF and the interlayer insulating layer 140. The 1-2 metal pattern MP12 of the first carry clock line CRC1 may be connected to the 1-1 metal pattern MP11 through a first contact hole CT1 penetrating the interlayer insulating layer 140.

[0217] like Fig.17As shown in FIG. 1 , the 2-1 th metal pattern MP21 of the sensing control line SES may be connected to the sensing control connection line SESB through a sensing control contact hole SEST penetrating the buffer layer BF and the interlayer insulating layer 140 .

[0218] like Fig.18 As shown in FIG. 1 , the 3-2 metal pattern MP32 of the third scan clock line SCC3 may be connected to the scan connection line SCB through a scan contact hole SCT penetrating the buffer layer BF and the interlayer insulating layer 140. The 3-2 metal pattern MP32 of the third scan clock line SCC3 may be connected to the 3-1 metal pattern MP31 through a fourth contact hole CT4 penetrating the interlayer insulating layer 140.

[0219] like Fig.19 As shown in FIG. 1 , the 4-2 metal pattern MP42 of the third sensing clock line SEC3 may be connected to the sensing connection line SEB through the sensing contact hole SET penetrating the buffer layer BF and the interlayer insulating layer 140. The 4-2 metal pattern MP42 of the third sensing clock line SEC3 may be connected to the 4-1 metal pattern MP41 through the sixth contact hole CT6 penetrating the interlayer insulating layer 140.

[0220] A passivation layer 159 for insulating the thin film transistor may be formed on the source electrode DT_S and the drain electrode DT_D. The passivation layer 159 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0221] A planarization layer 160 for planarizing a stepped portion formed by a thin film transistor may be formed on the passivation layer 159. The planarization layer 160 may include a first planarization layer 161 and a second planarization layer 162. The first planarization layer 161 and the second planarization layer 162 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0222] The anode connection electrode ANDE may be formed on the first planarization layer 161. In addition, a 1st-3rd metal pattern MP13 of each of the carry clock lines CRC1 to CRC3, a 3rd-3rd metal pattern MP33 of each of the scan clock lines SCC1 to SCC4, and a 4th-3rd metal pattern MP43 of each of the sensing clock lines SEC1 to SEC4 may be formed on the first planarization layer 161. In addition, a 2nd-2nd metal pattern MP22 of each of the sensing control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2 may be formed on the first planarization layer 161.

[0223] like Fig.15As shown in , the anode connection electrode ANDE may be connected to the source electrode DT_S or the drain electrode DT_D through a contact hole penetrating the passivation layer 159 and the first planarization layer 161. Fig.16 As shown in FIG. 1 , the 1-3 metal pattern MP13 of the first carry clock line CRC1 may be connected to the 1-2 metal pattern MP12 through the second contact hole CT2 penetrating the passivation layer 159 and the first planarization layer 161. Fig.17 As shown in FIG. 1 , the 2-2 metal pattern MP22 of the sensing control line SES may be connected to the 2-1 metal pattern MP21 through the third contact hole CT3 penetrating the passivation layer 159 and the first planarization layer 161. Fig.18 As shown in FIG. 1 , the 3-3rd metal pattern MP33 of the third scan clock line SCC3 may be connected to the 3-2nd metal pattern MP32 through the fifth contact hole CT5 penetrating the passivation layer 159 and the first planarization layer 161. Fig.19 As shown in FIG. 1 , the 4-3 th metal pattern MP43 of the third sensing clock line SEC3 may be connected to the 4-2 th metal pattern MP42 through the seventh contact hole CT7 penetrating the passivation layer 159 and the first planarization layer 161 .

[0224] The anode connecting electrode ANDE, the 1st-3rd metal pattern MP13, the 2nd-2nd metal pattern MP22, the 3rd-3rd metal pattern MP33 and the 4th-3rd metal pattern MP43 can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0225] The first electrode 171 and the pixel defining layer 180 are formed on the second planarization layer 162. The first electrode 171 can be connected to the anode connection electrode ANDE through a contact hole penetrating the second planarization layer 162. In a top emission structure in which light is emitted toward the second electrode 173 when viewed relative to the organic light emitting layer 172, the first electrode 171 can be formed of a metal material with high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu). Alternatively, in a bottom emission structure in which light is emitted toward the first electrode 171 when viewed relative to the organic light emitting layer 172, the first electrode 171 may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In this case, when the first electrode 171 is formed of a semi-transmissive metal material, the light emitting efficiency may be increased due to the microcavity effect.

[0226] The pixel defining layer 180 may be formed to cover the edge of the first electrode 171 on the second planarization layer 162 so as to define an emission region. Each of the emission regions refers to a region in which the first electrode 171, the organic light emitting layer 172, and the second electrode 173 are sequentially stacked and holes from the first electrode 171 and electrons from the second electrode 173 are combined with each other in the organic light emitting layer 172 to emit light. The pixel defining layer 180 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0227] The organic light emitting layer 172 may be disposed on the first electrode 171 and the pixel defining layer 180. The organic light emitting layer 172 may include an organic material to emit light of a predetermined color. For example, the organic light emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic light emitting layer 172 may be a common layer generally formed in the emission region.

[0228] The second electrode 173 is formed on the organic light-emitting layer 172. The second electrode 173 may be formed to cover the organic light-emitting layer 172. The second electrode 173 may be a common layer generally formed in the emission region. A cap layer may be formed on the second electrode 173. In the top emission structure, the second electrode 173 may be formed of a transparent conductive material (TCO) (such as ITO or IZO) capable of transmitting light or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag) or an alloy of magnesium (Mg) and silver (Ag)). When the second electrode 173 is formed of a semi-transmissive metal material, the luminous efficiency may be increased due to the microcavity effect. Alternatively, in the bottom emission structure, the second electrode 173 may be formed of a metal material with high reflectivity (such as a stacked structure (Ti / Al / Ti) of aluminum (Al) and titanium (Ti), a stacked structure (ITO / Al / ITO) of Al and ITO, an APC alloy, a stacked structure (ITO / APC / ITO) of an APC alloy and ITO, etc.). APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu).

[0229] The encapsulation layer 190 is formed on the second electrode 173. The encapsulation layer 190 is disposed on the second electrode 173. The encapsulation layer 190 may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the organic light-emitting layer 172 and the second electrode 173. In addition, the encapsulation layer 190 may include at least one organic layer to protect the light-emitting element layer from foreign matter such as dust. For example, the encapsulation layer 190 may include a first inorganic layer disposed on the second electrode 173, an organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the organic layer. The first inorganic layer and the second inorganic layer may be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not limited thereto. The organic layer may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc., but is not limited thereto.

[0230] At the same time, the 1-1st metal pattern MP11, the 3-1st metal pattern MP31, and the 4-1st metal pattern MP41 are arranged at the same layer as the gate electrode DT_G, and the 1-2nd metal pattern MP12, the 3-2nd metal pattern MP32, and the 4-2nd metal pattern MP42 are arranged at the same layer as the source electrode DT_S. In addition, the 1-3rd metal pattern MP13, the 3-3rd metal pattern MP33, and the 4-3rd metal pattern MP43 are arranged at the same layer as the drain electrode DT_D, and the first carry connection line CRB1, the second carry connection line CRB2, the sense connection line SEB, and the scan connection line SCB are arranged at the same layer as the light blocking layer BML. In this case, the distance between the gate electrode DT_G and the light blocking layer BML is smaller than the distance between the source electrode DT_S and the light blocking layer BML and the distance between the drain electrode DT_D and the light blocking layer BML. Therefore, in order to reduce the size of parasitic capacitance generated in the area where the first carry link line CRB1, the second carry link line CRB2, the sense link line SEB, and the scan link line SCB overlap with the carry clock lines CRC1 to CRC3, the sense clock lines SEC1 to SEC4, and the scan clock lines SCC1 to SCC4, each of the 1-1st metal pattern MP11, the 3-1st metal pattern MP31, and the 4-1st metal pattern MP41 may not overlap with at least one of the first carry link line CRB1, the second carry link line CRB2, the sense link line SEB, and the scan link line SCB. Therefore, the resistance value of each of the scan control lines can be reduced at an ultra-high resolution such as 8K UHD, which makes it possible to reduce the RC delay of the scan control lines.

[0231] Fig. 20 It shows that along Fig.11 A cross-sectional view of the example taken along line II'. Fig.21 It shows that along Fig.12 A cross-sectional view of the example taken along line II-II'. Fig. 22 It shows that along Fig.13 A cross-sectional view of the example taken along line III-III'. Fig.23 It shows that along Fig.14 A cross-sectional view of the example taken along line IV-IV'.

[0232] Figure 20 to Figure 23 Examples and Figures 16 to 19 The embodiment shown in FIG. 1 is different in that the 1st-2nd metal pattern MP12 of each of the carry clock lines CRC1 to CRC3, the 3rd-2nd metal pattern MP32 of each of the scan clock lines SCC1 to SCC4, and the 4th-2nd metal pattern MP42 of each of the sense clock lines SEC1 to SEC4 are formed on the first interlayer insulating layer 141 instead of the second interlayer insulating layer 142. In addition, Figure 20 to Figure 23Examples and Figures 16 to 19 The difference between the embodiment shown in FIG. 1 and FIG. 2 is that the 2-1st metal pattern MP21 of each of the sensing control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1 and the second gate-off voltage line VFL2 is formed on the first interlayer insulating layer 141 instead of the second interlayer insulating layer 142.

[0233] like Fig. 20 As shown in FIG, the 1-2 metal pattern MP12 of the first carry clock line CRC1 may be connected to the first carry connection line CRB1 through a first carry contact hole CRT1 penetrating the buffer layer BF and the first interlayer insulating layer 141. The 1-2 metal pattern MP12 of the first carry clock line CRC1 may be connected to the 1-1 metal pattern MP11 through a first contact hole CT1 penetrating the first interlayer insulating layer 141.

[0234] like Fig.21 As shown in , the 2-1 th metal pattern MP21 of the sensing control line SES may be connected to the sensing control connection line SESB through a sensing control contact hole SEST penetrating the buffer layer BF and the first interlayer insulating layer 141 .

[0235] like Fig. 22 As shown in FIG. 1 , the 3-2 metal pattern MP32 of the third scan clock line SCC3 may be connected to the scan connection line SCB through a scan contact hole SCT penetrating the buffer layer BF and the first interlayer insulating layer 141. The 3-2 metal pattern MP32 of the third scan clock line SCC3 may be connected to the 3-1 metal pattern MP31 through a fourth contact hole CT4 penetrating the first interlayer insulating layer 141.

[0236] like Fig.23 As shown in FIG. 1 , the 4-2 metal pattern MP42 of the third sensing clock line SEC3 may be connected to the sensing connection line SEB through the sensing contact hole SET penetrating the buffer layer BF and the first interlayer insulating layer 141. The 4-2 metal pattern MP42 of the third sensing clock line SEC3 may be connected to the 4-1 metal pattern MP41 through the sixth contact hole CT6 penetrating the first interlayer insulating layer 141.

[0237] Fig.24 It specifically shows Fig.10 An enlarged plan view of a third scan clock line and a scan connection line. Fig.25 It specifically shows Fig.10 An enlarged plan view of a third sensing clock line and a sensing connection line.

[0238] like Fig.24As shown in , the 3-1st metal pattern MP31 of each of the scan clock lines SCC1 to SCC4 may overlap the first carry link line CRB1, the second carry link line CRB2, and the sensing link line SEB. In this case, in order to reduce the size of the parasitic capacitance, in the area overlapping with the first carry link line CRB1, the second carry link line CRB2, and the sensing link line SEB, the width W34 of the 3-1st metal pattern MP31 of the third scan clock line SCC3 may be formed to be smaller than the width W33 of the 3-3rd metal pattern MP33.

[0239] like Fig.25 As shown in , the 4-1st metal pattern MP41 of each of the sensing clock lines SEC1 to SEC4 may overlap with the first carry link line CRB1 and the second carry link line CRB2. In this case, in order to reduce the size of the parasitic capacitance, in the region overlapping with the first carry link line CRB1 and the second carry link line CRB2, the width W44 of the 4-1st metal pattern MP41 of the third sensing clock line SEC3 may be formed to be smaller than the width W43 of the 4-3rd metal pattern MP43.

[0240] Fig.26 It specifically shows Fig.10 An enlarged plan view of a first carry clock line and a first carry connection line. Fig. 27 It specifically shows Fig.10 An enlarged plan view of the sensing control lines and sensing connection lines. Fig.28 It specifically shows Fig.10 An enlarged plan view of a third scan clock line and a scan connection line. Fig.29 It specifically shows Fig.10 An enlarged plan view of a third sensing clock line and a sensing connection line.

[0241] Fig.26 Examples and Fig.11 The embodiment shown in FIG. 1 is different in that each of the carry clock lines CRC1 to CRC3 has a double-layer structure including a 1-1th metal pattern MP11 and a 1-2th metal pattern MP12 .

[0242] Fig. 27 Examples and Fig.12 The embodiment shown in FIG. 1 is different in that each of the sensing control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2 has a single-layer structure including the 2-1st metal pattern MP21.

[0243] Fig.28 Examples and Fig.13The embodiment shown in FIG. 4 is different in that each of the scan clock lines SCC1 to SCC4 has a double-layer structure including a 3-1st metal pattern MP31 and a 3-2nd metal pattern MP32.

[0244] Fig.29 Examples and Fig.14 The embodiment shown in FIG. 4 is different in that each of the sensing clock lines SEC1 to SEC4 has a double-layer structure including a 4-1st metal pattern MP41 and a 4-2nd metal pattern MP42 .

[0245] Fig.30 It shows in detail Figure 4 A cross-sectional view of an example of a sub-pixel. Fig.31 It shows that along Fig.26 A cross-sectional view of the example taken along line II'. Fig.32 It shows that along Fig. 27 A cross-sectional view of the example taken along line II-II'. Fig.33 It shows that along Fig.28 A cross-sectional view of the example taken along line III-III'. Fig.34 It shows that along Fig.29 A cross-sectional view of the example taken along line IV-IV'.

[0246] Figure 30 to Figure 34 Examples and Figures 15 to 19 The embodiment differs in that the source electrode DT_S and the drain electrode DT_D of the driving transistor DT are formed at the same layer as the gate electrode DT_G, the second capacitor electrode CE2 is formed at the same layer as the light blocking layer BML, and the first electrode 171 is connected to the light blocking layer BML.

[0247] Reference Figure 30 to Figure 34 A light blocking layer BML, a second capacitor electrode CE2, and a 1-1th metal pattern MP11 of each of the carry clock lines CRC1 to CRC3, a 3-1th metal pattern MP31 of each of the scan clock lines SCC1 to SCC4, and a 4-1th metal pattern MP41 of each of the sense clock lines SEC1 to SEC4 may be formed on one surface of the substrate SUB. A buffer layer BF may be formed on the light blocking layer BML, the second capacitor electrode CE2, the 1-1th metal pattern MP11, the 3-1th metal pattern MP31, and the 4-1th metal pattern MP41.

[0248] The active layer DT_ACT, the first carry connection line CRB1 and the second carry connection line CRB2, the scan connection line SCB, the sensing connection line SEB, the sensing control connection line SESB, the control connection line SCKB, the gate turn-on connection line VOB, the first gate turn-off connection line VFB1 and the second gate turn-off connection line VFB2 may be formed on the buffer layer BF. The first carry connection line CRB1 and the second carry connection line CRB2, the scan connection line SCB, the sensing connection line SEB, the sensing control connection line SESB, the control connection line SCKB, the gate turn-on connection line VOB, the first gate turn-off connection line VFB1 and the second gate turn-off connection line VFB2 may be made conductive and have conductivity.

[0249] like Fig.31 As shown in FIG. 1 , the 1-1 metal pattern MP11 of the first carry clock line CRC1 may be connected to the first carry connection line CRB1 through the first carry contact hole CRT1 penetrating the buffer layer BF. Fig.32 As shown in FIG. 1 , the 2-1 metal pattern MP21 of the sensing control line SES may be connected to the sensing control connection line SESB through the sensing control contact hole SEST penetrating the buffer layer BF. Fig.33 As shown in FIG. 1 , the 3-2 metal pattern MP32 of the third scan clock line SCC3 may be connected to the scan connection line SCB through a scan contact hole SCT penetrating the buffer layer BF. Fig.34 As shown in FIG. 4 , the 4-1 th metal pattern MP41 of the third sensing clock line SEC3 may be connected to the sensing connection line SEB through the sensing contact hole SET penetrating the buffer layer BF.

[0250] The gate electrode DT_G, the source electrode DT_S, the drain electrode DT_D, the first capacitor electrode CE1, and the 1st-2nd metal pattern MP12 of each of the carry clock lines CRC1 to CRC3, the 3rd-2nd metal pattern MP32 of each of the scan clock lines SCC1 to SCC4, and the 4th-2nd metal pattern MP42 of each of the sensing clock lines SEC1 to SEC4 may be formed on the gate insulating layer 130. In addition, the 2nd-1st metal pattern MP21 of each of the sensing control line SES, the control clock line SCK, the gate-on voltage line VOL, the first gate-off voltage line VFL1, and the second gate-off voltage line VFL2 may be formed on the gate insulating layer 130. The first planarizing layer 161 may be formed on the gate electrode DT_G, the first capacitor electrode CE1, the 1st-2nd metal pattern MP12, the 3rd-2nd metal pattern MP32, the 4th-2nd metal pattern MP42, and the 2nd-1st metal pattern MP21.

[0251] like Fig.30As shown in , the source electrode DT_S may be connected to the light blocking layer BML through a contact hole penetrating the buffer layer BF and the gate insulating layer 130, and the first capacitor electrode CE1 may be disposed to overlap the second capacitor electrode CE2. Fig.31 As shown in , the 1-2 metal pattern MP12 of the first carry clock line CRC1 may be connected to the 1-1 metal pattern MP11 through a first contact hole CT1 penetrating the gate insulating layer 130 and the buffer layer BF. Fig.33 As shown in FIG. 1 , the 3-2 metal pattern MP32 of the third scan clock line SCC3 may be connected to the 3-1 metal pattern MP31 through a fourth contact hole CT4 penetrating the gate insulating layer 130 and the buffer layer BF. Fig.34 As shown in FIG. 1 , the 4-2 th metal pattern MP42 of the third sensing clock line SEC3 may be connected to the 4-1 th metal pattern MP41 through a sixth contact hole CT6 penetrating the gate insulating layer 130 and the buffer layer BF.

[0252] The first electrode 171 and the pixel defining layer 180 may be formed on the first planarization layer 161. Fig.30 As shown in , the first electrode 171 may be connected to the light blocking layer BML through a contact hole penetrating the buffer layer BF, the gate insulating layer 130 , and the first planarization layer 161 .

[0253] according to Figure 30 to Figure 34 According to the embodiment, a display device can be manufactured while minimizing the number of photomask processes, so that the manufacturing cost can be reduced.

[0254] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may implement the present invention in other specific forms without changing the technical spirit or basic features of the present invention. Therefore, it should be understood that the above embodiments are illustrative and not restrictive in all aspects.

Claims

1. A scanning signal driving unit, the scanning signal driving unit comprising: a plurality of stages configured to sequentially output scanning signals; a first clock line to which a first clock signal is applied; as well as a second clock line to which a second clock signal is applied, Each of the first clock lines includes a 1-1 metal pattern, a 1-2 metal pattern disposed on the 1-1 metal pattern, and a 1-3 metal pattern disposed on the 1-2 metal pattern, and Each of the second clock lines includes a 2-1st metal pattern and a 2-2nd metal pattern respectively disposed at the same layer as the 1-2nd metal pattern and the 1-3rd metal pattern.

2. The scanning signal driving unit according to claim 1, wherein: A minimum distance between one of the plurality of stages and one of the first clock lines is greater than a minimum distance between one of the plurality of stages and one of the second clock lines.

3. The scanning signal driving unit according to claim 1, further comprising: a first connection line configured to connect the plurality of stages and the first clock line; as well as The second connection line is configured to connect the plurality of stages and the second clock line.

4. The scanning signal driving unit according to claim 3, wherein: The length of one of the first connecting lines is longer than the length of one of the second connecting lines.

5. The scanning signal driving unit according to claim 3, wherein: One of the first connection lines overlaps the 1-2 metal pattern of one of the first clock lines and does not overlap the 1-1 metal pattern of the first clock line.

6. The scanning signal driving unit according to claim 1, wherein: One of the first connection lines overlaps the 1st to 3rd metal patterns of one of the first clock lines.

7. The scan signal driving unit according to claim 3, further comprising a third clock line to which a third clock signal is applied, in, Each of the third clock lines includes a 3-1st metal pattern disposed at the same layer as the 1-1st metal pattern and a 3-2nd metal pattern disposed at the same layer as the 1-2nd metal pattern.

8. The scanning signal driving unit according to claim 7, wherein: A minimum distance between one of the plurality of stages and one of the third clock lines is greater than a minimum distance between one of the plurality of stages and one of the second clock lines. 9 . The scan signal driving unit of claim 7 , further comprising a third connection line configured to connect the plurality of stages and the third clock line.

10. The scanning signal driving unit according to claim 9, wherein: A length of one of the third connecting lines is longer than a length of the second connecting line.

11. The scanning signal driving unit according to claim 9, wherein: One of the third connection lines overlaps the 3-2 th metal pattern of one of the third clock lines and does not overlap the 3-1 th metal pattern of the third clock line.

12. The scanning signal driving unit according to claim 9, wherein: Each of the third clock lines includes a 3-3rd metal pattern disposed on the 3-1st metal pattern.

13. The scanning signal driving unit according to claim 12, wherein: One of the third connection lines overlaps the 3-3 th metal pattern of one of the third clock lines.

14. A display device, comprising: A display panel comprising data lines, scanning signal lines and sensing signal lines crossing the data lines, and pixels connected to the data lines, the scanning signal lines and the sensing signal lines; a data driver configured to apply a data voltage to the data line; as well as a scanning signal driving unit including a plurality of stages configured to sequentially apply scanning signals to the scanning signal lines and sequentially apply sensing signals to the sensing signal lines, Wherein, the scanning signal driving unit further includes: a first clock line to which a first clock signal is applied; and a second clock line to which a second clock signal is applied, Each of the first clock lines includes a 1-1 metal pattern, a 1-2 metal pattern disposed on the 1-1 metal pattern, and a 1-3 metal pattern disposed on the 1-2 metal pattern, and Each of the second clock lines includes a 2-1st metal pattern and a 2-2nd metal pattern respectively disposed at the same layer as the 1-2nd metal pattern and the 1-3rd metal pattern.

15. The display device according to claim 14, wherein: Each of the pixels includes at least one thin film transistor, and The thin film transistor comprises: light blocking layer; an active layer, disposed on the light blocking layer and comprising an active region, a source region and a drain region; A gate electrode, disposed on the active layer; a source electrode disposed on the gate electrode and connected to the source region; and A drain electrode is disposed on the gate electrode and connected to the drain region.

16. The display device according to claim 15, wherein: The 1-1 metal pattern and the gate electrode are disposed at the same layer, and the 1-2 metal pattern and the source electrode are disposed at the same layer.

17. The display device according to claim 15, wherein: The 1-1 metal pattern and the gate electrode are disposed at the same layer, and the 1-2 metal pattern is disposed between the gate electrode and the source electrode.

18. The display device according to claim 14, wherein: Each of the pixels includes at least one thin film transistor, and The thin film transistor comprises: a source electrode and a drain electrode; an active layer, disposed on the source electrode and the drain electrode, the active layer comprising an active region, a source region and a drain region; and The gate electrode is arranged on the active layer.

19. The display device according to claim 18, wherein: The 1-1 metal pattern is disposed on the same layer as the source electrode and the drain electrode, and the 1-2 metal pattern is disposed on the same layer as the gate electrode.

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