Semiconductor device and manufacturing method thereof
By adopting a stacked structure and a vertical columnar structure in a three-dimensional memory device, combined with edge block materials with low resistance values, the problem of insufficient storage capacity and density in the prior art is solved, and efficient storage performance is achieved.
Patent Information
- Application Number
- CN202311300352.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-11
- Filing Date
- 2023-10-09
- Publication Date
- 2025-03-11
AI Technical Summary
Existing three-dimensional memory devices are difficult to achieve high component density and small size storage capacity requirements in limited space.
A stacked structure is adopted, including an insulating layer and a conductive layer arranged alternately, and a vertical columnar structure is provided in the conductive layer, including a conductive core, a shell electrode and an OTS layer. The edge block material of the conductive layer has a low resistance value, which is used to reduce the overall resistance value.
High component density and small size memory capacity are achieved, the resistance value of the conductive layer is reduced, and the performance of the memory is improved.
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Figure CN119603974A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. Background Art
[0002] In recent years, as the structure of semiconductor devices has evolved, the storage capacity of these semiconductor devices has also increased. Memory devices are often used in storage components of electronic products such as digital cameras, mobile phones, and computers. As the application field expands, the demand for memory devices is also developing towards small size and large capacity. In order to meet these needs, a high component density and small size memory device and a corresponding manufacturing method are needed.
[0003] In order to increase the capacity of memory in a limited space, a three-dimensional (3D) memory has been developed. In some 3D memory technologies, vertical channel structures are set in each operating area (block) and arranged in rows. In each operating area, multiple horizontal word lines are formed by stacking conductive layers. These word lines intersect these vertical channel structures in the operating area. Therefore, this type of 3D memory is also called a gate-all-around memory cell. Summary of the invention
[0004] According to one aspect of the present disclosure, a semiconductor device is provided, comprising a stack and a plurality of vertical columnar structures. The stack comprises a plurality of insulating layers and conductive layers arranged alternately, each conductive layer comprises a central block and an edge block located at the edge of the central block, wherein the resistance value of the material of the edge block is lower than the resistance value of the material of the central block. The vertical columnar structures are arranged in the stack, each vertical columnar structure comprises a conductive core, a shell electrode arranged on the sidewall of the conductive core, and an ovonic threshold switch (OTS) layer arranged on the sidewall of the shell electrode.
[0005] In some embodiments, the central block directly contacts the OTS layer of the vertical columnar structures, and the central block continuously extends between the vertical columnar structures.
[0006] In some embodiments, the material of the central block includes TiN, carbon, graphene, doped carbon, W, WN, or TaN.
[0007] In some embodiments, the material of the edge block includes TiN, TaN, Co, CoSix, Ni, NiSix, Ru, W, WN, or a combination thereof.
[0008] In some embodiments, the electrical resistance of the material of the conductive core is lower than the electrical resistance of the material of the shell electrode.
[0009] In some embodiments, the stack includes an array region and a stepped region extending from the array region, wherein the length of the conductive layer and the insulating layer thereunder decreases from bottom to top along a first direction, wherein edge blocks of the conductive layer are disposed on opposite sides of the central block and extend along the first direction.
[0010] In some embodiments, the edge block surrounds the center block.
[0011] In some embodiments, the edge blocks enter the center block.
[0012] Another aspect of the present disclosure is a method for manufacturing a semiconductor device, comprising the following steps: forming a stack, the stack comprising a plurality of insulating layers and a plurality of first conductive material layers arranged alternately. Then, forming a vertical columnar structure in an array region of the stack, the vertical columnar structure comprising a conductive core, a shell electrode disposed on a sidewall of the conductive core, and an ovonic threshold switch (OTS) layer disposed on a sidewall of the shell electrode. Then, forming an edge portion on a sidewall of the first conductive material layer, the material of the edge portion being a second conductive material, wherein the resistance value of the second conductive material is lower than the resistance value of the first conductive material layer.
[0013] In some embodiments, the method further includes selectively growing a plurality of landing pad portions on the first conductive material layer in the stepped region of the stack; and forming a plurality of contacts respectively connected to the landing pad portions in the stepped region.
[0014] According to some embodiments of the present disclosure, manufacturing a semiconductor device includes first depositing a stack formed by a first conductive material layer and an insulating layer, and then the first conductive material layer is not completely replaced by a second conductive material. More specifically, only a portion at the edge of the first conductive material layer is replaced by the second conductive material. In this way, the difficulty of manufacturing a conductive layer as a gate structure of a semiconductor device is reduced, and because the second conductive material is selected from a material with a lower resistance value, the overall resistance value of the conductive layer is also reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] To make the purpose, features, advantages and embodiments of the present disclosure more clearly understood, the detailed description of the accompanying drawings is as follows:
[0016] Figure 1 is a perspective view of a semiconductor device according to some embodiments of the present disclosure.
[0017] Figure 2 Along Figure 1 Cross-section view of line segment AA in .
[0018] Figure 3 Along Figure 1Cross-section of line segment BB in .
[0019] Figure 4 Along Figure 1 Cross-sectional view of line segment CC in .
[0020] Figures 5 to 11 They are cross-sectional views of a method for manufacturing a semiconductor device at different manufacturing stages according to some embodiments of the present disclosure.
[0021] Fig.12 is a perspective view of a semiconductor device according to some embodiments of the present disclosure.
[0022] Fig.13 and Fig.14 Each of the above is a top view of a conductive layer in a semiconductor device according to different embodiments of the present disclosure.
[0023] Description of Reference Numerals
[0024] 10: Operation area
[0025] 12: Array area
[0026] 14: Stepped area
[0027] 100, 100A: Semiconductor device
[0028] 110: Insulation layer
[0029] 112: Hard mask layer
[0030] 115: Insulation spacer
[0031] 120: Conductive layer
[0032] 122: Word plane
[0033] 123: Landing pad section
[0034] 124: Landing Pad
[0035] 130: Central block
[0036] 130': first conductive material layer
[0037] 140: Edge Block
[0038] 140': Second conductive material
[0039] 150: Covering layer
[0040] 160: Contact
[0041] 170: Dielectric layer
[0042] 180: Interval
[0043] 200: Vertical columnar structure
[0044] 210: Conductive core
[0045] 220: Shell electrode
[0046] 230: OTS layer
[0047] AA,BB,CC: Line segment
[0048] D1: First direction
[0049] D2: Second direction
[0050] t1, t2: thickness
[0051] r: diameter
[0052] S1, S2: Slits DETAILED DESCRIPTION
[0053] The spirit of the present disclosure will be clearly illustrated below with accompanying drawings and detailed descriptions. Any person skilled in the art in the relevant technical field, after understanding the preferred embodiments of the present disclosure, can make changes and modifications based on the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure.
[0054] Reference Figures 1 to 4 ,in Figure 1 is a perspective view of a semiconductor device according to some embodiments of the present disclosure, Figure 2 Along Figure 1 The cross-section of line segment AA in Figure 3 Along Figure 1 The cross-section of line segment BB in Figure 4 Along Figure 1 Please note that in order to make the figure clearer, Figure 1 Some components are hidden.
[0055] The semiconductor device 100 is related to a gate-all-around (GAA) memory cell, and more particularly to an ovonic threshold switch (OTS) type memory cell. The semiconductor device 100 includes a stack formed by alternating a plurality of insulating layers 110 and a plurality of conductive layers 120, and a plurality of vertical columnar structures 200 passing through the stack of the insulating layers 110 and the conductive layers 120. An operating area 10 of the semiconductor device 100 includes an array region 12 and a stepped region 14. The vertical columnar structures 200 are disposed in the array region 12. Each vertical columnar structure 200 includes a conductive core 210, a shell electrode 220, and an ovonic threshold switch (OTS) layer 230, wherein the shell electrode 220 covers the sidewall of the conductive core 210, and the OTS layer 230 covers the sidewall of the shell electrode 220. In some embodiments, the cross-section of the conductive core 210 in the top view is circular, and the cross-section of the shell electrode 220 and the OTS layer 230 in the top view is annular.
[0056] The conductive layer 120 extends from the array region 12 to the stepped region 14. The length of the conductive layer 120 and the insulating layer 110 thereunder gradually decreases from bottom to top to form the stepped region 14. The conductive layer 120 in the array region 12 serves as a word plane 122 of the vertical columnar structure 200, and the conductive layer 120 in the stepped region 14 serves as a landing pad 124 for internal connection.
[0057] Each conductive layer 120 includes a central block 130 and a plurality of edge blocks 140. The central block 130 surrounds the vertical columnar structure 200 and extends continuously between the vertical columnar structures 200. The edge blocks 140 are disposed on the side surfaces of the central block 130. The material of the edge blocks 140 in the conductive layer 120 is different from the material of the central block 130 in the conductive layer 120. For example, the resistance value of the material of the edge blocks 140 is lower than the resistance value of the material of the central block 130.
[0058] like Figure 2 As shown, the length of the conductive layer 120 and the insulating layer 110 thereunder changes gradually in the first direction D1, and no edge block 140 is formed in the second direction D2 perpendicular to the first direction D1. Figure 3 and Figure 4 As shown, the edge area 140 is formed on two opposite sides of the array region 12 and the stepped region 14 in the first direction D1 .
[0059] The semiconductor device 100 further includes a capping layer 150 disposed on the array region 12 to seal the memory cells. The semiconductor device 100 further includes a plurality of contacts 160 disposed on the stepped region 14 and connected to corresponding landing pads 124, respectively.
[0060] Optionally, in some embodiments, in order to avoid the phenomenon of unexpected breakdown of the conductive layer 120 when making the opening of the contact 160, an additional landing pad portion 123 can be made on the digit plane 122 of the stepped region 14, so that the thickness t2 of the landing pad 124 in the stepped region 14 can be thickened to be greater than the thickness t1 of the digit plane 122 in the array region 12.
[0061] The semiconductor device 100 is a three-dimensional OTS type memory cell. The OTS type memory cell is a current type element, which requires current to flow through the vertical columnar structure 200 and the conductive layer 120 to complete the operation. The size of the set / reset current flowing through the vertical columnar structure 200 and the conductive layer 120 is related to the contact area between the vertical columnar structure 200 and the conductive layer 120. If the contact area between the vertical columnar structure 200 and the conductive layer 120 is larger, the required set / reset current is also larger.
[0062] For example, the contact area of each independent memory cell can be represented by π×r×t1, where r is the diameter of each vertical columnar structure 200, and t1 is the thickness of each conductive layer 120 in the array region 12. For a three-dimensional OTS type memory cell, as the size becomes smaller, a smaller contact area is required to reduce the size of the required operating current. Therefore, a smaller thickness t1 is expected in a three-dimensional OTS type memory cell to reduce the required operating current as the size becomes smaller.
[0063] In the conventional gate replacement process for manufacturing the conductive layer, a stack of alternately arranged insulating layers and sacrificial layers is first manufactured, and then the sacrificial layers are replaced with conductive materials after the vertical columnar structure is manufactured. However, the thickness t1 of each conductive layer 120 in the array region 12 of the semiconductor device 100 of the present disclosure is getting thinner and thinner, for example, it may be as thin as 10 nanometers, 5 nanometers or even 3 nanometers, making it difficult to manufacture the conductive layer 120 using the conventional gate replacement process.
[0064] Therefore, the conductive layer 120 in the semiconductor device 100 of some embodiments of the present disclosure is formed by a local replacement process, and each conductive layer 120 includes a central block 130 and an edge block 140 , wherein the material of the edge block 140 is different from that of the central block 130 .
[0065] Reference Figures 5 to 11 , which are cross-sectional views of the manufacturing method of the semiconductor device at different manufacturing stages according to some embodiments of the present disclosure. Figure 5 As shown, Figure 5 The cross-sectional position is equivalent to that along Figure 1 First, a stack including an insulating layer 110 and a first conductive material layer 130' arranged alternately is formed. The stack includes an array region 12 and a stepped region 14. The length of the first conductive material layer 130' and the insulating layer 110 below it is gradually reduced from bottom to top to form the stepped region 14. The material of the insulating layer 110 can be an oxide, such as silicon oxide. The material of the first conductive material layer 130' is selected to have the same thickness as the vertical columnar structure 200 (see Figure 1 ) and is not easily affected during the manufacturing process of the vertical columnar structure 200. For example, the material of the first conductive material layer 130' can be TiN, carbon, graphene, doped carbon, W, WN, or TaN.
[0066] In some embodiments, the stack of the insulating layer 110 and the first conductive material layer 130' is formed on a substrate, such as a silicon substrate. In other embodiments, the stack of the insulating layer 110 and the first conductive material layer 130' is formed on a substrate having a semiconductor element, such as a substrate having a complementary metal oxide semiconductor (CMOS) or other suitable circuits.
[0067] Then, if Figure 6 As shown, the array area 12 is protected by the hard mask layer 112, and insulating spacers 115 are formed on the sides of the paired insulating layers 110 and the first conductive material layer 130', wherein each insulating spacer 115 contacts the corresponding insulating layer 110 and the material layer above it, such as the topmost insulating spacer 115 contacts the side walls of the topmost insulating layer 110 and the hard mask layer 112, and the remaining insulating spacers 115 contact the side walls of the insulating layer 110 and the first conductive material layer 130' above it.
[0068] It should be noted that part of the first conductive material layer 130' in the stepped region 14 is still not covered by the insulating spacer 115. The insulating spacer 115 is a dielectric material, such as SiN. In some embodiments, the insulating spacer 115 can be formed by first depositing a dielectric material layer and then performing back etching, such as reactive ion etching, to define it.
[0069] Then, if Figure 7As shown, a selective growth process is performed to grow a landing pad portion 123 on the first conductive material layer 130' in the stepped region 14, wherein due to the conditions of the selective growth process, the landing pad portion 123 grows only on the first conductive material layer 130' and does not grow on the insulating spacer 115. In other words, the insulating spacer 115 can be used to laterally isolate the first conductive material layer 130' and the landing pad portion 123 adjacent to each other on the plane. The first conductive material layer 130' in the stepped region 14 and the landing pad portion 123 thereon can be collectively referred to as a landing pad 124, and the thickness t2 of the landing pad 124 is greater than the thickness t1 of the first conductive material layer 130' in the array region 12.
[0070] In some embodiments, the material of the landing pad portion 123 may be the same as or different from the material of the first conductive material layer 130'. For example, the material of the first conductive material layer 130' may be carbon, and the material of the landing pad portion 123 may be carbon, TiN, TaN or tungsten. As long as the material of the landing pad portion 123 can be selectively grown on the material of the first conductive material layer 130'. The hard mask layer 112 may be removed after the landing pad portion 123 is fabricated.
[0071] Reference Figure 8 , which is along Figure 1 A cross-sectional view of the cross-sectional position of the line segment AA of FIG. A plurality of vertical columnar structures 200 are formed in the stacked array region 12. The method for making the vertical columnar structures 200 includes first forming a plurality of holes in the stacked array region 12, and then conformally depositing an OTS material on the sidewalls of the holes. The electrode material is then conformally deposited on the OTS material, and then a conductor material is deposited to fill the holes. In some embodiments, the holes are completely filled with the conductor material without any gaps therein.
[0072] The method for making the vertical columnar structure 200 also includes performing a polishing process to remove excess portions of the conductor material, the electrode material, and the OTS material. The polishing process may be a chemical mechanical polishing (CMP) process, and the polishing process stops at the topmost insulating layer 110. Thus, after the polishing process, the vertical columnar structure 200 is defined in the array region 12, wherein each vertical columnar structure 200 includes a conductive core 210 formed of a conductor material, a shell electrode 220 formed of an electrode material, and an OTS layer 230 formed of an OTS material. Next, a cap layer 150 is deposited on the vertical columnar structure 200 and the topmost insulating layer 110 to seal the memory array. A dielectric layer 170 is then deposited on the cap layer 150 and the stack including the array region 12 and the stepped region 14.
[0073] The material of the OTS layer 230 includes a chalcogenide that can be used as a bidirectional threshold switch, such as As2Se3, ZnTe or GeSe, etc. In some embodiments, the material of the OTS layer 230 can be a combination of a chalcogenide and other elements, such as a chalcogenide and Te, Se, Ge, Si, As, Ti, S, Sb and a combination thereof.
[0074] The material of the shell electrode 220 is different from the material of the conductive core 210. More specifically, the material of the shell electrode 220 is also conductive, and the resistance value of the material of the conductive core 210 is lower than the resistance value of the material of the shell electrode 220.
[0075] For example, the material of the conductive core 210 includes TiN, W, Al, Cu, TaN, Ru, Co or a combination thereof. The material of the shell electrode 220 is selected to have a good junction resistance performance between the OTS layer 230 and the conductive core 210. For example, the material of the shell electrode 220 can be TiN, carbon, graphene, doped carbon, W, WN, or TaN.
[0076] In each vertical columnar structure 200 , the shell electrode 220 directly and continuously contacts the sidewall of the conductive core 210 , and the OTS layer 230 directly and continuously contacts the sidewall of the shell electrode 220 .
[0077] Reference Fig. 9 , Fig. 9 For along Figure 1 A plurality of slits S1 and S2 are formed in the cross-sectional position of the line segment BB. Figure 8 In the structure shown, an operating area 10 of the semiconductor device is defined. Then, a removal process is performed to locally remove the portion of the first conductive material layer 130' exposed by the slits S1 and S2. More specifically, the removal process is a selective etching process, which has a high etching selectivity between the insulating layer 110 and the first conductive material layer 130'. After the etching process is performed, the side surface of the first conductive material layer 130' is recessed inward from the side surface of the insulating layer 110. In some embodiments, after the etching process is performed, the side surface of the first conductive material layer 130' can be a plane. In some other embodiments, after the etching process is performed, the side surface of the first conductive material layer 130' can be a concave surface or a convex surface. After the etching process is performed, a plurality of gaps 180 are formed at the edge of the first conductive material layer 130'.
[0078] In some embodiments, the lengths of the insulating layer 110 and the first conductive material layer 130' are gradually changed along the first direction D1. The slits S1 and S2 are formed on opposite sides of the operating area 10 and extend along the first direction D1. The slits S1 and S2 cut through the array area 12 and the stepped area 14.
[0079] Reference Fig.10 ,in Fig.10 For along Figure 1 The second conductive material 140' is deposited in the gap 180 (see Fig. 9 ), and the second conductive material 140' is deposited on the side surface of the insulating layer 110. Then, an anisotropic etching process, such as reactive ion etching (RIE), is performed to remove the protruding portion of the second conductive material 140', so that the side surface of the remaining portion of the second conductive material 140' is flush with the side surface of the insulating layer 110. The remaining portion of the second conductive material 140' remains at the edge of the first conductive material layer 130'.
[0080] The material of the second conductive material 140' is different from the material of the first conductive material layer 130'. For example, the resistance value of the second conductive material 140' is lower than the resistance value of the first conductive material layer 130'. For example, the material of the second conductive material 140' may include TiN, TaN, Co, CoSix, Ni, NiSix, Ru, W, WN or a combination thereof. Since the material of the second conductive material 140' in the conductive layer 120 is selected from a material with a lower resistance value, the overall resistance value of the conductive layer 120 can be reduced.
[0081] The first conductive material layer 130' is recessed and is located at the center of the conductive layer 120, so the first conductive material layer 130' can also be referred to as the central block 130 of the conductive layer 120. The remaining second conductive material 140' is located at the edge of the conductive layer 120, so the second conductive material 140' can also be referred to as the edge block 140 of the conductive layer 120. The edge block 140 is formed on the sidewall of the first conductive material layer 130'. The sidewall of the OTS layer 230 of each vertical columnar structure 200 directly and continuously contacts the side surface of the insulating layer 110 and the central block 130. The conductive layer 120 includes the central block 130 and the edge block 140 and serves as the gate structure of the vertical columnar structure 200, thereby forming a memory cell with a fully surrounded gate.
[0082] The partial replacement process used to form the conductive layer 120 has been described in detail in Fig. 9 and Fig.10The first conductive material layer 130' is deposited together with the insulating layer 110 to form a stack at the beginning, and the first conductive material layer 130' is not completely replaced by the second conductive material 140'. More specifically, only the edge portion of the first conductive material layer 130' is replaced by the second conductive material 140'. In this way, the difficulty of manufacturing the conductive layer 120 is reduced, and because the second conductive material 140' is selected from a material with a lower resistance value, the overall resistance value of the conductive layer 120 is also reduced.
[0083] Reference Fig.11 , which is along Figure 1 A cross-sectional view of the cross-sectional position of the line segment AA of FIG. A plurality of contacts 160 are formed and landed on the stepped region 14. The contacts 160 are respectively connected to the landing pads 124 (i.e., the landing pad portion 123) of the conductive layer 120 in the stepped region 14. In some embodiments, the landing pad 124 located in the stepped region 14 has a relatively thick thickness T2, so that while ensuring the electrical connection between the contact 160 and the landing pad 124, the problem of unexpectedly hitting the landing pad 124 during the process of manufacturing the contact 160 is prevented.
[0084] Reference Fig.12 , which is a three-dimensional view of a semiconductor device according to some embodiments of the present disclosure. The semiconductor device 100A includes a plurality of operating areas 10. Each conductive layer 120 in the operating area 10 has a central block 130 and an edge block 140 disposed at the edge of the central block 130, wherein the resistance value of the edge block 140 is lower than the resistance value of the central block 130. The central block 130 is a conductor and directly contacts the OTS layer 230 of the vertical columnar structure 200. In some embodiments, the stepped regions 14 of these operating areas 10 can be independent or integrated together.
[0085] Reference Fig.13 and Fig.14 , Fig.13 and Fig.14 Schematic diagrams of top views of a conductive layer in a semiconductor device according to different embodiments of the present disclosure. Fig.13 As shown, the operating area 10 is rectangular, and the edge blocks 140 are located at four edges of the central block 130 and surround the central block 130. In addition, in some embodiments, the edge blocks 140 may extend into the central block 130 of the conductive layer 120.
[0086] According to some embodiments of the present disclosure, manufacturing a semiconductor device includes first depositing a stack formed by a first conductive material layer and an insulating layer, and then the first conductive material layer is not completely replaced by a second conductive material. More specifically, only a portion at the edge of the first conductive material layer is replaced by the second conductive material. In this way, the difficulty of manufacturing a conductive layer as a gate structure of a semiconductor device is reduced, and because the second conductive material is selected from a material with a lower resistance value, the overall resistance value of the conductive layer is also reduced.
[0087] Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the appended claims.
Claims
1. A semiconductor device comprising: A stack comprising a plurality of insulating layers and conductive layers arranged alternately, each of the conductive layers comprising a central block and a plurality of edge blocks located at the edges of the central block, wherein the resistance of the material of the edge blocks is lower than the resistance of the material of the central block; and A plurality of vertical columnar structures are arranged in the stack, each of which comprises a conductive core, a shell electrode arranged on a side wall of the conductive core, and an ovonic threshold switch (OTS) layer arranged on a side wall of the shell electrode. 2 . The semiconductor device according to claim 1 , wherein the central blocks directly contact the OTS layers of the vertical column structures, and each of the central blocks continuously extends between the vertical column structures. 3 . The semiconductor device according to claim 1 , wherein a material of the central blocks comprises TiN, carbon, graphene, doped carbon, W, WN, or TaN. 4 . The semiconductor device according to claim 1 , wherein a material of the edge blocks comprises TiN, TaN, Co, CoSix, Ni, NiSix, Ru, W, WN or a combination thereof. 5 . The semiconductor device according to claim 1 , wherein a resistance value of a material of the conductive core is lower than a resistance value of a material of the shell electrode.
6. The semiconductor device according to claim 1, wherein the stack comprises an array region and a stepped region extending from the array region, wherein the lengths of the conductive layers and the insulating layers thereunder decrease gradually from bottom to top along a first direction, wherein the edge blocks of each of the conductive layers are arranged on opposite sides of the central block and extend along the first direction. The semiconductor device as claimed in claim 1 , wherein the edge blocks surround the central block. The semiconductor device according to claim 1 , wherein the edge blocks enter the central block.
9. A method for manufacturing a semiconductor device, comprising the following steps: forming a stack comprising a plurality of insulating layers and a plurality of first conductive material layers arranged alternately; forming a vertical columnar structure in an array region of the stack, the vertical columnar structure comprising a conductive core, a shell electrode disposed on a side wall of the conductive core, and an ovonic threshold switch (OTS) layer disposed on a side wall of the shell electrode; A plurality of edge blocks are formed adjacent to the sidewalls of the first conductive material layers. The material of the edge blocks is a second conductive material, wherein the resistance of the second conductive material is lower than the resistance of the first conductive material layers.
10. The method according to claim 9, further comprising: selectively growing a plurality of landing pad portions on the first conductive material layers in a stepped region of the stack; and A plurality of contact members are formed and respectively connected to the landing pad portions in the stepped region.