Method for improving read current stability in analog nonvolatile memory using final bake at a predetermined programming state

Abstract

A method for improving stability of a memory device having a controller configured to program each of a plurality of nonvolatile memory cells within a range of programming states defined by a minimum programming state and a maximum programming state. The method includes testing the memory cells to confirm that the memory cells are operable, programming each of the memory cells to an intermediate programming state, and baking the memory device at an elevated temperature while programming the memory cells to the intermediate programming states. Each memory cell has a first threshold voltage when programmed in the minimum programming state, a second threshold voltage when programmed in the maximum programming state, and a third threshold voltage when programmed in the intermediate programming state. The third threshold voltage is substantially midway between the first threshold voltage and the second threshold voltage and corresponds to an actual logarithmic midpoint of a read current.

Description

[0001] Related patent applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 895,458, filed on September 3, 2019, and U.S. Patent Application No. 16 / 803,401, filed on February 27, 2020. Technical Field

[0003] The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during a read operation. Background Art

[0004] Non-volatile memory devices are well known in the art. See, for example, U.S. Pat. No. 7,868,375, which discloses a quad-gate memory cell configuration. Specifically, the present application Figure 1 A split gate memory cell 10 is shown having spaced-apart source and drain regions 14 and 16 formed in a silicon semiconductor substrate 12. The source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other memory cells in the same row or column), and the drain region 16 is typically connected to a bit line through a bit line contact 28. A channel region 18 of the substrate is defined between the source / drain regions 14 and 16. A floating gate 20 is disposed over and insulated from (and controls the conductivity of) a first portion of the channel region 18 (and is partially located over and insulated from the source region 14). A control gate 22 is disposed over and insulated from the floating gate 20. A select gate 24 is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18. An erase gate 26 is disposed over and insulated from the source region 14 and is laterally adjacent to the floating gate 20. A plurality of such memory cells may be arranged in rows and columns to form a memory cell array.

[0005] Various combinations of voltages are applied to the control gate 22, the select gate 24, the erase gate 26, and / or the source region 14 / drain region 16 to program the memory cell (i.e., inject electrons into the floating gate), erase the memory cell (i.e., remove electrons from the floating gate), and read the memory cell (i.e., measure or detect the conductivity of the channel region 18 to determine the programmed state of the floating gate 20).

[0006] The memory cell 10 can be operated in a digital mode, where the memory cell is set to one of only two possible states: a programmed state and an erased state. The memory cell is erased by applying a high positive voltage on the erase gate 26 and optionally a negative voltage on the control gate 22 to cause tunneling of electrons from the floating gate 20 to the erase gate 26 (putting the floating gate in a more positively charged state - the erased state). The memory cell 10 can be programmed by applying a positive voltage on the control gate 22, the erase gate 26, the select gate 24 and the source region 14 and applying a current on the drain region 16. The electrons will then flow from the drain region 16 to the source region 14 along the channel region 18, where some of the electrons become accelerated and heated, whereby they are injected onto the floating gate 20 by hot electron injection (putting the floating gate in a more negatively charged state - the programmed state). The memory cell 10 can be read by applying a positive voltage on the select gate 24 (turning on the portion of the channel region below the select gate 24) and the drain region 16 (and optionally on the erase gate 26 and / or the control gate 22) and sensing the current flowing through the channel region 18. If the floating gate 20 is positively charged (erased), the memory cell will turn on and current will flow from the source region 14 to the drain region 16 (i.e., the memory cell 10 is sensed to be in its erased "1" state based on the sensed current). If the floating gate 20 is negatively charged (programmed), the channel region below the floating gate is turned off, thereby preventing any current from flowing (i.e., the memory cell 10 is sensed to be in its programmed "0" state based on the absence of current).

[0007] The following table provides non-limiting examples of erase, program, and read voltages:

[0008] Table 1

[0009] WL(SG) BL (Drain) Source EG CG Erase 0V 0V 0V 11.5V 0V programming 1V 1μA 4.5V 4.5V 10.5V Read Vcc 0.6V 0V 0V Vcc

[0010] The memory cell 10 may alternatively be operated in an analog manner, where the memory state of the memory cell (i.e., the amount of charge on the floating gate, such as the number of electrons) may be continuously changed from a fully erased state (least electrons on the floating gate) to a fully programmed state (most electrons on the floating gate), or just a portion of that range. This means that the cell storage is analog, which allows very precise and individual adjustments to each memory cell in the memory cell array. Alternatively, the memory may be operated as an MLC (multi-level cell), where the MLC is configured to be programmed to one of many discrete values, such as 16 or 64 different values. In the case of analog or MLC programming, the programming voltage is applied only for a limited time or as a series of pulses until the desired programming state is achieved. In the case of multiple programming pulses, intermediate read operations between programming pulses may be used to determine whether the desired programming state has been achieved (in which case programming stops) or has not yet been achieved (in which case programming continues).

[0011] A memory cell 10 operated in an analog manner or as an MLC can be more sensitive to noise and read current instability, which can adversely affect the accuracy of the memory device. One source of read current instability in analog non-volatile memory devices is the capture and emission of electrons by electron traps at the gate oxide-channel interface. The gate oxide is an insulating layer that isolates the floating gate 20 and the channel region 18 of the substrate 12. When electrons are trapped at the interface traps, it reduces the channel conductivity during a read operation, thereby increasing the threshold voltage Vt of the memory cell (i.e., the minimum voltage on the control gate required to turn on the channel region of the memory cell to produce a certain level of current, such as 1 μA). When the control gate voltage is equal to or above the threshold voltage, a conductive path is formed between the source region and the drain region. When the control gate voltage is below the threshold voltage, no conductive path is created, and any source / drain current is considered sub-threshold or leakage current. These single events of electron well recharging result in 1) random telegraph noise (RTN) and 2) unidirectional threshold voltage (Vt) shifts (also causing variations in the read operation channel current), which is known as relaxation or CCI - cell current instability.

[0012] This relaxation has been detected after a memory cell has been kept at room temperature for a long time or baked at high temperature in one state and then changed to a different state. Relaxation manifests itself as a small drift of the new state of the memory cell from the previous state. For example, if a memory cell is kept in its erased state for a period of time (characterized by a low threshold voltage Vt and a high channel current during a read operation) and is subsequently programmed to its programmed state (characterized by a high threshold voltage Vt and a low channel current during a read operation), then under the same read conditions, over time, the threshold voltage Vt is found to drop slightly and the read current during a read operation is found to increase slightly. The Vt and read current shifts are relatively small when compared to the typical cell current operating window between the 1 and 0 states of a digitally operated memory cell. However, for a memory cell operated as an MLC (multi-level cell) or in an analog manner, these shifts may not be negligible.

[0013] There is a need to reduce read current instability in non-volatile memory devices. Summary of the invention

[0014] The above problems and needs are solved by a method of improving the stability of a memory device, the memory device including a plurality of non-volatile memory cells and a controller configured to program each of the memory cells within a range of programming states defined by a minimum programming state and a maximum programming state. The method includes testing the memory cells to confirm that the memory cells are operable, programming each of the memory cells to an intermediate programming state, and baking the memory device at an elevated temperature while programming the memory cells to the intermediate programming states. For each of the memory cells, the memory cell has a first threshold voltage when programmed in the minimum programming state, a second threshold voltage when programmed in the maximum programming state, and a third threshold voltage when programmed in the intermediate programming state, wherein the third threshold voltage is substantially at a midpoint between the first threshold voltage and the second threshold voltage.

[0015] A method for improving stability of a memory device, the memory device comprising a plurality of nonvolatile memory cells and a controller, each of the nonvolatile memory cells comprising at least a floating gate disposed above and insulated from a channel region of a semiconductor substrate and a control gate disposed above and insulated from the floating gate, the controller being configured to program each of the memory cells within a programming state range defined by a minimum programming state and a maximum programming state, and to read each of the memory cells using a read voltage applied to the control gate. The method comprises testing the memory cells to confirm that the memory cells are operable, programming each of the memory cells to an intermediate programming state, and baking the memory device at a high temperature while programming the memory cells to the intermediate programming states. For each of the memory cells, when programmed in a minimum programming state, the memory cell generates a first read current during a read operation using a read voltage applied to a control gate, when programmed in a maximum programming state, the memory cell generates a second read current during a read operation using the read voltage applied to the control gate, and when programmed in an intermediate programming state, the memory cell generates a third read current during a read operation using the read voltage applied to the control gate, wherein the third read current is substantially at a logarithmic midpoint between the first read current and the second read current.

[0016] Other objects and features of the present invention will become apparent by examining the specification, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a side cross-sectional view of a conventional memory cell.

[0018] Figure 2 is a diagram illustrating components of a memory device.

[0019] Figure 3 is a graph showing the operating range of a memory cell with respect to read current and threshold voltage Vt within a sub-threshold operating range.

[0020] Figure 4 is a flow chart showing the steps for programming and baking a memory cell.

[0021] Figure 5 is a graph showing an example of IV characteristics of a memory cell within an operating range. DETAILED DESCRIPTION

[0022] The present invention is a method for stabilizing Figure 1A technique for stabilizing the read current of non-volatile memory cells of a type to improve the accuracy of the read operation and the memory retention life. The read stabilization technique involves programming the completed and operational memory cells to a predetermined programming state before performing a final high temperature bake process. Specifically, during the memory device testing process, the memory array in the device may undergo many thermal operations in various data patterns. However, once the memory device testing is completed, all memory cells are then programmed to a predetermined intermediate programming state and then the memory device is subjected to a final high temperature bake. It has been found that by performing this final high temperature bake when the memory cells are programmed to the intermediate programming state, the memory cell threshold voltage (Vt) shifts over time, thereby reducing the drift of the read operation current over time.

[0023] The desired intermediate programming state is a function of the controller configuration of the memory array, from Figure 2 This can be better understood by looking at the architecture of an exemplary memory device shown. The memory device includes an array 50 of non-volatile memory cells 10 that can be separated into two separate planes (Plane A 52a and Plane B 52b). The memory cells 10 can be Figure 1 Memory cells of the type shown in the figure may be formed on a single chip and may be arranged in multiple rows and columns in the semiconductor substrate 12. Adjacent to the array of non-volatile memory cells are address decoders (e.g., XDEC 54), source line drivers (e.g., SLDRV 56), column decoders (e.g., YMUX 58), high voltage row decoders (e.g., HVDEC 60), and bit line controllers (BLINHCTL 62) for decoding addresses and providing various voltages to various memory cell gates and regions during read, program, and erase operations of the selected memory cells. The column decoder 58 includes a sense amplifier that includes circuitry for measuring current on the bit line during a read operation. The controller 66 (including control circuitry) controls the various device elements to implement each operation (program, erase, read) on the target memory cell. The charge pump CHRGPMP 64 provides various voltages for reading, programming, and erasing memory cells under the control of the controller 66. The controller 66 is configured to operate the memory device to program, erase, and read the memory cells 10 .

[0024] It is the controller 66 that specifies the minimum and maximum programming states of the memory cells that are available during normal user operation. The minimum programming state is the programming state (i.e., the most erased state) to which each of the memory cells can be programmed under the control of the controller 66 during normal user operation, for which the lowest number of electrons are located on the floating gate 20 and the memory cell produces the highest (maximum) source / drain current during normal read operations. The maximum programming state is the programming state to which each of the memory cells can be programmed under the control of the controller 66 during normal user operation, for which the highest number of electrons are located on the floating gate 20 and the memory cell produces the lowest (minimum) source / drain current during normal read operations.

[0025] The intermediate programming state used during the final device high temperature bake operation is preferably a programming state in which a read current is generated during a read operation, which read current is the logarithmic actual midpoint between the minimum read current and the maximum read current of the maximum programming state and the minimum programming state, respectively, of the defined programming operating range specified by the controller 66. The intermediate programming state can be determined by the threshold voltage Vt or the read current as a parameter. The memory cell is a MOSFET transistor, and therefore Vt and read current are directly related via the basic transistor equation, therefore, the operating range of the memory cell can be determined based on the read current or Vt. An example of a memory cell current-voltage (IV) characteristic showing the relationship between Vt and read current is as follows Figure 3 , where the two curves represent the IV characteristics of the minimum programming state and the maximum programming state of the memory cell, respectively. In this non-limiting example, applying a voltage equal to or higher than the threshold voltage on the control gate will result in a read current (between the source and drain regions) of 1 μA or more during a read operation, which in this example is considered to be an indication of the amount of current that forms a conductive path between the source / drain regions. Figure 3 The rightward inflection point of the medium current-voltage (IV) curve at 1 μA indicates that this is the read current achieved when the voltage on the control gate reaches the threshold voltage Vt.

[0026] exist Figure 3In the example of , the right curve (curve A) is the IV curve of the exemplary memory cell in the maximum programming state of its simulated operating range, and the left curve (curve B) is the IV curve of the exemplary memory cell in the minimum programming state of its simulated operating range. The controller of the memory cell is configured to use a read voltage on the control gate of 1.2V, which means that the memory cell is read in a sub-threshold state (i.e., the programming state of the memory cell is detected using a sub-threshold current). Considering the two IV curves of the maximum programming state and the minimum programming state, the operating range of the read current of the memory cell operated by the controller is between 100nA and 100pA. The range of programming states corresponds to a Vt range of about 0.3V (between about 1.3V and about 1.6V). The read instability of the programmed memory cell can be represented by a Vt change or a read current change during the read operation. As described below, Vt or read current can be used as a parameter to quantify a solution to reduce read current fluctuations. Thus, an intermediate programming state is defined as a programming state corresponding substantially to half of the Vt of the minimum and maximum programming states achievable during normal operation, and corresponding to the logarithmic practical midpoint between the minimum and maximum read currents of the maximum and minimum programming states, respectively.

[0027] There are three main stages to achieve this read stabilization technique, such as Figure 4 As shown. First (step 1), the memory device including the memory cells 10 and their controllers 66 are tested to the point that they are operational and no further high temperature baking operation is required to complete the testing of the device. Second (step 2), all memory cells 10 are programmed to a substantially intermediate programming state. Finally (step 3), the memory device including all memory cells 10 programmed to an intermediate programming state undergoes a final high temperature baking process. Figure 5 Shows the above Figure 3 An example of a memory cell IV characteristic curve (curve C) for a memory cell programmed to a substantially intermediate programming state is described. Its threshold voltage Vt is about 1.48V, which is substantially mid-point between Vt_min and Vt_max for the minimum programming state and the maximum programming state, respectively (i.e., the mid-point threshold voltage is substantially mid-way between Vt_min and Vt_max). Similarly, when a read voltage of 1.2V is applied to the control gate during a read operation, the read current of the memory cell is about 3nA, which is the logarithmic practical mid-point between 100nA and 100pA for the minimum programming state and the maximum programming state, respectively (i.e., the mid-point read current is substantially between 100nA and 100pA on a logarithmic scale).

[0028] The high bake temperature is an elevated temperature that exceeds the maximum operating temperature to which the memory device is subjected during normal use. For example, if the maximum operating temperature specification of the product under user conditions is 150°C, the final high temperature bake process may include baking the memory device at 175°C for 24 hours. The minimum bake time depends on the bake temperature and may be shorter at higher temperatures. Preferably, for Figure 1 The memory cell shown can be baked for up to 24 hours at a bake temperature of 175°C. Generally speaking, the longer the bake time, the better the improvement in reducing read instability. As a practical example, if the selected package allows such high temperature processing, the assembled parts can be set to bake at 175°C for one day. Once the memory device, packaging and final testing and baking are completed, the memory device will operate under user conditions with higher read stability.

[0029] It should be understood that the present invention is not limited to the embodiments described above and shown herein, but encompasses any and all variations within the scope of any claims. For example, reference to the present invention herein is not intended to limit the scope of any claim or claim term, but only to refer to one or more features that may be covered by one or more of these claims. The examples of materials, processes and values ​​described above are merely exemplary and should not be considered to limit the claims. In addition, as is apparent from the claims and description, unless otherwise stated, not all method steps may need to be performed in the specific order shown or required.

Claims

1. A method for improving stability of a memory device, the memory device comprising a plurality of non-volatile memory cells and a controller, the controller being configured to program each of the memory cells within a programming state range defined by a minimum programming state and a maximum programming state, the method comprising: testing the memory cell to confirm that the memory cell is operable; programming each of the memory cells to an intermediate programming state; as well as baking the memory device at an elevated temperature when the memory cell is programmed to the intermediate programming state; Wherein, for each of the memory cells: When programmed in the minimum programming state, the memory cell has a first threshold voltage, The memory cell has a second threshold voltage when programmed in the maximum programming state, and When programmed in the intermediate programming state, the memory cell has a third threshold voltage, wherein the third threshold voltage is substantially at a midpoint between the first threshold voltage and the second threshold voltage; Each of the memory cells comprises: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the source and drain regions, a floating gate vertically disposed above a first portion of the channel region and insulated from the first portion, a select gate disposed vertically above and insulated from a second portion of the channel region, and A control gate is vertically disposed above the floating gate and insulated therefrom.

2. The method of claim 1 , wherein each of the memory cells further comprises: An erase gate is disposed above and insulated from the source region.

3. A method for improving stability of a memory device, the memory device comprising a plurality of non-volatile memory cells and a controller, each non-volatile memory cell comprising at least a floating gate disposed above and insulated from a channel region of a semiconductor substrate and a control gate disposed above and insulated from the floating gate, the controller being configured to program each of the memory cells within a programming state range defined by a minimum programming state and a maximum programming state, and to read each of the memory cells using a read voltage applied to the control gate, the method comprising: testing the memory cell to confirm that the memory cell is operable; programming each of the memory cells to an intermediate programming state; as well as baking the memory device at an elevated temperature when the memory cell is programmed to the intermediate programming state; Wherein, for each of the memory cells: The memory cell generates a first read current during a read operation using the read voltage applied to the control gate when programmed in the minimum programming state, When programmed in the maximum programming state, the memory cell generates a second read current during a read operation using the read voltage applied to the control gate, and The memory cell generates a third read current during a read operation using the read voltage applied to the control gate when programmed in the intermediate programming state, wherein the third read current is substantially at a logarithmic midpoint between the first read current and the second read current, Each of the memory cells comprises: spaced-apart source and drain regions formed in a semiconductor substrate, wherein the channel region of the substrate extends between the source and drain regions, a floating gate vertically disposed above a first portion of the channel region and insulated from the first portion, A select gate is disposed vertically over and insulated from a second portion of the channel region.

4. The method of claim 3, wherein each of the memory cells further comprises: An erase gate is disposed above and insulated from the source region.

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