Instruction execution control method, apparatus, processor, and electronic device

Abstract

Embodiments of the present application provide an instruction execution control method, device, processor and electronic device, wherein the instruction execution control method comprises: transmitting a memory access waiting instruction, including a target read-write instruction total amount, the target read-write instruction total amount being a target number that a current effective execution read-write memory access instruction should not exceed, the memory access waiting instruction being adapted to block transmission of subsequent instructions until the current effective execution read-write memory access instruction is not greater than the target read-write instruction total amount; obtaining the target read-write instruction total amount and an instruction type transmission order of each memory access instruction currently effectively executed; and according to the target read-write instruction total amount and the instruction type transmission order, obtaining a target read instruction total amount and a target write instruction total amount, the sum of the target read instruction total amount and the target write instruction total amount being equal to the target read-write instruction total amount. The instruction execution control method provided by the embodiments of the present application can implement execution of read-write memory access instructions compiled in sequence in a program in a manner of out-of-order execution.

Description

Technical Field

[0001] This application relates to the field of computer processors, specifically to an instruction execution control method, apparatus, processor, and electronic device. Background Technology

[0002] Normally, processors issue read and write memory access instructions sequentially. The order of completion is divided into sequential completion and out-of-order completion. Sequential completion means that read and write memory accesses are completed in the order they are issued. Out-of-order completion means that read and write memory accesses are not completed in the order they are issued, but read and write memory accesses are still completed in the order they are issued within each individual memory access.

[0003] To prevent errors when memory access instructions and arithmetic instructions use the same registers, existing technology typically uses memory wait instructions to control instruction execution. Instructions following the memory wait instruction are only issued if the number of currently valid memory access instructions is less than or equal to the target number specified by the memory wait instruction.

[0004] Sequentially executed memory access wait instructions do not distinguish whether the target quantity is the number of read instructions or the number of write instructions. Therefore, executable programs using sequentially executed memory access wait instructions cannot run on processors that provide out-of-order execution. Without source code to recompile, the processor must be manually configured to execute sequentially, which is very inconvenient for users. As out-of-order execution processors become increasingly popular, and historical programs are mostly sequentially executed, this incompatibility problem is becoming increasingly prominent.

[0005] Therefore, how to execute read, write, and memory access instructions compiled sequentially in a program through out-of-order execution has become a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, embodiments of this application provide an instruction execution control method, apparatus, processor, and electronic device to achieve out-of-order execution of read, write, and memory access instructions compiled in sequence in a program.

[0007] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0008] In a first aspect, embodiments of this application provide an instruction execution control method, including:

[0009] The instruction to issue a memory access wait instruction includes a target total number of read and write instructions, wherein the target total number of read and write instructions is a target number that the currently valid read and write memory access instructions must not exceed, and the instruction to issue a memory access wait instruction is adapted to block the issuance of subsequent instructions until the currently valid read and write memory access instructions are not greater than the target total number of read and write instructions.

[0010] Obtain the total number of target read / write instructions and the instruction type issuance order of each currently valid memory access instruction;

[0011] Based on the total number of target read and write instructions and the order of instruction type issuance, the total number of target read instructions and the total number of target write instructions are obtained, and the sum of the total number of target read instructions and the total number of target write instructions is equal to the total number of target read and write instructions.

[0012] Secondly, embodiments of this application provide an instruction execution control device, comprising:

[0013] The instruction issuing module is adapted to issue a memory access wait instruction, including a target total number of read and write instructions. The target total number of read and write instructions is a target number that the currently valid read and write memory access instructions must not exceed. The memory access wait instruction is adapted to block the issuance of subsequent instructions until the currently valid read and write memory access instructions are not greater than the target total number of read and write instructions.

[0014] The target total number of read / write instructions and memory access instruction type acquisition module is adapted to acquire the target total number of read / write instructions and the instruction type issuance order of each currently valid memory access instruction;

[0015] The target instruction total quantity acquisition module is adapted to acquire the target read instruction total quantity and the target write instruction total quantity based on the target read and write instruction total quantity and the instruction type issuance order, wherein the sum of the target read instruction total quantity and the target write instruction total quantity is equal to the target read and write instruction total quantity.

[0016] Thirdly, embodiments of this application provide a processor, including:

[0017] The memory access type register records the type of memory access instruction in each bit.

[0018] The validity identifier register contains bits that record the validity of each corresponding memory access instruction.

[0019] Fourthly, embodiments of this application provide an electronic device including the integrated circuit described in the second aspect above.

[0020] The instruction execution control method provided in this application, after issuing a memory access wait instruction, obtains the instruction type and issuance order of the memory access instructions that are being executed in sequence in the program, as well as the total number of target read / write instructions included in the memory access wait instruction. Based on this, the total number of target read / write instructions is converted into a total number of target read instructions and a total number of target write instructions. The next instruction of the memory access wait instruction is executed only when both the total number of target read instructions and the total number of target write instructions are satisfied. Therefore, the instruction execution control method provided in this application only converts the total number of target read / write instructions in the memory access wait instruction of the compiled executable program into a total number of target read instructions and a total number of target write instructions. It does not require changing the program itself, and therefore does not require obtaining the source program and recompiling it. It can achieve out-of-order execution of the sequentially compiled read / write memory access instructions in the program. Therefore, by using the instruction execution control method provided in the embodiments of this application, it is very convenient to execute programs that execute sequentially compiled read, write, and memory access instructions in an out-of-order manner, thereby achieving good compatibility with historical instructions and programs. At the same time, since out-of-order execution is more efficient than sequential execution, changing the execution mode of sequentially compiled read, write, and memory access instructions in the program to out-of-order execution can also improve the overall execution speed of the program. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 A flowchart illustrating the process of waiting for a memory access instruction to be executed is shown.

[0023] Figure 2 This illustrates another flowchart of the process waiting for the execution of a memory access instruction;

[0024] Figure 3 A flowchart of an instruction execution control method provided in an embodiment of this application is shown;

[0025] Figure 4 This paper illustrates a flowchart of obtaining the instruction type issuance order in the instruction execution control method provided in an embodiment of this application;

[0026] Figure 5 A framework diagram of the processor provided in an embodiment of this application is shown;

[0027] Figure 6 Another flowchart illustrating the instruction type issuance sequence acquisition of the instruction execution control method provided in this application embodiment is shown;

[0028] Figure 7 This diagram illustrates the instruction type issuance sequence of the instruction execution control method provided in this application embodiment;

[0029] Figure 8 This paper illustrates a flowchart of obtaining the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in an embodiment of this application.

[0030] Figure 9 This illustration shows a schematic diagram of obtaining the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in this application embodiment;

[0031] Figure 10 This illustration shows another schematic diagram of obtaining the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in this application embodiment;

[0032] Figure 11 Another flowchart illustrating the acquisition of the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in this application embodiment is shown;

[0033] Figure 12 This paper illustrates a flowchart of the instruction execution control method provided in this application for obtaining the total number of instructions to be completed.

[0034] Figure 13a A frame diagram of the instruction execution control device provided in an embodiment of this application is shown;

[0035] Figure 13b This diagram illustrates a framework of the module for obtaining the target total number of read / write instructions and the type of memory access instructions in the instruction execution control device provided in an embodiment of this application. Detailed Implementation

[0036] As discussed above, the incompatibility problem is becoming increasingly prominent due to the growing popularity of out-of-order processors, while read, write, and memory access instructions in historical programs are mostly compiled for sequential execution.

[0037] The following section introduces the instruction execution control methods. Please refer to [link / reference]. Figure 1 , Figure 1 The flowchart illustrates the process of waiting for a memory access instruction to be executed.

[0038] like Figure 1As shown, after fetching the memory access wait instruction, executing the WAITCNT(M) instruction retrieves the target total number of read / write instructions M specified by the memory access wait instruction. Simultaneously, it retrieves the number of currently executing read / write instructions CNT in real time. The number of currently executing read / write instructions CNT is compared with the target total number of read / write instructions M to determine if CNT is not greater than M. If yes, the next instruction is fetched; otherwise, the process blocks fetching the next instruction, and the comparison between CNT and M is performed at the next moment. This process is repeated until CNT is not greater than M. Of course, the number of currently executing read / write instructions CNT refers to the number of memory access instructions that have been issued and are currently being executed at any given moment after the memory access wait instruction is issued.

[0039] In this way, when multiple memory access instructions are followed by an operation instruction, and the memory access instructions and operation instructions use the same register, or when there is data dependency or data hazard, the execution of the operation instruction can be blocked until the corresponding memory access instruction is completed, thus avoiding read-after-write or write-after-read operation errors due to the same register.

[0040] It is easy to understand, such as Figure 1 The execution mode of the memory access wait instruction shown is only suitable for sequential execution. This is because in out-of-order execution, the execution order of read instructions and write memory access instructions is not related to the issue order. Therefore, when the memory access wait instruction needs to wait for the first X issued read instructions to complete, and the number of read and write instructions is not greater than the specified target total number of read and write instructions M1, the later issued write memory access instructions may complete before the read instructions. As a result, before the X read instructions have completed, the number of read and write instructions CNT has already met the condition of not being greater than the specified target total number of read and write instructions M1, thus incorrectly performing the fetch and issue operation for the next operation instruction, causing an operation error.

[0041] The condition that the total number of read and write instructions M1 must meet is: X read instructions are completed and Y write instructions are completed. However, since the write memory access instructions issued later may complete before the read instructions, when the number of read and write instructions CNT has met the condition of not being greater than the total number of read and write instructions M1, Xn read instructions are completed and Y+n write instructions are completed. In this case, the fetch operation for the next operation instruction is performed, resulting in an operation error.

[0042] Therefore, existing technology provides another instruction execution control method for blocking instruction execution during out-of-order execution. This method provides two instructions for controlling instruction execution: a read memory access wait instruction and a write memory access wait instruction. Each instruction specifies a target total number of wait instructions; the read memory access wait instruction specifies the target total number of read instructions, and the write memory access wait instruction specifies the target total number of write instructions. Valid, currently executing memory access instructions are also fetched in real-time according to read and write memory access instructions. The next instruction is fetched only if the number of read instructions (RCNT) is not greater than the target total number of read instructions specified by the read memory access wait instruction, and the number of write instructions (WCNT) is not greater than the target total number of write instructions specified by the write memory access wait instruction.

[0043] As can be seen, this method provides two new instructions different from memory access wait instructions. To ensure compatibility with programs containing memory access wait instructions, the instruction execution device needs to support both methods simultaneously. For details, please refer to [reference needed]. Figure 2 , Figure 2 This diagram illustrates another process flow for waiting for a memory access instruction to be executed.

[0044] like Figure 2 As shown, after a memory access instruction is successfully issued, it first affects the number of currently valid read and write instructions (CNT), incrementing it by 1. Then, it determines the type of the memory access instruction and applies the corresponding memory access instruction count. If it is a read memory access, then RCNT+1; if it is a write memory access, then WCNT+1. When the memory access instruction is completed, CNT is first decremented by 1. Then, depending on whether it was a write or read memory access, if it was a read memory access, then RCNT-1; if it was a write memory access, then WCNT-1.

[0045] It can be seen that, as Figure 2 As shown, the instruction execution control flow can simultaneously count the number of memory access instructions (CNT), the number of read instructions (RCNT), and the number of write instructions (WCNT) for memory access wait instructions.

[0046] When a memory access wait instruction is issued, such as the WAITCNT instruction, or the WAITCNT and WAITWCNT instructions, the number of read / write instructions in the corresponding WAITCNT instruction, the number of read instructions in the WAITCNT instruction, and the number of write instructions in the WAITWCNT instruction can also be obtained. This allows for the comparison of the number of read / write instructions in the CNT and WAITCNT instructions, enabling the execution of a program including memory access wait instructions in sequential execution mode. Alternatively, it allows for the comparison of the number of read instructions in the RCNT and WAITCNT instructions, and the comparison of the number of write instructions in the WCNT and WAITWCNT instructions, enabling the execution of a program including read and write memory access wait instructions in out-of-order execution mode.

[0047] However, programs compiled to execute read and write memory access instructions sequentially only contain read and write memory access wait instructions, lacking read and write memory access wait instructions. Therefore, they can only utilize the CNT counter and WAITCNT instructions in the aforementioned structure and flow to execute the sequentially compiled read and write memory access instructions sequentially. Out-of-order execution of sequentially compiled read and write memory access instructions is not possible. Consequently, devices employing the above instruction execution can only select the corresponding execution mode based on the compilation status of read and write memory access instructions in different programs. This requires additional configuration from the program user, consuming their effort. Furthermore, even if the structure and flow of the execution instructions could achieve a faster out-of-order execution method, programs that execute sequentially compiled read and write memory access instructions can still only use the slower sequential execution method, failing to achieve out-of-order execution and affecting program execution efficiency.

[0048] It is evident that the above instruction execution control method does not achieve out-of-order execution of programs that execute compiled read, write, memory access, and wait instructions in sequence. In other words, existing technology cannot execute programs that execute compiled read, write, memory access, and wait instructions in sequence out of order.

[0049] To address the aforementioned problems, embodiments of this application provide an instruction execution control method, suitable for a processor, comprising:

[0050] The instruction to issue a memory access wait instruction includes a target total number of read and write instructions, wherein the target total number of read and write instructions is a target number that the currently valid read and write memory access instructions must not exceed, and the instruction to issue a memory access wait instruction is adapted to block the issuance of subsequent instructions until the currently valid read and write memory access instructions are not greater than the target total number of read and write instructions.

[0051] Obtain the total number of target read / write instructions and the instruction type issuance order of each currently valid memory access instruction;

[0052] Based on the total number of target read and write instructions and the order of instruction type issuance, the total number of target read instructions and the total number of target write instructions are obtained, and the sum of the total number of target read instructions and the total number of target write instructions is equal to the total number of target read and write instructions.

[0053] Thus, the instruction execution control method provided in this application, after the memory access wait instruction in the launch program, obtains the instruction type and launch order of the memory access instructions that are being executed in sequence and are being compiled in order, as well as the total number of target read and write instructions included in the memory access wait instruction, and accordingly converts the total number of target read and write instructions into the total number of target read instructions and the total number of target write instructions. The next instruction of the memory access wait instruction is executed only when both the total number of target read instructions and the total number of target write instructions are satisfied.

[0054] As can be seen, the instruction execution control method provided in this application only transforms the total number of target read and write instructions in the compiled executable program that are waiting for memory access instructions into the total number of target read instructions and the total number of target write instructions. It does not require changing the program itself, so it does not require obtaining the source program and recompiling it. It can achieve out-of-order execution of the read and write memory access instructions that are executed sequentially in the program. Therefore, using the instruction execution control method provided in this application, it is very convenient to execute the program that executes the compiled read and write memory access instructions in sequence by means of out-of-order execution, so as to have good compatibility with historical instructions and programs. At the same time, since out-of-order execution is more efficient than sequential execution, changing the execution mode of the read and write memory access instructions that are executed sequentially in the program to out-of-order execution can also improve the overall execution speed of the program.

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] Please refer to Figure 3 , Figure 3 A flowchart of an instruction execution control method provided in an embodiment of this application is shown.

[0057] like Figure 3 As shown, the instruction execution control method provided in this application includes the following steps:

[0058] In step S1100, a memory access wait instruction is issued.

[0059] It is easy to understand that a memory access wait instruction is one of many instructions, suitable for preventing the issuance of subsequent memory access instructions, that is, preventing the issuance of the instruction following the memory access wait instruction. The next instruction refers to the instruction following the memory access wait instruction in the program where the memory access wait instruction is located.

[0060] Specifically, the memory access wait instruction includes a target total number of read and write instructions. This target total number of read and write instructions is the target number that the currently valid read and write memory access instructions being executed must not exceed. Only when the number of currently valid read and write memory access instructions being executed is less than or equal to this target number will the memory access wait instruction no longer prevent the issuance of the next instruction of the memory access wait instruction.

[0061] The total number of target read / write instructions is included in the memory access wait instructions issued, and its value is stored in the program along with the memory access wait instructions and will not change as the program is executed.

[0062] Of course, the read / write memory access instructions being executed include both read and write instructions.

[0063] In summary, the specific form of the memory access wait instruction is memory access WAITCNT(M), where M is the total number of target read / write instructions. The number of currently valid read / write memory access instructions being executed can be denoted as CNT. Only when CNT <= M will the next instruction of the memory access wait instruction no longer be blocked.

[0064] In step S1200, the total number of target read / write instructions and the instruction type issuance order of each of the currently valid memory access instructions are obtained.

[0065] After issuing the memory access wait instruction, the total number of target read and write instructions is obtained. Since the total number of target read and write instructions is directly contained in the memory access wait instruction, the total number of target read and write instructions can be easily obtained based on the memory access wait instruction.

[0066] The currently active memory access instructions refer to any memory access instructions that have been issued and are being executed at any given time after the memory access wait instruction has been issued. The number of these instructions will gradually decrease as time goes on and each instruction is completed.

[0067] Therefore, it is easy to understand that the instruction type issuance order of each of the currently valid memory access instructions refers to the memory access type and issuance order of each instruction that was issued before the memory access waiting instruction and is still being executed.

[0068] For example: first, read command 1 is issued, then read command 2, then write command 1, read command 3, and so on.

[0069] In step S1300, the total number of target read instructions and the total number of target write instructions are obtained according to the total number of target read and write instructions and the order of instruction type issuance.

[0070] Based on the total number of target read and write instructions and the order in which the instructions are issued, we can determine the instructions and instruction types of the last total number of target read and write instructions issued. By further statistical analysis, we can determine the number of read instructions and the number of write instructions in the last total number of target read and write instructions issued, thus obtaining the target number of read instructions and the target number of write instructions.

[0071] Therefore, the target total number of read instructions is the target number that the currently valid read instructions being executed must not exceed, and the target total number of write instructions is the target number that the currently valid write instructions being executed must not exceed. Only when both target numbers are not greater than the target number will the memory access wait instruction no longer prevent the sending of the next instruction of the memory access wait instruction.

[0072] It is easy to understand that the sum of the total number of target read instructions and the total number of target write instructions equals the total number of target read and write instructions.

[0073] After obtaining the target total number of read instructions and the target total number of write instructions, the relevant instructions can be generated separately to achieve instruction control.

[0074] As can be seen, the instruction execution control method provided in this application only transforms the total number of target read and write instructions in the compiled executable program that are waiting for memory access instructions into the total number of target read instructions and the total number of target write instructions. It does not require changing the program itself, so it does not require obtaining the source program and recompiling it. It can achieve out-of-order execution of the read and write memory access instructions that are executed sequentially in the program. Therefore, using the instruction execution control method provided in this application, it is very convenient to execute the program that executes the compiled read and write memory access instructions in sequence by means of out-of-order execution, so as to have good compatibility with historical instructions and programs. At the same time, since out-of-order execution is more efficient than sequential execution, changing the execution mode of the read and write memory access instructions that are executed sequentially in the program to out-of-order execution can also improve the overall execution speed of the program.

[0075] In another specific implementation, in order to achieve final instruction execution control, it may further include:

[0076] In step S1400, it is determined whether the total number of current read instructions is less than or equal to the target total number of read instructions. If so, step S1500 is executed; otherwise, step S1700 is executed to continue obtaining the total number of current read instructions.

[0077] During the instruction execution control process, the current total number of read instructions will be continuously acquired and compared with the target total number of read instructions. If they match, it means that the execution status of the current read instructions has met the requirements and further judgment of the current total number of write instructions is needed; otherwise, it means that the execution status of the current read instructions still does not meet the requirements and it is necessary to wait for the current read instruction to continue execution, and at the same time execute step S1700.

[0078] In step S1500, it is determined whether the total number of current write instructions is less than or equal to the target total number of write instructions. If so, step S1600 is executed; otherwise, step S1800 is executed to continue obtaining the total number of current write instructions.

[0079] It is easy to understand that during the instruction execution control process, the current total number of write instructions will be continuously obtained and compared with the target total number of write instructions to determine whether it is not greater than the target total number of write instructions. If it is, it means that the execution status of the current write instructions has met the requirements and step S1600 can continue to be executed; otherwise, it means that the execution status of the current write instructions still does not meet the requirements and it is necessary to wait for the current write instruction to continue to be executed.

[0080] It should be noted that in other embodiments, the execution steps of steps S1400 and S1500 can be replaced. Only when both of the above conditions are met will the requirement to send the next instruction be satisfied.

[0081] It is easy to understand that the "re-acquisition and judgment" refers to rereading the current total number of read instructions and the current total number of write instructions, comparing the newly acquired current total number of read instructions with the target total number of read instructions, and comparing the newly acquired current total number of write instructions with the target total number of write instructions. Specifically, the comparison can be performed after a fixed number of clock cycles if the conditions are not met simultaneously, or the comparison can be performed after a change in the current total number of memory access instructions is detected.

[0082] In step S1600, the next instruction following the memory access wait instruction is transmitted.

[0083] The next instruction is the instruction following the memory access wait instruction in the currently executing program where the memory access instruction is located.

[0084] In step S1700, the current total number of read instructions is obtained, and the process proceeds to step S1400.

[0085] In step S1800, the current total number of write instructions is obtained, and the process proceeds to step S1500.

[0086] It is easy to understand that the "continue to acquire" means to read the total number of current read instructions and the total number of current write instructions again, and then compare the newly acquired total number of current read instructions with the target total number of read instructions, and compare the newly acquired total number of current write instructions with the target total number of write instructions.

[0087] Specifically, the comparison can be performed at fixed clock intervals after the conditions are not met simultaneously, or it can be performed after detecting a change in the total number of memory access instructions.

[0088] In one specific implementation, both the current total number of read instructions and the current total number of write instructions can be recorded by a counter. When the value in the counter changes, the new current total number of read instructions and the current total number of write instructions can be obtained and compared for judgment.

[0089] As can be seen, by comparing the total number of target read instructions and the total number of target write instructions with the total number of current read instructions and the total number of current write instructions, it is possible to determine whether to issue the next instruction of the memory access wait instruction. There is no need to generate new wait instructions corresponding to read and write respectively. By utilizing the existing physical structure of this execution process, the subsequent instruction execution can be easily implemented.

[0090] To facilitate obtaining the instruction type and issuance order after issuing a memory access wait instruction, in one specific implementation, please refer to... Figure 4 , Figure 4 A flowchart illustrating the instruction type issuance sequence acquisition of the instruction execution control method provided in this application embodiment is shown.

[0091] like Figure 4 As shown, the instruction type issuance order of the instruction execution control method provided in this application embodiment can be obtained through the following steps, including:

[0092] In step S1210, the type information and valid memory access information of each memory access instruction arranged in the order of instruction issuance are obtained.

[0093] The type information refers to information that identifies whether the instruction is a read instruction or a write instruction, and the valid memory access information refers to information that identifies whether the instruction is valid and the number of valid memory access instructions.

[0094] It's easy to understand that since the voltage levels in a memory cell are either high or low, type information alone cannot distinguish whether a high or low voltage level in a memory cell storing valid memory access type information is a valid bit representing the instruction type or an invalid bit that doesn't represent any meaning. Therefore, it's necessary to combine the corresponding bits in the valid memory access information with the type information bits, and determine whether the bits in the type information represent the instruction type based on whether the corresponding bit represents a valid bit.

[0095] In step S1220, the instruction type issue order is obtained by combining the type information and the valid memory access information.

[0096] After obtaining the type information and valid memory access information, the type issue order of the valid instructions being executed can be obtained by combining the type information and valid memory access information. The type issue order is the information obtained by arranging the types of instructions according to the order in which the instructions are issued.

[0097] To make it easier to understand, the following example is provided:

[0098] For example: Suppose a high level is represented by 1 and a low level by 0. Also, 1 indicates a read instruction and represents a valid bit, while 0 indicates a write instruction and represents an invalid bit. The currently executing memory access instructions are issued in the following order: read instruction 0, read instruction 1, read instruction 2, write instruction 0, write instruction 1, read instruction 3, write instruction 2, write instruction 3. Therefore, there are 8 instructions being executed. Thus, eight bits in the valid memory access information are 1. The bit order in the type information, from beginning to end, is 1, 1, 1, 0, 0, 1, 0, 0. The resulting instruction type issuance order is: read-read-read-write-write-read-write-write.

[0099] Therefore, the instruction type issue order can be easily obtained through type information and valid memory access information.

[0100] In one specific implementation, a register can be used to conveniently record the instruction issuance order. By retrieving the information recorded in the register, the type issuance order can be obtained. For ease of understanding, the basic structure of a processor suitable for implementing the instruction execution control method provided in any embodiment of this application will first be described. Please refer to... Figure 5 , Figure 5 A structural block diagram of a processor provided in an embodiment of this application is shown.

[0101] like Figure 5 As shown, the processor 400 includes:

[0102] The memory access type register 420 is suitable for recording the type of memory access instruction through each bit.

[0103] The validity identifier register 410 is adapted to record the validity of each corresponding memory access instruction by means of each bit.

[0104] Specifically, each bit of the memory access type register 420 uses one of 0 and 1 to represent a read instruction and the other to represent a write instruction.

[0105] For example, 0 represents a write instruction and 1 represents a read instruction.

[0106] Each bit of the valid identifier register 410 is 0 or 1 to indicate whether the corresponding bit of the memory access type register 420 is valid.

[0107] For example, if 1 represents a valid bit value, then the bit value corresponding to 0 is invalid.

[0108] Of course, the valid identifier register 410 records the validity of each corresponding memory access instruction through each bit. Therefore, the number of data bits in the valid identifier register 410 must not be less than the number of data bits in the memory access type register 420.

[0109] In this way, by reading the number of bits stored in the valid flag register that indicate that the corresponding bit is valid (with a value of 1), the number of currently valid memory access instructions can be obtained; according to the memory access type register corresponding to the valid flag register, the type information and valid memory access information of the valid memory access instructions being executed can be obtained, and then the type issue order can be obtained.

[0110] Please combine Figure 5 refer to Figure 6 and Figure 7 , Figure 6This paper illustrates another flowchart of obtaining the instruction type issue order of the instruction execution control method provided in an embodiment of this application. Figure 7 This diagram illustrates the instruction type issuance sequence of the instruction execution control method provided in this application embodiment.

[0111] As shown in the figure, the instruction type issuance order acquisition step of the instruction execution control method provided in this application embodiment includes:

[0112] In step S1211, the type information of each memory access instruction arranged in the instruction issuance order is obtained through the memory access type register.

[0113] Based on the values ​​of each bit in the memory access type register and the corresponding instruction type, the type information of each instruction can be obtained. At the same time, in order to determine the instruction issue order, the values ​​of each bit can be arranged in accordance with the issue order.

[0114] Right now Figure 7 As shown, in the memory access type register 420, 1 represents a read instruction and 0 represents a write instruction. The bits of the memory access type register 420, arranged from right to left, represent the type information of each instruction issued from earliest to latest.

[0115] Specifically, in one embodiment, the read instruction pointer 422 and the write instruction pointer 421 can be used to point to the bits of the earliest issued read instruction and the earliest issued write instruction stored in the memory access type register 420, respectively, to record the earliest issued but incomplete read and write instructions.

[0116] In step S1212, the valid memory access information is obtained through the memory access type register and the valid identifier register corresponding to each bit of the memory access type register.

[0117] Since the memory access type register 420 needs to identify both read and write instructions, and identification is impossible when no instruction is sent, a validity flag register is set up to determine the valid bits in the memory access type register 420.

[0118] Continue to refer to Figure 7 Assuming that a 1 in the valid identifier register 410 indicates that a record is valid, then Figure 7 The valid identifier register shows that 8 data bits from data bit 0 to data bit 7 are 1, indicating that 8 instructions are being executed. The memory access type register 420 has invalid bits from data bit 8 onwards. Although the bit values ​​are 0, it does not indicate a write instruction.

[0119] Specifically, the valid pointer 411 can be used to point to the location in the valid identifier register 410 that records the latest issued but incomplete memory access instruction.

[0120] Therefore, by combining the valid identifier register 410 and the memory access type register 420, we can know that the instruction type sequence is 11100100, which is read-read-read-write-write-read-write-write.

[0121] Of course, using registers and pointers is just one specific implementation method. In other implementations, linked lists can also be used.

[0122] In this way, by setting the memory access type register 420 and the valid identifier register 410, the type information and valid memory access information of the currently executing instruction can be quickly and easily accessed, and the above information can be updated in a timely manner, thereby realizing the acquisition of the instruction type issue order.

[0123] After obtaining the instruction type issuance order, it is also necessary to obtain the total number of target read instructions and the total number of target write instructions. In one specific implementation, to facilitate obtaining the total number of target read instructions and the total number of target write instructions based on the total number of target read and write instructions and the instruction type issuance order, please refer to [reference needed]. Figure 8 , Figure 8 A flowchart illustrating the acquisition of the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in this application embodiment is shown.

[0124] like Figure 8 As shown, the steps for obtaining the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in this application embodiment may include:

[0125] In step S1310, the total number of currently valid read and write memory access instructions is obtained, and the instruction quantity difference is obtained based on the total number of currently valid read and write instructions and the target total number of read and write instructions.

[0126] Of course, the total number of current read and write instructions refers to the total number of all memory access instructions currently being executed, including the total number of current read instructions and the total number of current write instructions. The target total number of read and write instructions is specified by the execution wait instruction.

[0127] The instruction quantity difference can be obtained by subtracting the target total number of read and write instructions from the current total number of read and write instructions.

[0128] Based on the previous example, the current total number of read / write instructions is 8. Assuming the target total number of read / write instructions is 3, then the instruction quantity difference is 5.

[0129] In step S1320, at least one of the read instruction issuance order and the write instruction issuance order is obtained according to the instruction type issuance order to obtain the instruction issuance order.

[0130] It should be noted that, as described in this article, obtaining at least one of the read instruction issuance order and the write instruction issuance order based on the instruction type issuance order means that it is possible to obtain only the read instruction issuance order, or only the write instruction issuance order, or to obtain both the read instruction issuance order and the write instruction issuance order simultaneously.

[0131] Therefore, the instruction issuance order described in this article may include only the read instruction issuance order or the write instruction issuance order, or it may include both the read instruction issuance order and the write instruction issuance order. Of course, when only the read instruction issuance order is obtained, the obtained instruction issuance order is the read instruction issuance order; when only the write instruction issuance order is obtained, the obtained instruction issuance order is the write instruction issuance order; when both the read instruction issuance order and the write instruction issuance order are obtained, the obtained instruction issuance order includes both the read instruction issuance order and the write instruction issuance order.

[0132] For ease of description, the case described in this article will be illustrated using both methods:

[0133] In some implementations, combined Figure 7 refer to Figure 9 , Figure 9 This illustration shows a schematic diagram of obtaining the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in this application embodiment.

[0134] The valid identifier register and the memory access type register can be subjected to corresponding logical operations to obtain the logical read instruction register 4201 and the logical write instruction register 4202. The logical read instruction register is represented by 1 to indicate that it is valid and is a read instruction, and the logical write instruction register is represented by 1 to indicate that it is valid and is a write instruction.

[0135] As shown in the figure, the read instruction issuance sequence should be: 00100111, that is, the bit corresponding to the non-issued read instruction (including whether the write instruction was issued or not) is 0; the write instruction issuance sequence should be: 11011000, that is, the bit corresponding to the non-issued write instruction (including whether the read instruction was issued or not) is 0.

[0136] In step S1330, the instruction issuance sequence is shifted by a target number of bits from the side of the earliest issued memory access instruction through logical operations and logical shifts.

[0137] To facilitate subsequent logical operations and shifts, the logic register may include an original data bit length portion and an extended data bit length portion. The original data bit length portion is equal to the data bit length of the memory access type register. The extended data length portion is located on the side of the earliest issued memory access instruction of the original data bit length portion, and its length is not less than that of the original data bit length portion. It is easy to understand that the data bits in the extended data length portion obtained after logical operations are all 0.

[0138] Then, the values ​​of the bits in the logical read instruction register 4201 and the logical write instruction register 4202 are shifted to the side of the earliest issued memory access instruction, shifting the instruction amount difference by data bits.

[0139] Based on the aforementioned case, the values ​​of the bits in the logical read instruction register 4201 and the logical write instruction register 4202 are set to... Figure 9 Shifting 5 bits to the right as shown, we get Figure 10 , Figure 10 This illustration shows another schematic diagram of obtaining the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in the embodiments of this application.

[0140] In step S1340, the number of instruction types of the memory access instructions that have not been moved is obtained, thereby obtaining the total number of target read instructions and the total number of target write instructions.

[0141] Of course, the memory access instruction that is not moved does not mean that no logical shift was performed, but rather that the data bits that are 1 remain in the original data bit length after the logical shift.

[0142] Please continue to refer to this. Figure 10 Therefore, the total number of target read instructions is 1 and the total number of target write instructions is 2.

[0143] It is easy to understand that when the instruction issue sequence obtained in step S1320 above only includes the read instruction issue sequence, the target total number of read instructions can only be obtained first, and the target total number of write memory accesses also needs to be calculated. At this time, it is only necessary to calculate the difference between the target total number of read and write memory accesses and the target total number of read instructions. When the instruction issue sequence obtained in step S1320 above only includes the write instruction issue sequence, the target total number of write instructions can only be obtained first, and the difference between the target total number of read and write memory accesses and the target total number of write instructions also needs to be calculated before the target total number of write instructions can be obtained.

[0144] In this way, based on the total number of target read / write instructions and the order in which the instruction types are issued, the number of the instruction types of each memory access instruction that are issued last, equal to the total number of target read / write instructions, can be obtained, thus yielding the total number of target read instructions and the total number of target write instructions. The method for obtaining these instructions is simple and easy to implement.

[0145] To obtain the target total number of read commands and the target total number of write commands based on the target total number of read and write commands and the order in which the command types are issued, this application also provides another specific implementation method. Please refer to [link / reference needed]. Figure 11 , Figure 11 Another flowchart illustrating the acquisition of the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in this application embodiment is shown.

[0146] like Figure 11 As shown, the steps for obtaining the target total number of read instructions and the target total number of write instructions in the instruction execution control method provided in this application embodiment include:

[0147] In step S1350, the total number of currently valid read / write memory access instructions and the total number of current instructions are obtained. Based on the total number of current read / write instructions and the target total number of read / write instructions, the instruction quantity difference is obtained.

[0148] For details of step S1350, please refer to [link / reference]. Figure 8 The description of step S1310 shown will not be repeated here.

[0149] Of course, unlike step S1310, it is also necessary to obtain the current total number of instructions. The current total number of instructions mentioned in this article refers to at least one of the current total number of read instructions and the current total number of write instructions.

[0150] In order to read the current total number of instructions, in one specific implementation, the current total number of instructions can be read through a corresponding instruction counter, which includes a read instruction counter and a write instruction counter.

[0151] This allows for full utilization of the physical structure that supports the designed out-of-order execution, reducing the complexity of the physical structure.

[0152] Combination Figure 9 In the example shown, the total number of current read instructions is 4, and the total number of current write instructions is also 4.

[0153] In step S1360, based on the instruction quantity difference and the instruction type issuance order, the quantity of the earliest issued instruction type of each memory access instruction is obtained, and the total number of instructions to be completed is obtained.

[0154] It should be noted that the total number of instructions to be completed as mentioned in this article refers to at least one of the total number of read instructions to be completed and the total number of write instructions to be completed; and it is consistent with the total number of instructions to be completed in step S1350, that is, if the total number of read instructions to be completed is obtained, then the total number of read instructions to be completed is obtained; if the total number of write instructions to be completed is obtained, then the total number of write instructions to be completed is obtained.

[0155] In one specific embodiment, please refer to the details of step S1360. Figure 12 , Figure 12 This paper illustrates a flowchart of the instruction execution control method provided in this application, which obtains the total number of instructions to be completed.

[0156] like Figure 12 As shown, the steps for obtaining the total number of instructions in the instruction control method provided in this application embodiment include:

[0157] In step S1361, at least one of the read instruction issuance order and the write instruction issuance order is obtained according to the instruction type issuance order to obtain the instruction issuance order.

[0158] For details of step S1361, please refer to [link / reference]. Figure 8 The description of step S1320 shown will not be repeated here.

[0159] In step S1362, the instruction issuance sequence is shifted by a target number of bits from the side of the earliest issued memory access instruction through logical operations and logical shifts.

[0160] For details of step S1362, please refer to [link / reference]. Figure 8 The description of step S1330 shown will not be repeated here.

[0161] In step S1363, the number of instruction types corresponding to the memory access instructions that have been moved is obtained to obtain the total number of instructions that need to be completed.

[0162] For details of step S1363, please refer to [link / reference]. Figure 8 The description of step S1340 shown will not be repeated here.

[0163] Of course, what is obtained is the moved memory access instruction. The moved memory access instruction does not refer to an instruction that has undergone logical shifting, but rather to an instruction that has logically shifted from the original data bit length portion to the extended data bit length portion where the value is 1.

[0164] Of course, depending on the order in which the instructions are issued, the total number of instructions that need to be completed at the moment can be either the total number of read instructions or the total number of write instructions, or it can be both the total number of read instructions and the total number of write instructions.

[0165] Please continue to refer to this. Figure 10 Based on the aforementioned case, the total number of read instructions to be completed is 3, and the total number of write instructions to be completed is 2.

[0166] In step S1370, the difference between the current total number of instructions and the current total number of instructions to be completed is obtained to obtain the target total number of read instructions and the target total number of write instructions.

[0167] By obtaining the difference between the current total number of instructions and the current total number of instructions to be completed, the target total number of read instructions and the target total number of write instructions can be obtained.

[0168] Continue to combine Figure 10 In the example shown, the total number of target read instructions is 4-3=1, and the total number of target write instructions is 4-2=2.

[0169] In this way, based on the total number of target read and write instructions and the order in which the instruction types are issued, the number of the earliest issued memory access instructions can be obtained, which is equal to the difference in the number of instructions. Alternatively, the total number of target read instructions and the total number of target write instructions can be obtained, and the instruction types of the latest issued memory access instructions can be obtained. This method is easier to implement at the physical layer and has less design difficulty.

[0170] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0171] This application also provides an instruction execution control device, which can be considered as a functional module required to implement the instruction execution control method provided in this application. The device described below can be referred to in correspondence with the method described above.

[0172] As an alternative implementation scheme, please refer to Figure 13a and Figure 13b , Figure 13a A frame diagram of the instruction execution control device provided in an embodiment of this application is shown; Figure 13b This diagram illustrates a framework of the module for obtaining the target total number of read / write instructions and the type of memory access instructions in an embodiment of this application. Figure 13a and Figure 13b As shown, the instruction execution control device may include:

[0173] The instruction issuing module 210 is adapted to issue a memory access wait instruction, including a target total number of read and write instructions. The target total number of read and write instructions is a target number that the currently valid read and write memory access instructions must not exceed. The memory access wait instruction is adapted to block the issuance of subsequent instructions until the currently valid read and write memory access instructions are not greater than the target total number of read and write instructions.

[0174] The target total number of read / write instructions and memory access instruction type acquisition module 220 is adapted to acquire the target total number of read / write instructions and the instruction type issuance order of each of the currently valid memory access instructions.

[0175] The target read instruction total and target write instruction total acquisition module 230 is adapted to acquire the target read instruction total and target write instruction total based on the target read instruction total and the instruction type issuance order, wherein the sum of the target read instruction total and the target write instruction total is equal to the target read instruction total.

[0176] In some embodiments, the target read / write instruction total quantity and memory access instruction type acquisition module 220 includes:

[0177] The type information and valid memory access information acquisition unit 221 is adapted to acquire the type information and valid memory access information of each memory access instruction arranged in the order of instruction issuance, wherein the valid memory access information identifies the validity of each memory access instruction currently being executed.

[0178] The instruction type issue order acquisition unit 222 is adapted to combine the type information and the valid memory access information to obtain the instruction type issue order.

[0179] In some embodiments, the type information and valid memory access information acquisition unit 221 is adapted to acquire the type information and valid memory access information of each memory access instruction arranged sequentially according to the instruction issuance order, including:

[0180] The type information of each memory access instruction arranged in the order of instruction issuance is obtained through the memory access type register, and each bit of the memory access type register records the type of the corresponding memory access instruction.

[0181] In some embodiments, the type information and valid memory access information acquisition unit 221 is adapted to acquire the type information of each memory access instruction arranged sequentially according to the instruction issuance order through a memory access type register, including:

[0182] The valid memory access information is obtained through the memory access type register and the valid identifier register corresponding to each bit of the memory access type register. Each bit of the valid identifier register records the validity of each corresponding memory access instruction.

[0183] In some embodiments, the target read instruction total and target write instruction total acquisition module 230 is adapted to acquire the target read instruction total and target write instruction total based on the target read instruction total and the instruction type issuance order, including:

[0184] Based on the total number of target read / write instructions and the order in which the instruction types are issued, the number of the instruction types of each memory access instruction that are issued last, whose quantity is equal to the total number of target read / write instructions, is obtained, thus obtaining the total number of target read instructions and the total number of target write instructions.

[0185] In some embodiments, the target total read instruction count and target total write instruction count acquisition module 230 is adapted to acquire, based on the target total read instruction count and the instruction type issuance order, the number of the latest issued instruction type among all memory access instructions, equal to the target total read instruction count, to obtain the target total read instruction count and target total write instruction count, including:

[0186] Obtain the total number of currently valid read / write memory access instructions, and obtain the instruction quantity difference based on the current total number of read / write instructions and the target total number of read / write instructions;

[0187] Based on the instruction type issuance order, at least one of the read instruction issuance order and the write instruction issuance order is obtained to obtain the instruction issuance order;

[0188] Through logical operations and logical shifts, the instruction issuance sequence is shifted by a target number of bits from the side of the earliest issued memory access instruction, and the target number of bits is equal to the instruction quantity difference.

[0189] Obtain the number of instruction types of the memory access instructions that have not been moved, and thus obtain the total number of target read instructions and the total number of target write instructions.

[0190] In some embodiments, the target read instruction total and target write instruction total acquisition module 230 is further adapted to:

[0191] Obtain the current total number of read / write instructions and the current total number of instructions currently being executed. Based on the current total number of read / write instructions and the target total number of read / write instructions, obtain the instruction quantity difference, wherein the current total number of instructions includes at least one of the current total number of read instructions and the current total number of write instructions.

[0192] Based on the instruction quantity difference and the instruction type issuance order, obtain the quantity of the earliest issued instruction type of each memory access instruction, which is equal to the instruction quantity difference, to obtain the total number of instructions that need to be completed. The total number of instructions that need to be completed includes at least one of the total number of read instructions and the total number of write instructions that need to be completed.

[0193] The difference between the current total number of instructions and the current total number of instructions to be completed is obtained to obtain the target total number of read instructions and the target total number of write instructions.

[0194] In some embodiments, the target read instruction total and target write instruction total acquisition module 230 is further adapted to acquire, based on the instruction quantity difference and the instruction type issuance order, the quantity of the earliest issued instruction type of each memory access instruction equal to the instruction quantity difference, to obtain the current total number of instructions to be completed. The current total number of instructions to be completed includes at least one of the current total number of read instructions to be completed and the current total number of write instructions to be completed, including:

[0195] Based on the instruction type issuance order, at least one of the read instruction issuance order and the write instruction issuance order is obtained to obtain the instruction issuance order;

[0196] Through logical operations and logical shifts, the instruction issuance sequence is shifted by a target number of bits from the side of the earliest issued memory access instruction, and the target number of bits is equal to the instruction quantity difference.

[0197] Obtain the number of instruction types corresponding to the memory access instructions that have been moved, and get the total number of instructions that need to be completed.

[0198] In some embodiments, the target read instruction total and target write instruction total acquisition module 230 is further adapted to acquire the current instruction total of currently valid read and write memory access instructions, including:

[0199] The current total number of instructions is read by the corresponding instruction counter, which includes a read instruction counter and a write instruction counter.

[0200] In some embodiments, the command issuing module 210 is further adapted to:

[0201] When the total number of current read instructions acquired is less than or equal to the target total number of read instructions, and the total number of current write instructions acquired is less than or equal to the target total number of write instructions, the next instruction of the memory access wait instruction is issued.

[0202] The instruction execution control device provided in this application only converts the total number of target read and write instructions in the compiled executable program that are waiting for memory access instructions into the total number of target read instructions and the total number of target write instructions. It does not need to change the program itself, so it does not need to obtain the source program and recompile it. It can realize the out-of-order execution of the read and write memory access instructions that are compiled and executed in sequence in the program. Therefore, the instruction execution control device provided in this application can easily realize the execution of the program that executes the compiled read and write memory access instructions in sequence by means of out-of-order execution, thereby achieving good compatibility with historical instructions and programs. At the same time, since out-of-order execution is more efficient than sequential execution, changing the execution mode of the read and write memory access instructions that are compiled and executed in sequence in the program to out-of-order execution can also improve the overall execution speed of the program.

[0203] This application also provides a processor to implement the instruction execution control method described in any embodiment of this application. Please refer to [reference needed] for details. Figure 5

[0204] like Figure 5 As shown, the processor 400 includes:

[0205] The memory access type register 420 records the type of memory access instruction in each bit.

[0206] The validity identifier register 410 has each bit recording the validity of the corresponding memory access instruction.

[0207] This application also provides an electronic device, which includes the instruction execution control device provided above in this application.

[0208] The processor and electronic device provided in this application only convert the total number of target read and write instructions in the memory access wait instructions of the compiled executable program into the total number of target read instructions and the total number of target write instructions. It does not require changing the program itself. Therefore, it does not require obtaining the source program and recompiling it. It can realize the out-of-order execution of the read and write memory access instructions compiled in the program that are executed in sequence. Therefore, the processor and electronic device provided in this application can easily realize the execution of the program that executes the compiled read and write memory access instructions in sequence by means of out-of-order execution, thereby achieving good compatibility with historical instructions and programs. At the same time, since out-of-order execution is more efficient than sequential execution, changing the execution method of the read and write memory access instructions compiled in sequence in the program to out-of-order execution can also improve the overall execution speed of the program.

[0209] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for controlling instruction execution, characterized in that, Suitable for processors, including: The instruction to issue a memory access wait instruction includes a target total number of read and write instructions, wherein the target total number of read and write instructions is a target number that the currently valid read and write memory access instructions must not exceed, and the instruction to issue a memory access wait instruction is adapted to block the issuance of subsequent instructions until the currently valid read and write memory access instructions are not greater than the target total number of read and write instructions. Obtain the total number of target read / write instructions and the instruction type issuance order of each currently valid memory access instruction; Based on the total number of target read and write instructions and the order of instruction type issuance, the total number of target read instructions and the total number of target write instructions are obtained, and the sum of the total number of target read instructions and the total number of target write instructions is equal to the total number of target read and write instructions. When the total number of current read instructions acquired is less than or equal to the target total number of read instructions, and the total number of current write instructions acquired is less than or equal to the target total number of write instructions, the next instruction of the memory access wait instruction is issued. The step of obtaining the total number of target read commands and the total number of target write commands based on the total number of target read and write commands and the order in which the command types are issued includes: Based on the total number of target read / write instructions and the order in which the instruction types are issued, obtain the number of instruction types of each memory access instruction that are issued last and whose number is equal to the total number of target read / write instructions, and thus obtain the total number of target read instructions and the total number of target write instructions. Alternatively, the step of obtaining the target total number of read commands and the target total number of write commands based on the target total number of read and write commands and the command type issuance order includes: Obtain the current total number of read / write instructions and the current total number of instructions currently being executed. Based on the current total number of read / write instructions and the target total number of read / write instructions, obtain the instruction quantity difference, wherein the current total number of instructions includes at least one of the current total number of read instructions and the current total number of write instructions. Based on the instruction quantity difference and the instruction type issuance order, obtain the quantity of the earliest issued instruction type of each memory access instruction, which is equal to the instruction quantity difference, to obtain the total number of instructions that need to be completed. The total number of instructions that need to be completed includes at least one of the total number of read instructions and the total number of write instructions that need to be completed. The difference between the current total number of instructions and the current total number of instructions to be completed is obtained to obtain the target total number of read instructions and the target total number of write instructions.

2. The instruction execution control method as described in claim 1, characterized in that, The step of obtaining the instruction type issuance order of each of the currently executing memory access instructions includes: Obtain the type information and valid memory access information of each memory access instruction arranged in the order of instruction issuance, wherein the valid memory access information identifies the validity of each memory access instruction currently being executed. By combining the type information and the valid memory access information, the instruction type issue order is obtained.

3. The instruction execution control method as described in claim 2, characterized in that, The step of obtaining the type information of each memory access instruction arranged in the instruction issuance order includes: The type information of each memory access instruction arranged in the order of instruction issuance is obtained through the memory access type register, and each bit of the memory access type register records the type of the corresponding memory access instruction.

4. The instruction execution control method as described in claim 3, characterized in that, The steps for obtaining valid memory access information include: The valid memory access information is obtained through the memory access type register and the valid identifier register corresponding to each bit of the memory access type register. Each bit of the valid identifier register records the validity of each corresponding memory access instruction.

5. The instruction execution control method as described in claim 1, characterized in that, The step of obtaining the number of instruction types of each memory access instruction that is the latest issued and equal to the total number of target read instructions, based on the total number of target read / write instructions and the issuance order of the instruction types, to obtain the total number of target read instructions and the total number of target write instructions, includes: Obtain the total number of currently valid read / write memory access instructions, and obtain the instruction quantity difference based on the current total number of read / write instructions and the target total number of read / write instructions; Based on the instruction type issuance order, at least one of the read instruction issuance order and the write instruction issuance order is obtained to obtain the instruction issuance order; Through logical operations and logical shifts, the instruction issuance sequence is shifted by a target number of bits from the side of the earliest issued memory access instruction, and the target number of bits is equal to the instruction quantity difference. Obtain the number of instruction types of the memory access instructions that have not been moved, and thus obtain the total number of target read instructions and the total number of target write instructions.

6. The instruction execution control method as described in claim 1, characterized in that, The step of obtaining the number of instruction types of each memory access instruction that was issued earliest, whose quantity is equal to the instruction quantity difference, based on the instruction quantity difference and the instruction type issuance order, and thus obtaining the total number of instructions to be completed, includes: Based on the instruction type issuance order, at least one of the read instruction issuance order and the write instruction issuance order is obtained to obtain the instruction issuance order; Through logical operations and logical shifts, the instruction issuance sequence is shifted by a target number of bits from the side of the earliest issued memory access instruction, and the target number of bits is equal to the instruction quantity difference. Obtain the number of instruction types corresponding to the memory access instructions that have been moved, and get the total number of instructions that need to be completed.

7. The instruction execution control method as described in claim 1, characterized in that, The step of obtaining the total number of currently executing read / write memory access instructions includes: The current total number of instructions is read by the corresponding instruction counter, which includes a read instruction counter and a write instruction counter.

8. An instruction execution control device, characterized in that, Suitable for processors, including: The instruction issuing module is adapted to issue a memory access wait instruction, including a target total number of read and write instructions. The target total number of read and write instructions is a target number that the currently valid read and write memory access instructions must not exceed. The memory access wait instruction is adapted to block the issuance of subsequent instructions until the currently valid read and write memory access instructions are not greater than the target total number of read and write instructions. The target total number of read / write instructions and memory access instruction type acquisition module is adapted to acquire the target total number of read / write instructions and the instruction type issuance order of each currently valid memory access instruction; The target read instruction total and target write instruction total acquisition module is adapted to acquire the target read instruction total and target write instruction total based on the target read instruction total and the instruction type issuance order, wherein the sum of the target read instruction total and the target write instruction total is equal to the target read instruction total; The command issuing module is further adapted to: When the total number of current read instructions acquired is less than or equal to the target total number of read instructions, and the total number of current write instructions acquired is less than or equal to the target total number of write instructions, the next instruction of the memory access wait instruction is issued. The target read instruction total and target write instruction total acquisition module is adapted to acquire the target read instruction total and target write instruction total based on the target read instruction total and the instruction type issuance order, including: Based on the total number of target read / write instructions and the order in which the instruction types were issued, obtain the number of each memory access instruction type that was issued last, equal to the total number of target read / write instructions, to obtain the total number of target read instructions and the total number of target write instructions; or, Obtain the current total number of read / write instructions and the current total number of instructions currently being executed. Based on the current total number of read / write instructions and the target total number of read / write instructions, obtain the instruction quantity difference, wherein the current total number of instructions includes at least one of the current total number of read instructions and the current total number of write instructions. Based on the instruction quantity difference and the instruction type issuance order, obtain the quantity of the earliest issued instruction type of each memory access instruction, which is equal to the instruction quantity difference, to obtain the total number of instructions that need to be completed. The total number of instructions that need to be completed includes at least one of the total number of read instructions and the total number of write instructions that need to be completed. The difference between the current total number of instructions and the current total number of instructions to be completed is obtained to obtain the target total number of read instructions and the target total number of write instructions.

9. The instruction execution control device as described in claim 8, characterized in that, The module for obtaining the total number of target read / write instructions and the type of memory access instructions includes: The type information and valid memory access information acquisition unit is adapted to acquire the type information and valid memory access information of each memory access instruction arranged in the order of instruction issuance, wherein the valid memory access information identifies the validity of each memory access instruction currently being executed. The instruction type issue order acquisition unit is adapted to combine the type information and the valid memory access information to obtain the instruction type issue order.

10. The instruction execution control device as described in claim 9, characterized in that, The type information and valid memory access information acquisition unit is adapted to acquire the type information and valid memory access information of each memory access instruction arranged sequentially according to the instruction issuance order, including: The type information of each memory access instruction arranged in the order of instruction issuance is obtained through the memory access type register, and each bit of the memory access type register records the type of the corresponding memory access instruction.

11. The instruction execution control device as described in claim 10, characterized in that, The type information and valid memory access information acquisition unit is adapted to acquire the type information of each memory access instruction arranged sequentially according to the instruction issuance order through the memory access type register, including: The valid memory access information is obtained through the memory access type register and the valid identifier register corresponding to each bit of the memory access type register. Each bit of the valid identifier register records the validity of each corresponding memory access instruction.

12. The instruction execution control device as described in claim 8, characterized in that, The target read instruction total and target write instruction total acquisition module is adapted to acquire, based on the target read instruction total and the instruction type issuance order, the number of instruction types of each memory access instruction that is the latest issued and whose quantity is equal to the target read instruction total, to obtain the target read instruction total and target write instruction total, including: Obtain the total number of currently valid read / write memory access instructions, and obtain the instruction quantity difference based on the current total number of read / write instructions and the target total number of read / write instructions; Based on the instruction type issuance order, at least one of the read instruction issuance order and the write instruction issuance order is obtained to obtain the instruction issuance order; Through logical operations and logical shifts, the instruction issuance sequence is shifted by a target number of bits from the side of the earliest issued memory access instruction, and the target number of bits is equal to the instruction quantity difference. Obtain the number of instruction types of the memory access instructions that have not been moved, and thus obtain the total number of target read instructions and the total number of target write instructions.

13. The instruction execution control device as described in claim 8, characterized in that, The target read instruction total and target write instruction total acquisition module is further adapted to acquire, based on the instruction quantity difference and the instruction type issuance order, the quantity of the earliest issued instruction type of each memory access instruction equal to the instruction quantity difference, to obtain the current total number of instructions to be completed. The current total number of instructions to be completed includes at least one of the current total number of read instructions to be completed and the current total number of write instructions to be completed, including: Based on the instruction type issuance order, at least one of the read instruction issuance order and the write instruction issuance order is obtained to obtain the instruction issuance order; Through logical operations and logical shifts, the instruction issuance sequence is shifted by a target number of bits from the side of the earliest issued memory access instruction, and the target number of bits is equal to the instruction quantity difference. Obtain the number of instruction types corresponding to the memory access instructions that have been moved, and get the total number of instructions that need to be completed.

14. The instruction execution control device as described in claim 8, characterized in that, The target read instruction total and target write instruction total acquisition module is also adapted to acquire the current instruction total of currently valid read and write memory access instructions, including: The current total number of instructions is read by the corresponding instruction counter, which includes a read instruction counter and a write instruction counter.

15. A processor, characterized in that, Suitable for implementing the instruction execution control method as described in any one of claims 1-7, comprising: The memory access type register records the type of memory access instruction in each bit. The validity identifier register contains bits that record the validity of each corresponding memory access instruction.

16. An electronic device, characterized in that, Includes the instruction execution control device as described in any one of claims 8-14.

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