Data verification method, device, computer equipment and storage medium of a memory

Abstract

The present invention discloses a data verification method, device, computer device, and storage medium for a memory. A redundant array of independent disks has N*B redundant array blocks and B*P row storage pages and is connected to W word lines. Each redundant array block includes P storage pages, and each word line is connected to (B*P) / W row storage pages. The method includes setting a redundant array tag group having P different redundant array tags, where one redundant array tag group corresponds to one row of redundant array blocks, and taking the redundant array block located in the Nth physical storage platform in the first row of redundant array blocks as the first parity check data storage block. Therefore, the user data pages in the first P row storage pages corresponding to the first parity check data storage block can be accurately verified, which is equivalent to improving the protection factor of the user data pages corresponding to the bottom P / ((B*P) / W) word lines.

Description

Technical Field

[0001] The present invention generally relates to electronic devices, and more specifically, to a data verification method and apparatus for a memory, a computer device, and a storage medium. Background Art

[0002] As the amount of Nand flash increases, system storage products will increase data reliability. In addition to the Error Checking and Correcting (ECC) module protection, they will also add a raid parity algorithm to correct errors in user data pages. Therefore, the raid parity algorithm is becoming more and more important.

[0003] Due to the defects in the development stage of Nand flash and the limitations of the process, some known failure codes will be generated. However, as the number of word lines (WL) of Nand flash increases, it is difficult to make all word lines have channel holes (CH) with the same aperture size from the process perspective, or due to the process limitations of other manufacturing processes, it cannot be guaranteed that the probability of problems occurring in all word lines is the same. There will definitely be some word lines that are more easily damaged, but the existing verification data verification method has a low verification rate for the user data pages corresponding to these word lines, that is, a low protection coefficient. Summary of the invention

[0004] The object of the present invention is to provide a data verification method, device, computer equipment and storage medium of a memory, aiming to improve the protection factor of the user data page corresponding to the bottom P / ((B*P) / W) word lines.

[0005] On the one hand, the present invention provides a data verification method for a memory, wherein the memory includes N parallel physical storage platforms, each of which includes B storage blocks, so that the N physical storage platforms constitute an independent disk redundant array with N*B redundant array blocks, the independent disk redundant array includes B rows of redundant array blocks, each of which includes P storage pages, and the storage pages are used to store user data pages; the N physical storage platforms are connected to W word lines and have B*P row storage pages, each of which is connected to (B*P) / W row storage pages, and N, B, P, W are positive integers and N>2; the data verification method includes:

[0006] Set a redundant array tag group with P different redundant array tags. The first to the Bth redundant array blocks respectively correspond to the first to the Bth redundant array tag groups. The P row storage pages in each row of the redundant array blocks respectively correspond to the P redundant array tags in each redundant array tag group;

[0007] Take the redundant array block in the first row of the redundant array blocks located in the Nth physical storage platform as the first parity check data storage block for storing P first parity check data pages. Each of the first parity check data pages corresponds to one of the redundant array tags in the first redundant array tag group and is used to check the user data pages in the row storage pages corresponding to the corresponding redundant array tag.

[0008] Further preferably, the data verification method further includes:

[0009] Take the redundant array block in the Bth row of the redundant array blocks located in the Nth physical storage platform as the second parity check data storage block for storing P second parity check data pages. Each of the second parity check data pages is used to check the user data pages in the row storage pages corresponding to the same redundant array tag in the second to the Bth redundant array tag groups.

[0010] Further preferably, the memory further includes SRAM, and the data verification method further includes:

[0011] Perform an exclusive OR operation on the user data pages in the row storage pages corresponding to each redundant array tag in the first redundant array tag group and located in the first N - 1 physical storage platforms to obtain one first parity check data page, and cache the obtained P first parity check data pages in the SRAM;

[0012] Copy the P first parity check data pages to the first parity check data storage block for storage and initialize the SRAM.

[0013] Further preferably, the data verification method further includes:

[0014] Cache the user data pages in the row storage pages corresponding to the same redundant array tag in the second to the B - 1th redundant array tag groups in the SRAM, and perform an exclusive OR operation each time one user data page is cached to obtain P second parity check data pages;

[0015] The user data pages located in the first N-1 physical storage platforms in the row storage page corresponding to each redundant array tag in the B-th redundant array tag group are cached in the SRAM, and an exclusive-OR operation is performed once for each cached user data page to update the P second parity check data pages;

[0016] The P second parity data pages are copied to the second parity data storage block for storage.

[0017] Further preferably, the redundant array blocks in the first row are located at the bottom of the memory, and the redundant array blocks in the Bth row are located at the top of the memory; among the P rows of row storage pages in the first row of the redundant array blocks, the word lines connecting the first (B*P) / W row storage pages are located at the bottom of the memory, and among the P rows of row storage pages in the Bth row of the redundant array blocks, the word lines connecting the last (B*P) / W row storage pages are located at the top of the memory.

[0018] Further preferably, the data verification method further includes:

[0019] When the SRAM is powered off, copying the P first parity data pages cached in the SRAM to the memory for storage;

[0020] When the SRAM is powered on again, the P first parity data pages copied to the memory are copied to the SRAM for storage.

[0021] Further preferably, the data verification method further includes:

[0022] The redundant array blocks in one or more rows of the redundant array blocks in the second row to the B-1th row, which are located in the Nth physical storage platform, are used as third parity data storage blocks to store third parity data.

[0023] On the other hand, the present invention provides a data verification device for a memory, wherein the memory includes N parallel physical storage platforms, each of which includes B storage blocks, so that the N physical storage platforms constitute an independent disk redundant array with N*B redundant array blocks, the independent disk redundant array includes B rows of redundant array blocks, each of which includes P storage pages, and the storage pages are used to store user data pages; the N physical storage platforms are connected to W word lines and have B*P row storage pages, each word line is connected to (B*P) / W row storage pages, and N, B, P, W are positive integers and N>2; the data verification device includes:

[0024] A setting module, configured to set a redundant array tag group having P different redundant array tags. The P redundant array tags in each redundant array tag group are arranged in the same order. Each row of the redundant array blocks corresponds to one redundant array tag group. The first to the Pth row storage pages in each row of the redundant array blocks respectively correspond to the first to the Pth redundant array tags in each redundant array tag group. The same redundant array tag corresponds to B row storage pages. Among them, the first to the Bth rows of the redundant array blocks respectively correspond to the first to the Bth redundant array tag groups;

[0025] A first setting module, configured to use the redundant array block located in the Nth entity storage platform in the first row of the redundant array blocks as the first parity check data storage block for storing P first parity check data pages. Each of the first parity check data pages corresponds to one redundant array tag in the first redundant array tag group and is used to check the user data pages in the row storage pages corresponding to the corresponding redundant array tag.

[0026] On the other hand, the present invention provides a computer device, including a memory and a processor; wherein,

[0027] The memory is configured to save user data;

[0028] The processor is configured to execute a computer program to implement the steps in the data verification method described in any one of the above.

[0029] On yet another hand, the present invention provides a computer storage medium for saving a computer program. When the computer program is executed by a processor, the data verification method described in any one of the above is implemented.

[0030] The beneficial effects of the present invention are as follows: A data verification method, device, computer device, and computer storage medium for a memory are provided. In this memory, N entity storage platforms form an independent disk redundant array with N*B redundant array blocks and are connected to B*P row storage pages. Each of the redundant array blocks includes P storage pages. The N entity storage platforms are connected to W word lines, and each word line is connected to (B*P) / W of the row storage pages. The verification method includes setting a redundant array tag group with P different redundant array tags. One redundant array tag group corresponds to one row of redundant array blocks. The redundant array block located in the Nth entity storage platform in the first row of the redundant array blocks is used as the first parity check data storage block. Since the first parity check data storage block is located in the redundant array block corresponding to the Nth entity storage platform in the first row of the redundant array blocks, the first parity check data storage block can accurately verify the user data pages in the first P row storage pages, which is equivalent to improving the protection coefficient of the user data pages corresponding to the bottom P / ((B*P) / W) word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The following will, with reference to the accompanying drawings, make the technical solutions and other beneficial effects of the present invention obvious through a detailed description of the specific embodiments of the present invention.

[0032] Figure 1 is a schematic diagram of data verification through a parity check data storage block provided by an embodiment of the present invention;

[0033] Figure 2 is a flowchart of a data verification method for a memory provided by an embodiment of the present invention;

[0034] Figure 3 is a flowchart of a data verification method for a memory provided by a further embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of data verification through a parity check data storage block provided by a specific embodiment of the present invention;

[0036] Figure 5 is a schematic diagram of a data verification method through a parity check data storage block provided by the present invention;

[0037] Figure 6 is a schematic structural diagram of a data verification device for a memory provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0039] It should be understood that although terms such as first and second can be used here to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component can be called the second component, and similarly, the second component can be called the first component without departing from the scope of the present invention.

[0040] It should be noted that the diagrams provided in the embodiments of the present invention only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the types, numbers, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex. Some disk array parity check algorithms can use more parity check data storage blocks to check the corresponding user data pages. However, if the positions of the parity check data storage blocks are all symmetric, for example, each parity check data storage block covers the same number of user data pages, this makes the check rates of all user data pages equal, that is, there is no difference in the check rates of the user data pages corresponding to all word lines.

[0041] The inventor has found through research that the word lines at the bottom of the memory are more likely to be damaged than other word lines. The probability of leakage of the 0-4 word lines at the bottom is much greater than that of other word lines. Therefore, in fact, the probabilities of damage of word lines at different positions are different. So, the symmetric setting of the parity check data storage blocks cannot improve the check rate of the user data pages corresponding to the bottom word lines. Moreover, using more parity check data storage blocks will also increase the storage space overhead.

[0042] Please refer to Figure 1 , Figure 1It is a schematic diagram of data verification through parity check data storage blocks provided by an embodiment of the present invention. The memory may include NAND, and the memory includes N parallel physical storage platforms (plane1~planeN). Each physical storage platform (plane) includes B storage blocks (block0~blockB-1). Only 4 storage blocks are shown in the figure, and the storage blocks between block2~blockB-1 are omitted. One storage block in each physical storage platform corresponds to a redundant array block. Therefore, the N physical storage platforms constitute an independent disk redundant array (Redundant Array of Independent Disks, RAID) with N*B redundant array blocks. The independent disk redundant array includes B rows of redundant array blocks and N columns of redundant array blocks. The redundant array block corresponding to block0 of the physical storage platform plane0 is marked with a thick black square frame in the figure, and the other redundant array blocks are similar. Each redundant array block includes P storage pages, and each storage page is used to store a user data page. The user data page is represented by user in the figure.

[0043] In this embodiment, multiple storage pages in the same row can be referred to as a row storage page (page). Therefore, each row of redundant array blocks includes P row storage pages, and further, the N physical storage platforms have B*P row storage pages (page0~pageB*P-1). For example, the first row of redundant array blocks includes page0~pageP-1, the second row of redundant array blocks includes pageP~page2P-1, the third row of redundant array blocks includes page2P~page3P-1, and the Bth row of redundant array blocks includes page(B-1)*P~pageB*P-1. In the figure, all row storage pages (page) are numbered in order to correspond to their positions in the physical structure of the memory. The numbers of the row storage pages represent the position order of the row storage pages. For example, the numbers of the row storage pages are arranged from small to large from the bottom to the top of the memory, and at the same time, it also represents that block0~blockB-1 are located from the bottom to the top of the memory, and the first row of redundant array blocks~the Bth row of redundant array blocks are located from the bottom to the top of the memory.

[0044] In this embodiment, the N physical storage platforms can be connected to W word lines. Since the N physical storage platforms have B*P row storage pages, each word line is connected to (B*P) / W row storage pages (page). Then, corresponding to the physical structure of the memory, a word line connected to the first (B*P) / W row storage pages is located at the bottom of the memory, and a word line connected to the last (B*P) / W row storage pages is located at the top of the memory.

[0045] It should be noted that N, B, P, and W are positive integers and N > 2, that is, the physical storage platform of the memory has at least 3, and generally the number of physical storage platforms is an even number.

[0046] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of the data verification method of the memory provided by an embodiment of the present invention. The data verification method includes the following steps S1 - S3.

[0047] Step S1: Set a redundant array tag group (tag0 to tagP - 1) with P different redundant array tags.

[0048] In this embodiment, the P different redundant array tags in each redundant array tag group are arranged in the same order, such as tag0 to tagP - 1. Therefore, the serial numbers of the same redundant array tag can represent the same redundant array tag, and the serial numbers of different redundant array tags represent different redundant array tags. Each redundant array tag group corresponds to a row of redundant array blocks. Therefore, there are B redundant array tag groups, and the first to the Bth rows of redundant array blocks correspond to the first to the Bth redundant array tag groups respectively. The first to the Pth redundant array tags (tag0 to tagP - 1) in each redundant array tag group correspond to the first to the Pth row storage pages (such as page0 to pageP - 1, pageP to page2P - 1, etc.) in each row of redundant array blocks. Among them, the functions of setting the redundant array tags and the redundant array tag group will be explained in detail in the subsequent steps.

[0049] Step S2: Use the redundant array block located on the Nth physical storage platform in the first row of redundant array blocks as the first parity check data storage block to store P first parity check data pages (parity1).

[0050] In the figure, the first parity check data storage block is represented by the gray part. Among them, one storage page in the first parity check data storage block is used to store one first parity check data page (parity1). Each first parity check data page corresponds to a redundant array tag, and the P first parity check data pages correspond to P different redundant array tags tag0 to tagP - 1.

[0051] Specifically, each first parity data page is used to verify the user data pages in the row storage pages corresponding to the redundant array tags. When an error occurs in the user data pages in the row storage pages corresponding to the redundant array tag corresponding to a first parity page, then this first parity data page can recover these user data pages. Therefore, the user data pages in the P row storage pages corresponding to the first redundant array tag group can be recovered by P first parity data pages. That is, the verification rate of the user data pages in page0 to pageP-1 is 100%, which is equivalent to increasing the protection factor of the user data pages corresponding to the bottom P / ((B*P) / W) word lines.

[0052] It can be understood that the redundant array block is used to store user data pages. After taking the redundant array block located in the Nth physical storage platform in the first row of redundant array blocks as the first parity data storage block, the first parity data storage block is used to store P first parity data pages (parity1), and no longer stores user data pages. Therefore, the user data pages mentioned below do not default to include the user data pages in the redundant array block located in the Nth physical storage platform in the first row of redundant array blocks, because this redundant array block does not store user data pages. Similarly, the second parity data storage block and the third parity data storage block in the following text also do not store user data pages.

[0053] Step S3: Take the redundant array block located in the Nth physical storage platform in the Bth row of redundant array blocks as the second parity data storage block for storing P second parity data pages (parity2).

[0054] Among them, the second parity data storage block, like the first parity data storage block, is used to store P second parity data pages (parity2), and the second parity data storage block is also marked in gray. Different from the first parity data storage block, the first parity data storage block corresponds to only one redundant array tag group, and the second parity data storage block corresponds to the second to the Bth redundant array tag groups (B-1 redundant array tag groups). Each second parity data page is used to verify the user data pages in the row storage pages corresponding to the same redundant array tag (referring to the redundant array tags with the same serial number, such as all tag0) in the B-1 redundant array tag groups. For example, the first parity2 from top to bottom can verify the user data pages in the row storage pages corresponding to tag0 in the B-1 redundant array tag groups, the second parity2 can verify the user data pages in the row storage pages corresponding to tag1 in the B-1 redundant array tag groups, and the Pth parity2 can verify the user data pages in the row storage pages corresponding to tagP-1 in the B-1 redundant array tag groups.

[0055] The redundant array tag is used to jointly verify the user data page with the parity data page. When errors occur in two user data pages corresponding to the same redundant array tag in a parity2, the parity data page cannot recover the faulty user data page. For example, if parity2 corresponds to multiple identical redundant array tags (such as B - 1 tag0s and B - 1 tag1s, etc.), once errors occur in two user data pages corresponding to tag0, they cannot be recovered. Therefore, the more redundant array tag groups (the more user data pages) the parity data page corresponds to, the more identical redundant array tags a parity data page will correspond to, and the lower the verification rate of the corresponding user data pages. So the recovery probability of the user data pages of parity2 is lower than that of parity1, that is, the recovery probability of the user data pages in the redundant array blocks from the second row to the Bth row is lower than that of the user data pages in the redundant array block of the first row.

[0056] In a variant, the data verification method further includes: using one or more redundant array blocks located in the Nth physical storage platform in the redundant array blocks from the second row to the (B - 1)th row as the third parity data storage block for storing the third parity data (without storing user data pages). By adding the third parity data page to share some user data pages, the user data pages corresponding to the second parity data page can be reduced, and thus the verification rate of the user data in the redundant array blocks from the second row to the Bth row can be improved.

[0057] The data verification method of the memory provided by the embodiment of the present invention sets P different redundant array tags, and sets the first parity data storage block at the end of the first row of redundant array blocks (the Nth plane), so that the protection coefficient of the user data pages corresponding to the bottom P / ((B * P) / W) word lines can be improved, and the protection coefficient is almost equal to 1, that is, a 100% recovery probability.

[0058] Please refer to Figure 3 , Figure 3 which is a schematic flowchart of the data verification method of the memory provided by a further embodiment of the present invention. In this embodiment, the memory may include NAND and SRAM, and the data verification method includes the following steps S100 - S800.

[0059] Step S100: Set a redundant array tag group (tag0 ~ tagP - 1) with P different redundant array tags (tag).

[0060] Step S100 is the same as step S1 in the above embodiment and will not be elaborated here.

[0061] Step S200: Perform an exclusive OR operation on the user data pages of the first N - 1 physical storage platforms in the row storage pages corresponding to each redundant array label in the first redundant array label group to obtain a first parity check data page, and cache the obtained P first parity check data pages in the SRAM.

[0062] Step S300: Use the redundant array block located on the Nth physical storage platform in the first row redundant array block as the first parity check data storage block for storing the P first parity check data pages (parity1).

[0063] Step S300 is the same as step S2 in the above embodiment and will not be elaborated here.

[0064] Step S400: Copy the P first parity check data pages to the first parity check data storage block for storage, and initialize the SRAM.

[0065] In this embodiment, the purpose of steps S200 - S400 is to perform an exclusive OR operation on the user data pages in the first row redundant array block in the SRAM to obtain the first parity check data pages. Finally, after storing the first parity check data pages in the first parity check data storage block, the SRAM is initialized. Therefore, the user data pages in the row storage pages corresponding to the first redundant array label group can be restored through the first parity check data pages in the first parity check data storage block. Specifically, each first parity check data page is obtained by performing an exclusive OR operation on the user data pages (N - 1) in the row storage page. When one or more user data pages in a row storage page are in error, the first parity check data page corresponding to the row storage page and the other user data pages in the row storage page can be subjected to an inverse operation to obtain the user data pages in error.

[0066] This data verification method further includes: when the SRAM is powered off, copying the P first parity check data pages cached in the SRAM to the memory for storage; when the SRAM is powered on again, copying the P first parity check data pages copied to the memory back to the SRAM for storage. This is to prevent the loss of the first parity check data pages due to the power-off of the SRAM before the P first parity check data pages are copied to the first parity check data storage block.

[0067] Step S500: Cache the user data pages in the row storage pages corresponding to the same redundant array label in the second to the (B - 1)th redundant array label groups in the SRAM, and perform an exclusive OR operation once for each cached user data page to obtain P second parity check data pages.

[0068] Step S600: Cache the user data pages of the first N - 1 physical storage platforms in the row storage pages corresponding to each redundant array tag in the Bth redundant array tag group in the SRAM, and perform an exclusive OR operation each time a user data page is cached to update the P second parity data pages.

[0069] In this embodiment, the parity2 corresponding to tag0 is obtained by performing an exclusive OR operation on all the user data pages corresponding to tag0 in the second to the B - 1th redundant array tag groups. For example, first cache the user data page of plane0 in page0 corresponding to tag0 in the second redundant array tag group in the SRAM, and then cache the user data page of plane1 in page0 in the SRAM. At this time, an exclusive OR value (parity2) is obtained by performing an exclusive OR operation on the two user data pages. Then, each time a user data page is cached, it is exclusive ORed with the previous exclusive OR value to update parity2 until the user data page of planeN - 1 in tag0 of the B - 1th redundant array tag group is cached, and then parity2 is finally updated. Similarly, the user data corresponding to tag1 to tagP - 1 are also cached and exclusive ORed in the SRAM respectively, and finally the parity2 corresponding to tag1 to tagP - 1 are obtained respectively, so a total of P parity2 are obtained.

[0070] It should be noted that an exclusive OR operation is performed each time a user data page is cached to obtain a new parity2. At this time, the user data page is replaced with parity2. Therefore, only parity2 is stored in the SRAM, and the total storage capacity of the SRAM is P parity2.

[0071] Step S700: Use the redundant array block located on the Nth physical storage platform in the Bth row of redundant array blocks as the second parity data storage block to store the P second parity data pages (parity2).

[0072] Step S700 is the same as step S3 in the above embodiment and will not be elaborated here.

[0073] Step S800: Copy the P second parity data pages to the second parity data storage block for storage.

[0074] Finally, store the P parity2 into the second parity data storage block. Although the overall verification rate of the user data pages of pageP to pageB*P-1 is lower than that of page0 to pageP-1, since the user data pages of pageP to page2P-1 corresponding to the second redundant array tag group can be restored through the parity2 cached in the SRAM, and the user data pages of page0 to pageP-1 corresponding to the first redundant array tag group can be restored through the parity1 in the first parity data storage block, when only the user data pages of the bottom 2P row storage pages have errors, they can be restored through parity1 and parity2, that is, the user data pages corresponding to the bottom 2P / ((B*P) / W) word lines can be restored.

[0075] Please refer to Figure 4 , Figure 4 is a schematic diagram of data verification through a parity data storage block provided by a specific embodiment of the present invention. In this embodiment, the memory includes 8 chips, each chip includes 2 physical storage platforms, so the memory includes 16 physical storage platforms (plane1 to plane16), that is, N is equal to 16. Each physical storage platform includes 18 storage blocks (that is, B is equal to 18), each redundant array block includes 64 storage pages (that is, P is equal to 64), 16 physical storage platforms are connected to 64 word lines (that is, W is equal to 64), and the 16 physical storage platforms have 1152 row storage pages (page0 to page1151), and each word line is connected to 18 row storage pages.

[0076] In this embodiment, 64 redundant array tags (tag0 to tag63) are set. D0 to D270 are user data pages stored in the redundant array block, and the serial numbers represent the storage order. Since the parity1 obtained from the user data pages in the row storage pages (page0 to pageP-1) corresponding to the first redundant array tag group is copied and stored in the first parity data storage block, the SRAM is initialized. Later, the parity2 obtained from the user data pages in the SRAM has nothing to do with the user data pages in page0 to pageP-1, so starting from the user data pages in the row storage pages corresponding to the second redundant array tag group, the user data pages start to be represented from D0.

[0077] Among them, parity1 checks 15 user data pages (D0 to D14), and parity2 checks 271 user data pages (D0 to D270). In addition, the user data pages in page0 to page63 can be restored through parity1 in the first parity check data storage block, and page64 to page127 can be restored through parity2 cached in SRAM. Therefore, 128 row storage pages can be completely restored, that is, when approximately 7 word lines at the bottom are damaged, the corresponding user data pages can be completely restored.

[0078] When 8 word lines (page0 to page143) at the bottom are damaged, the user data pages in page0 to page63 can still be restored through parity1 in the first parity check data storage block. Since page64 to page79 and page128 to page143 correspond to the same redundant array tags respectively, for example, page64 and page128 both correspond to tag0, page65 and page129 both correspond to tag1, and page79 and page143 both correspond to tag15, so the parity2 corresponding to tag0 cannot restore the user data pages corresponding to page64 and page128, and the same applies to others. Therefore, when 8 word lines (page0 to page143) at the bottom are damaged, only the user data pages in page0 to page63 can be completely restored, that is, only the user data pages corresponding to approximately 3 word lines at the bottom can be completely restored, and the recovery probability of other word lines is lower.

[0079] To illustrate the advantage of the position of the first parity check data storage block in the present invention, please compare Figure 5 , Figure 5 is a schematic diagram of data check through a parity check data storage block provided by the present invention. Figure 5 In [reference], the redundant array block located in the Nth physical storage platform in the second row redundant array block is used as the first parity check data storage block. Then each parity1 corresponds to a total of 31 user data pages from D0 to D30, and each parity2 corresponds to a total of 255 user data pages from D0 to D254. Therefore, from the overall check rate perspective, Figure 5 the protection coefficient of parity1 in [reference] for the user data pages corresponding to the 3 word lines at the bottom is higher than that of Figure 4Low. In addition, the data verification method can fully recover the user data pages corresponding to page0 to page63, because the user data pages of each row storage page can be recovered according to parity1 cached in SRAM, which is equivalent to only being able to fully recover the user data pages corresponding to approximately 3 word lines at the bottom. When 4 word lines at the bottom are damaged, it is equivalent to an error occurring in the user data pages corresponding to page0 to page71. Since page0 and page64 both correspond to tag0, page1 and page65 both correspond to tag1, page2 and page66 both correspond to tag2, and so on until page7 and page71 both correspond to tag7, because parity1 corresponds to the user data pages of two identical tags having errors, parity1 cannot recover the user data pages of page0 to page7 and page64 to page71, and thus the data verification method cannot fully recover the user data pages corresponding to 4 word lines.

[0080] In a specific embodiment of the present invention, the position setting of the first parity check data storage block can improve the protection coefficient of the user data pages corresponding to approximately 3 word lines at the bottom, and can also fully recover the user data pages corresponding to 7 word lines at the bottom of the memory. Additionally, compared with Figure 5 In the Figure 4 embodiment provided, the number of parity check data storage blocks is still 2 without increase (i.e., the number of parity check data pages is 128), the cache capacity of the parity check data pages in SRAM is still 64 without increase, and the number of redundant array tags is still 64 without increase. Therefore, there is no need to increase the additional storage space overhead.

[0081] An embodiment of the present invention further provides a data verification device. The memory includes N parallel physical storage platforms, each of the physical storage platforms includes B storage blocks, such that the N physical storage platforms form an independent disk redundant array having N*B redundant array blocks. The independent disk redundant array includes B rows of the redundant array blocks, each of the redundant array blocks includes P storage pages, and the storage pages are used to store user data pages; the N physical storage platforms are connected to W word lines and have B*P row storage pages, and each word line is connected to (B*P) / W of the row storage pages, where N, B, P, and W are positive integers and N>2.

[0082] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of the data verification device of the memory provided by the embodiment of the present invention. The data verification device 60 of the memory includes the following modules.

[0083] A setting module 61 is configured to set a redundant array tag group having P different redundant array tags. The P redundant array tags in each redundant array tag group are arranged in the same order. Each row of the redundant array blocks corresponds to one redundant array tag group. The first to the P-th row storage pages in each row of the redundant array blocks respectively correspond to the first to the P-th redundant array tags in each redundant array tag group. The same redundant array tag corresponds to B row storage pages. Among them, the first to the B-th row of the redundant array blocks respectively correspond to the first to the B-th redundant array tag groups.

[0084] A first setting module 62 is configured to use the redundant array block located in the N-th physical storage platform in the first row of the redundant array blocks as a first parity check data storage block for storing P first parity check data pages. Each of the first parity check data pages corresponds to one redundant array tag in the first redundant array tag group and is used to check the user data pages in the row storage pages corresponding to the corresponding redundant array tag.

[0085] A second setting module 63 is configured to use the redundant array block located in the N-th physical storage platform in the B-th row of the redundant array blocks as a second parity check data storage block for storing P second parity check data pages. Each of the second parity check data pages is used to check the user data pages in the row storage pages corresponding to the same redundant array tag in the second to the B-th redundant array tag groups.

[0086] The data verification device 60 of this memory has the same beneficial effects as the data verification method of the above-mentioned memory, which will not be elaborated here.

[0087] An embodiment of the present invention further provides a computer device, including a memory and a processor. The memory is used to store user data, and the processor is used to execute a computer program to implement the steps in the above data verification method.

[0088] An embodiment of the present invention further provides a computer device for storing a computer program. When the computer program is executed by a processor, the above data verification method is implemented.

[0089] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data verification method for a memory, characterized in that The memory includes N juxtaposed physical storage platforms, each physical storage platform includes B storage blocks, such that the N physical storage platforms constitute an independent disk redundant array with N*B redundant array blocks. The independent disk redundant array includes B rows of the redundant array blocks, each redundant array block includes P storage pages, and the storage pages are used to store user data pages; the N physical storage platforms are connected to W word lines and have B*P row storage pages, and each word line is connected to (B*P) / W of the row storage pages. The N, B, P, and W are positive integers and N>2; The data verification method includes: Setting a redundant array tag group with P different redundant array tags. The first to the Bth rows of the redundant array blocks respectively correspond to the first to the Bth redundant array tag groups. The P row storage pages in each row of the redundant array blocks respectively correspond to the P redundant array tags in each redundant array tag group; Taking the redundant array block in the first row of the redundant array blocks that is located in the Nth physical storage platform as the first parity check data storage block for storing P first parity check data pages. Wherein, each first parity check data page corresponds to one redundant array tag in the first redundant array tag group and is used to verify the user data pages in the row storage pages corresponding to the corresponding redundant array tag.

2. The data verification method of the memory according to claim 1, characterized in that, The data verification method further includes: Taking the redundant array block in the Bth row of the redundant array blocks that is located in the Nth physical storage platform as the second parity check data storage block for storing P second parity check data pages. Wherein, each second parity check data page is used to verify the user data pages in the row storage pages corresponding to the same redundant array tag in the second to the Bth redundant array tag groups.

3. The data verification method of the memory according to claim 1, wherein The memory further includes SRAM. The data verification method further includes: Performing an exclusive OR operation on the user data pages in the row storage pages corresponding to each redundant array tag in the first redundant array tag group and that are located in the first N-1 physical storage platforms to obtain one first parity check data page, and caching the obtained P first parity check data pages in the SRAM; Copying the P first parity check data pages to the first parity check data storage block for storage and initializing the SRAM.

4. The data verification method of the memory according to claim 2, wherein The memory further includes SRAM. The data verification method further includes: Caching the user data pages in the row storage pages corresponding to the same redundant array tag in the second to the B-1th redundant array tag groups in the SRAM, and performing an exclusive OR operation each time one user data page is cached to obtain P second parity check data pages; In the row storage pages corresponding to each redundant array label in the B-th redundant array label group, the user data pages located in the first N - 1 physical storage platforms are cached in the SRAM, and an exclusive OR operation is performed once for each cached user data page to update P second parity check data pages; Copy the P second parity check data pages to the second parity check data storage block for storage.

5. The data verification method of the memory according to claim 1, characterized in that The first row of the redundant array block is located at the bottom of the memory, and the B-th row of the redundant array block is located at the top of the memory; among the P row storage pages in the first row of the redundant array block, the word lines connected to the first (B * P) / W row storage pages are located at the bottom of the memory, and among the P row storage pages in the B-th row of the redundant array block, the word lines connected to the last (B * P) / W row storage pages are located at the top of the memory.

6. The data verification method of the memory according to claim 3, wherein The data verification method further includes: When the SRAM is powered off, copy the P first parity check data pages cached in the SRAM to the memory for storage; When the SRAM is powered on again, copy the P first parity check data pages copied to the memory back to the SRAM for storage.

7. The data verification method of the memory according to claim 1, wherein The data verification method further includes: Use one or more redundant array blocks located in the N-th physical storage platform in the redundant array blocks of the second row to the (B - 1)-th row as the third parity check data storage block for storing third parity check data.

8. A data verification device for a memory, characterized in that The memory includes N juxtaposed physical storage platforms, each physical storage platform includes B storage blocks, so that the N physical storage platforms form an independent disk redundant array with N * B redundant array blocks. The independent disk redundant array includes B rows of redundant array blocks, each redundant array block includes P storage pages, and the storage pages are used to store user data pages; the N physical storage platforms are connected to W word lines and have B * P row storage pages, and each word line is connected to (B * P) / W row storage pages. N, B, P, and W are positive integers and N > 2; The data verification device includes: A setting module for setting a redundant array label group with P different redundant array labels. The first row to the B-th row of the redundant array blocks respectively correspond to the first to the B-th redundant array label groups, and the P row storage pages in each row of the redundant array block respectively correspond to the P redundant array labels in each redundant array label group; A first setting module for using the redundant array block located in the N-th physical storage platform in the first row of the redundant array block as the first parity check data storage block for storing P first parity check data pages. Each first parity check data page corresponds to one redundant array label in the first redundant array label group and is used to verify the user data pages in the row storage pages corresponding to the corresponding redundant array label.

9. A computer device, characterized in that, including a memory and a processor; wherein, the memory is used to store user data; the processor is used to execute a computer program to implement the steps in the data verification method according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that, for storing a computer program, wherein the computer program, when executed by the processor, implements the data verification method according to any one of claims 1 to 7.

Images