Processor error positioning method, device, equipment and storage medium

Abstract

The application provides a processor error positioning method, device, equipment and storage medium, the method comprises the following steps: when a terminal to be tested is running in a specified running stage, detecting whether the terminal to be tested has error information about the processor; if the terminal to be tested has the error information about the processor in the specified running stage, controlling the terminal to stay in the current running stage and issuing a prompt information. The application divides the processor error into stages in advance, detects the error information when the terminal to be tested is running in the specified stage, stays in the current running stage if there is error information about the processor, and then enables the staff to quickly understand in which stage the error is generated, thereby providing reference information for accurately evaluating the influence of the MCA error of the processor on the stability of the system.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a processor error location method, apparatus, device, and storage medium. Background Technology

[0002] During the research and development process of electronic products, reboot tests are often required to assess the product's safety, reliability, and stability. Similarly, during the manufacturing process, aging tests (which also require reboot tests) are run in the factory to ensure product quality. Whether in the reboot tests during R&D or the aging tests during factory production, scenarios may arise where the CPU's (Central Processing Unit) MCA (Machine Check Architecture, a self-check of computer hardware that reports errors or anomalies) reports an error.

[0003] For example, a typical reboot test process is as follows: the CPU boots from the BIOS (Basic Input Output System) to load the OS (operating system) and complete the boot process, then runs aging applications under the system, and finally the CPU restarts for the next round of testing.

[0004] MCA errors can occur at any point during the entire process described above, and the impact of MCA errors occurring at different times on system security, reliability, and stability varies. Current solutions cannot precisely pinpoint the stage at which CPU MCA errors occur; therefore, they cannot accurately assess the impact of MCA errors on system security, reliability, and stability. Summary of the Invention

[0005] The purpose of this application is to provide a processor error localization method, apparatus, device, and storage medium, which can more accurately determine which stage the error occurred in the MCA (Multi-Channel Error Detection) and is beneficial for accurately assessing the impact of the MCA error on system stability.

[0006] The first aspect of this application provides a processor error location method, comprising: when a terminal under test is running in a specified running phase, detecting whether the terminal under test has error information about the processor; if the terminal under test has the error information about the processor in the specified running phase, controlling the terminal to stay in the current running phase and issuing a prompt message.

[0007] In one embodiment, the designated operation phase includes one or more of the following: BIOS startup phase, operating system startup phase, and application testing phase.

[0008] In one embodiment, the designated operating phase includes a BIOS startup phase; the step of controlling the terminal under test to remain in the current operating phase and issuing a prompt message if the terminal under test has the error information about the processor in the designated operating phase includes: if the terminal under test has the error information about the processor in the BIOS startup phase, controlling the terminal under test to crash in the BIOS startup phase and displaying BIOS interface information on the interactive interface.

[0009] In one embodiment, the specified operating phase includes: a BIOS startup phase; if the terminal under test has the error information about the processor in the specified operating phase, controlling the terminal to stay in the current operating phase and issuing a prompt message includes: if the terminal under test has the error information about the processor in the BIOS startup phase, controlling the terminal under test to enable BIOS debug mode and outputting the error information to the serial port for storage.

[0010] In one embodiment, the specified running stage includes an operating system startup stage; the method further includes: if the terminal under test does not have the error information about the processor during the BIOS startup stage, after the operating system startup stage is completed, detecting whether the terminal under test has the error information about the processor; if the terminal under test has the error information after the operating system startup stage is completed, controlling the terminal under test to remain in the operating system startup stage completion stage, and displaying operating system interface information on the interactive interface.

[0011] In one embodiment, the specified running phase includes an application testing phase; the method further includes: if, after the operating system startup phase is completed, the terminal under test does not have any error information regarding the processor, during the application testing phase, periodically detecting whether the terminal under test has any error information regarding the processor; if, during the application testing phase, the terminal under test has error information regarding the processor, controlling the terminal under test to stop running the current test application, and displaying the interface information of the current test application on the interactive interface.

[0012] In one embodiment, the method further includes: disabling the error reporting function of the processor of the terminal under test during the restart phase of the terminal under test; and after the restart phase is completed, detecting whether there is any error information about the processor in the terminal under test, and determining whether the error information occurred during the restart phase based on the detection result.

[0013] A second aspect of this application provides a processor error location device, comprising: an error detection module, configured to detect whether the terminal under test has error information about the processor when the terminal under test is running in a specified running stage; and an execution control module, configured to control the terminal to remain in the current running stage and issue a prompt message if the terminal under test has the error information about the processor in the specified running stage.

[0014] In one embodiment, the designated operation phase includes one or more of the following: BIOS startup phase, operating system startup phase, and application testing phase.

[0015] In one embodiment, the specified operating phase includes a BIOS startup phase; the execution control module is configured to: if the terminal under test has error information about the processor during the BIOS startup phase, control the terminal under test to crash during the BIOS startup phase, and display BIOS interface information on the interactive interface.

[0016] In one embodiment, the specified operating phase includes a BIOS startup phase; the execution control module is configured to: if the terminal under test has error information about the processor during the BIOS startup phase, control the terminal under test to enable BIOS debug mode and output the error information to a serial port for storage.

[0017] In one embodiment, the specified running stage includes: an operating system startup stage; the error detection module is further configured to: if the terminal under test does not have the error information about the processor during the BIOS startup stage, detect whether the terminal under test has the error information about the processor after the operating system startup stage is completed; the execution control module is further configured to: if the terminal under test has the error information after the operating system startup stage is completed, control the terminal under test to remain in the operating system startup stage completion stage, and display operating system interface information on the interactive interface.

[0018] In one embodiment, the specified running phase includes an application testing phase; the error detection module is further configured to: if, after the operating system startup phase is completed, the terminal under test does not have any error information regarding the processor, periodically detect whether the terminal under test has any error information regarding the processor during the application testing phase; the execution control module is further configured to, if, during the application testing phase, the terminal under test has any error information regarding the processor, control the terminal under test to stop running the current test application and display the interface information of the current test application on the interactive interface.

[0019] In one embodiment, the device further includes: an error blocking module, configured to block the error reporting function of the processor of the terminal under test during the restart phase of the terminal under test; and an error location module, configured to detect whether there is any error information about the processor in the terminal under test after the restart phase is completed, and determine whether the error information occurred during the restart phase based on the detection result.

[0020] A third aspect of this application provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the method of the first aspect of this application and any of its embodiments.

[0021] A fourth aspect of this application provides a non-transitory electronic device readable storage medium, comprising: a program, which, when run by an electronic device, causes the electronic device to execute the method of the first aspect of this application and any of its embodiments.

[0022] The processor error localization method, apparatus, device, and storage medium provided in this application pre-divide processor errors into stages. When the terminal under test is running in a specified stage, error information is detected. If there is an error related to the processor, the system stops at the current running stage, allowing staff to quickly understand which stage the error occurred in. This provides reference information for accurately assessing the impact of processor MCA errors on system stability. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of a system testing process according to an embodiment of this application;

[0026] Figure 3 This is a flowchart illustrating a processor error localization method according to an embodiment of this application;

[0027] Figure 4 This is a flowchart illustrating a processor error localization method according to an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of a processor error location device according to an embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. In the description of this application, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0030] To clearly describe the solution in this embodiment, the terms involved are defined as follows:

[0031] CPU: Central Processing Unit, is the core of a computer system for computation and control, and is the unit for executing software programs.

[0032] MCA: Machine Check Architecture, performs a self-check on computer hardware, and reports errors or anomalies when they occur; this is often referred to as an MCA error report.

[0033] BIOS: Basic Input Output System, is a set of programs embedded in a ROM chip on the computer's motherboard. It stores the computer's most important basic input and output programs, power-on self-test programs, and system startup programs.

[0034] like Figure 1 As shown, this embodiment provides an electronic device 1, including: at least one processor 11 and a memory 12. Figure 1 Taking a processor as an example, processor 11 and memory 12 are connected via bus 10. Memory 12 stores instructions that can be executed by processor 11. The instructions are executed by processor 11 to enable electronic device 1 to perform all or part of the process of the method in the following embodiment to more accurately locate the stage at which the processor's MCA error occurs.

[0035] In one embodiment, the electronic device 1 may be a mobile phone, tablet computer, laptop computer, desktop computer, or a large computing system composed of multiple computers.

[0036] like Figure 2 The diagram shown is a scenario example of a system testing process provided in this application embodiment. In actual scenarios, the process of running an aging test on the operating system of electronic device 1 is generally as follows: the processor CPU starts from the BIOS, loads the OS and completes the startup, then runs the application under the system, and finally the CPU restarts to carry out the next round of testing.

[0037] MCA errors may occur throughout the entire process, and the impact of MCA errors occurring at different stages on system security, reliability, and stability varies. This application's embodiments divide the aforementioned error-prone process into four stages:

[0038] 1) During the BIOS startup phase, the MCA status register is checked, and if an error occurs, it will be reported.

[0039] 2) OS startup phase (i.e., operating system startup phase): After the BIOS finishes booting, it loads the OS. After the OS finishes booting, it first checks the MCA status register. If an error occurs, it reports the error.

[0040] 3) During the application testing phase, when the system is running applications, such as stress tests, the MCA status register is checked periodically. If there is an error, it is reported and the current application is stopped. If no error is reported after the test is completed, a reboot operation is performed.

[0041] 4) During the restart phase, when the operating system restarts, the CPU state will be restored and then the system will start up again. During this process, a MAC error may occur momentarily during the CPU restart.

[0042] In real-world scenarios, the errors in stages 1) and 2) mentioned above occur during the BIOS startup, system loading, and boot phases, and have a relatively small impact on system stability.

[0043] In phase 3), if errors occur during application testing on the system, it will have a serious impact on the stability of the system.

[0044] In stage 4), the error generated during the instant of CPU restart has no impact on system operation, and therefore has a very minor impact on system stability.

[0045] Therefore, during aging tests or reboot tests, if the system reports an MCA error, pinpointing the stage at which the error occurred is crucial for assessing system stability.

[0046] Current solutions can only detect CPU MCA errors, but cannot pinpoint the exact stage at which they occurred. Furthermore, the stage at which a CPU MCA error occurs has different impacts on system stability; therefore, it is impossible to more accurately assess the impact of MCA errors on system security, reliability, and stability.

[0047] Please refer to Figure 3 This is a processor error location method according to an embodiment of this application. The method can be performed by... Figure 1 The electronic device 1 shown is used to perform this action, and it can be applied to the above-mentioned... Figure 2 In the system testing process scenario, this method aims to quickly pinpoint the stage at which a processor error occurs, providing reference information for accurately assessing the impact of the processor's MCA (Multi-Channel Accident) error on system stability. The method includes the following steps:

[0048] Step 301: When the terminal under test is running in the specified running phase, check whether there are any error messages about the processor in the terminal under test.

[0049] In this step, the terminal under test can be an electronic device such as a mobile phone or computer, and the error message can be the MAC error mentioned above. Figure 2 For example, during the testing process of the terminal under test, MAC errors often occur in the CPU of the terminal under test. Such errors can affect the stability and security of the system. However, the severity of the impact on the system varies depending on the stage at which the MAC error occurs. Therefore, the test process can be divided into specified running stages in advance based on the severity of the impact of the MAC error on the system.

[0050] In one embodiment, there can be multiple specified operating phases, such as, but not limited to, the BIOS startup phase, the operating system startup phase, and the application testing phase. When the terminal under test is running in a specified operating phase, it is possible to detect whether there are any error messages about the processor by checking the MCA status register.

[0051] Step 302: If the terminal under test has error messages about the processor during the specified running stage, the control terminal stays at the current running stage and issues a prompt message.

[0052] In this step, if the terminal under test has a MAC error in the MCA status register during a specified running phase, such as during the BIOS startup phase, it means that the error message was generated during the BIOS startup phase. In order to let the staff intuitively understand that the error was generated during this phase, the terminal under test can be directly controlled to stay in the current running phase and a prompt message can be issued.

[0053] In one embodiment, the method may further include:

[0054] Step 303: During the restart phase of the terminal under test, disable the error reporting function of the terminal under test processor.

[0055] In this step, the error reporting function can be disabled by executing the command `wrmsr -a 0x17b 0x0`. This command disables MCA error reporting during CPU restart. After the CPU restart is complete, the `msr 0x17b` command will automatically revert to its original value, thus automatically enabling MCA error reporting. In other words, it disables MCA error reporting during the instant of CPU restart.

[0056] Step 304: After completing the restart phase, check whether there are any error messages about the processor in the terminal under test, and determine whether the error messages occurred during the restart phase based on the detection results.

[0057] In this step, after running the reboot test, the MAC status register is checked to see if there are any MAC error messages on the terminal under test. If a MAC error occurs after rebooting without disabling error reporting, and no MAC error occurs after running the reboot test with the error reporting function disabled by executing the command `wrmsr -a 0x17b 0x0`, it indicates that the MCA error was caused at the moment of system restart, and the MAC error message has a minor impact on system stability.

[0058] If a MAC error occurs after rebooting without disabling error reporting, and the MAC error persists even after completing the reboot test by disabling error reporting using the command `wrmsr -a 0x17b 0x0`, then the MAC error was not generated during the reboot phase. It is likely an MCA error generated in another phase. Steps 301-302 can be used to determine which specific phase the MAC error originated from.

[0059] In one embodiment, when there are multiple specified running stages, if an unknown MAC error occurs during system testing, the terminal under test can be run separately for each specified running stage. Then, the MAC status register can be checked in the corresponding running stage. The stage in which the pause and prompt information occur indicates that the MAC error occurred in that stage, thereby achieving accurate location of the error information.

[0060] In one embodiment, based on the needs of the actual scenario, the terminal under test can be executed in a certain order for each specified running stage to avoid repetitive operations, for example... Figure 2 In system testing scenarios, the terminal under test can first run the BIOS boot stage, then the operating system boot stage, and then the application testing stage. During the operation of each stage, the corresponding MAC status register is checked, so that when a MAC error occurs, the test will pause and display a prompt.

[0061] The aforementioned processor error localization method pre-divides processor errors into stages. When the terminal under test is running in a specified stage, it detects error information. If there is an error related to the processor, it stops at the current running stage, allowing staff to quickly understand at which stage the error occurred. This provides reference information for accurately assessing the impact of processor MCA errors on system stability.

[0062] Please refer to Figure 4This is a processor error location method according to an embodiment of this application. The method can be performed by... Figure 1 The electronic device 1 shown is used to perform this action, and it can be applied to the above-mentioned... Figure 2 In the system testing process scenario, this method aims to quickly pinpoint the stage at which a processor error occurs, providing reference information for accurately assessing the impact of the processor's MCA (Multi-Channel Accident) error on system stability. The method includes the following steps:

[0063] Step 401: When the terminal under test is running in the BIOS startup phase, check if there are any error messages about the processor. If yes, proceed to step 402; otherwise, proceed to step 403.

[0064] In this step, BIOS software can be written to detect the MCA status register during the BIOS startup process to determine if a MAC error exists.

[0065] Step 402: Control the terminal under test to crash during the BIOS startup phase and display the BIOS interface information on the interactive interface.

[0066] In this step, if the terminal under test has error messages about the processor during the BIOS startup phase, the error will be reported and the terminal under test will be controlled to crash into the BIOS startup process. The BIOS interface information will be displayed on the interactive interface to help the staff find the error location more intuitively and in a timely manner.

[0067] In one embodiment, if the terminal under test (DUT) has error messages about the processor during the BIOS startup phase, the DUT is controlled to enable BIOS debug mode, and the error messages are output to the serial port for storage. That is, if the error is generated during the BIOS phase, the DUT can also be controlled to enable BIOS debug mode, and the MCA error messages can be output to the serial port for storage, making it easier for users to view and increasing the diversity of error location information prompts.

[0068] Step 403: After the operating system startup phase is complete, check if there are any error messages about the processor on the terminal under test. If yes, proceed to step 404; otherwise, proceed to step 405.

[0069] In this step, if the terminal under test does not have any error information about the processor during the BIOS startup phase, the OS will be automatically loaded after the BIOS startup is complete. After the OS has finished booting, the written script can be used to first check the MCA error status after the power-on is completed.

[0070] Step 404: Control the terminal under test to remain in the operating system startup completion stage and display the operating system interface information on the interactive interface.

[0071] In this step, if the terminal under test has an error message after the operating system startup phase is completed, the error is reported and the aging test process is not executed. Instead, the terminal under test is controlled to stay at the operating system startup completion phase and the operating system interface information is displayed on the interactive interface so that the user can view the error location in time and accurately assess the impact of the error on the system.

[0072] Step 405: During the application testing phase, periodically check if the terminal under test has any error messages related to the processor. If yes, proceed to step 406; otherwise, proceed to step 407.

[0073] In this step, if the terminal under test does not have any error messages about the processor after the operating system startup phase is completed, the application testing phase can be entered according to the process. For example, a script written in the system can periodically check the MCA status register during the aging test to determine if there are any MAC errors.

[0074] Step 406: Control the terminal under test to stop running the current test application and display the interface information of the current test application on the interactive interface.

[0075] In this step, if the terminal under test has error messages about the processor during the application testing phase, the terminal under test can be controlled to stop running the current test application and the interface information of the current test application can be displayed on the interactive interface to prompt the user that an error has occurred. The user can intuitively determine that the error occurred during system operation.

[0076] Step 407: During the restart phase of the terminal under test, disable the error reporting function of the terminal under test's processor.

[0077] In this step, if the terminal under test does not have any processor-related error messages during the application testing phase in step 405, meaning that no MAC errors are reported after all application tests have been completed, the following functions can be performed using a script before executing reboot:

[0078] First, check if there is an MCA error. If an error is detected, stay at the system running interface. If no error is detected, proceed to the next step.

[0079] b. Execute the instruction `wrmsr -a 0x17b 0x0`. This instruction disables MCA error reporting during CPU restart. After the CPU restart is complete, `msr 0x17b` will automatically revert to its original value, thus automatically enabling MCA error reporting. In other words, it disables MCA error reporting during the instant of CPU restart.

[0080] Step 408: After completing the restart phase, check whether there are any error messages about the processor in the terminal under test, and determine whether the error messages occurred during the restart phase based on the detection results.

[0081] In this step, if no error is reported after running the reboot test using the above-mentioned method of disabling error reporting, it means that the MCA error was caused at the moment of system restart. This MAC error has a minor impact on system stability and can be given as a reminder for user reference.

[0082] In one embodiment, if a MAC error occurs after rebooting without disabling error reporting, and the MAC error persists even after completing the reboot test by disabling error reporting using the command `wrmsr -a 0x17b 0x0`, then the MAC error is determined not to have originated during the reboot phase. It may be an MCA error originating from another phase. The specific phase from which the MAC error originated can be determined according to steps 401-405.

[0083] The aforementioned processor error localization method divides the system of the terminal under test into four stages from power-on to restart. By modifying the BIOS and writing executable scripts under the system, it can determine at which stage the CPU MCA error occurred, thereby providing accurate reference data for a more reasonable and effective assessment of the impact on system stability.

[0084] Please refer to Figure 5 This is a processor error location device 500 according to an embodiment of this application. The device can be applied to... Figure 1 The electronic device 1 shown can be applied to the above-mentioned Figure 2 In the system testing process scenario, this device aims to quickly locate the stage at which a processor error occurs, providing reference information for accurately assessing the impact of the processor's MCA error on system stability. The device includes an error detection module 501 and an execution control module 502, and the relationship between these modules is as follows:

[0085] The error detection module 501 is used to detect whether there are error messages about the processor in the terminal under test when the terminal under test is running in a specified running stage.

[0086] The execution control module 502 is used to control the terminal under test to remain in the current running stage and issue a prompt message if the terminal under test has an error message about the processor during a specified running stage.

[0087] In one embodiment, the specified operation phase includes one or more of the following: BIOS startup phase, operating system startup phase, and application testing phase.

[0088] In one embodiment, the specified operating phase includes the BIOS startup phase. The execution control module 502 is configured to: if the terminal under test has error information about the processor during the BIOS startup phase, control the terminal under test to crash during the BIOS startup phase, and display the BIOS interface information on the interactive interface.

[0089] In one embodiment, the specified operating phase includes: the BIOS startup phase. The execution control module 502 is configured to: if the terminal under test has error information about the processor during the BIOS startup phase, control the terminal under test to enable the BIOS debug mode, and output the error information to the serial port for storage.

[0090] In one embodiment, the specified operating phase includes: the operating system startup phase. The error detection module 501 is further configured to: if the terminal under test does not have any error information regarding the processor during the BIOS startup phase, detect whether there is any error information regarding the processor after the operating system startup phase is completed. The execution control module 502 is further configured to: if there is error information in the terminal under test after the operating system startup phase is completed, control the terminal under test to remain in the operating system startup phase completion phase and display operating system interface information on the interactive interface.

[0091] In one embodiment, the specified operating phase includes an application testing phase. The error detection module 501 is further configured to: if, after the operating system startup phase is completed, the terminal under test does not have any error information regarding the processor, periodically detect whether the terminal under test has any error information regarding the processor during the application testing phase. The execution control module 502 is further configured to: if, during the application testing phase, the terminal under test has error information regarding the processor, control the terminal under test to stop running the current test application and display the interface information of the current test application on the interactive interface.

[0092] In one embodiment, the system further includes: an error masking module 503, used to mask the error reporting function of the processor of the terminal under test during the restart phase of the terminal under test; and an error location module 504, used to detect whether there is any error information about the processor in the terminal under test after the restart phase is completed, and to determine whether the error information occurred during the restart phase based on the detection result.

[0093] For a detailed description of the processor error location device 500 described above, please refer to the description of the relevant method steps in the above embodiments.

[0094] This invention also provides a non-transitory electronic device readable storage medium, comprising: a program, which, when run on the electronic device, enables the electronic device to execute all or part of the processes of the methods described in the above embodiments. The storage medium may be a disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc. The storage medium may also include combinations of the above types of memory.

[0095] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for locating processor errors, characterized in that, include: When the terminal under test is running in a specified operating phase, check whether there are any error messages about the processor in the terminal under test; If the terminal under test has error information about the processor during the specified running stage, the terminal is controlled to stay in the current running stage and a prompt message is issued; the prompt message includes displaying the interface information of the current running stage on the interactive interface; During the restart phase of the terminal under test, a preset instruction is executed to write a specific value to a specific register to disable the error reporting function of the terminal under test processor; the specific register is automatically restored to its original value after the restart phase is completed, so as to enable the error reporting function of the terminal under test processor. After the restart phase is completed, it is detected whether the terminal under test currently has any error information about the processor, and based on the detection result, it is determined whether the error information occurred during the restart phase; Specifically, if the error message appears after the restart phase without disabling the error reporting function, and does not appear after the restart phase is completed with the error reporting function disabled, it indicates that the error message occurred during the restart phase.

2. The processor error location method according to claim 1, characterized in that, The specified operating phase includes one or more of the following: BIOS startup phase, operating system startup phase, and application testing phase.

3. The processor error location method according to claim 1, characterized in that, The specified operating phase includes: the BIOS startup phase; if the terminal under test has error information regarding the processor during the specified operating phase, the terminal is controlled to remain in the current operating phase, and a prompt message is issued, including: If the terminal under test has error information about the processor during the BIOS startup phase, the terminal under test is controlled to crash during the BIOS startup phase, and BIOS interface information is displayed on the interactive interface.

4. The processor error location method according to claim 1, characterized in that, The specified operating phase includes: the BIOS startup phase; if the terminal under test has error information regarding the processor during the specified operating phase, the terminal is controlled to remain in the current operating phase, and a prompt message is issued, including: If the terminal under test has error information about the processor during the BIOS startup phase, the terminal under test is controlled to enable BIOS debug mode, and the error information is output to the serial port for storage.

5. The processor error localization method according to claim 3 or 4, characterized in that, The specified operational phase includes: the operating system startup phase; the method further includes: If the terminal under test does not have the error message about the processor during the BIOS startup phase, after the operating system startup phase is completed, it is checked whether the terminal under test has the error message about the processor. If the terminal under test has the error message after the operating system startup phase is completed, the terminal under test is controlled to stay in the operating system startup phase completion phase, and the operating system interface information is displayed on the interactive interface.

6. The processor error location method according to claim 5, characterized in that, The specified operational phase includes: an application testing phase; the method further includes: If, after the operating system startup phase is completed, the terminal under test does not have any error messages regarding the processor, during the application testing phase, the terminal under test is periodically checked for any error messages regarding the processor. If, during the application testing phase, the terminal under test contains error information regarding the processor, the terminal under test is controlled to stop running the current test application, and the interface information of the current test application is displayed on the interactive interface.

7. A processor error location device, characterized in that, include: The error detection module is used to detect whether there are any error messages about the processor in the terminal under test when the terminal under test is running in a specified running stage. The execution control module is used to control the terminal under test to remain in the current running stage and issue a prompt message if the terminal under test has the error information about the processor in the specified running stage; the prompt message includes displaying the interface information of the current running stage on the interactive interface; An error reporting masking module is used to execute a preset instruction to write a specific value to a specific register during the restart phase of the terminal under test to mask the error reporting function of the terminal under test processor; the specific register is automatically restored to its original value after the restart phase is completed, so as to enable the error reporting function of the terminal under test processor. The error location module is used to detect whether the terminal under test currently has error information about the processor after the restart phase is completed, and to determine whether the error information occurred during the restart phase based on the detection result. Specifically, if the error message appears after the restart phase without disabling the error reporting function, and does not appear after the restart phase is completed with the error reporting function disabled, it indicates that the error message occurred during the restart phase.

8. The processor error location device according to claim 7, characterized in that, The specified operating phase includes: the BIOS startup phase; the execution control module is used to: if the terminal under test has the error information about the processor during the BIOS startup phase, control the terminal under test to crash during the BIOS startup phase, and display the BIOS interface information on the interactive interface.

9. The processor error location device according to claim 7, characterized in that, The specified operating phase includes: the BIOS startup phase; the execution control module is used to: if the terminal under test has error information about the processor during the BIOS startup phase, control the terminal under test to enable the BIOS debug mode, and output the error information to the serial port for storage.

10. The processor error location device according to claim 8 or 9, characterized in that, The specified running phase includes: the operating system startup phase; the error detection module is further configured to: if the terminal under test does not have the error information about the processor during the BIOS startup phase, detect whether the terminal under test has the error information about the processor after the operating system startup phase is completed; the execution control module is further configured to: if the terminal under test has the error information after the operating system startup phase is completed, control the terminal under test to stay in the operating system startup phase completion phase and display operating system interface information on the interactive interface.

11. The processor error location device according to claim 10, characterized in that, The specified running phase includes: an application testing phase; the error detection module is further configured to: if, after the operating system startup phase is completed, the terminal under test does not have any error information regarding the processor, periodically detect whether the terminal under test has any error information regarding the processor during the application testing phase; the execution control module is further configured to, if, during the application testing phase, the terminal under test has any error information regarding the processor, control the terminal under test to stop running the current test application and display the interface information of the current test application on the interactive interface.

12. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the method as described in any one of claims 1 to 6.

13. A non-transitory electronic device readable storage medium, characterized in that, Includes: a program, when executed by an electronic device, causing the electronic device to perform the method of any one of claims 1 to 6.

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