Data Transmission Processing Method and Related Devices in a Chip System

Abstract

An embodiment of the present application provides a data transmission processing method and related device in a chip system. The method includes: a first sub-chip receives a first data packet; wherein, the first data packet includes an identifier of a destination sub-chip; the first sub-chip and the destination sub-chip are sub-chips included in the chip system, and multiple sub-chips in the chip system are arranged in a matrix form, and each sub-chip in the multiple sub-chips is connected to adjacent surrounding sub-chips; the first sub-chip sends the data in the first data packet to the destination sub-chip based on a direction coordinate system according to the principle of consuming less bandwidth, and the principle of consuming less bandwidth is the principle of delivering the data to the destination sub-chip with less transmission bandwidth; the direction coordinate system is constructed with the first sub-chip as the center. The present application can achieve efficient data transmission between sub-chips in the chip system and improve the processing performance of the chip system.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a data transmission processing method and related devices in a chip system. Background Art

[0002] A chip system may include multiple sub-chips, each of which has the function of independently processing data. The multiple sub-chips are connected in a certain topology to achieve mutual communication. Moreover, the multiple sub-chips can cooperate to process a single large computing task in a model parallel manner to improve the processing efficiency of the task. During the process of cooperative task processing, data needs to be frequently exchanged and transmitted between the multiple sub-chips, and the efficiency of this data transmission affects the processing performance of the entire chip system. Summary of the Invention

[0003] Embodiments of the present application disclose a data transmission processing method and related devices in a chip system, which can achieve efficient data transmission between sub-chips in the chip system and improve the processing performance of the chip system.

[0004] In a first aspect, the present application provides a data transmission processing method in a chip system, and the method includes:

[0005] A first sub-chip receives a first data packet; wherein, the foregoing first data packet includes an identifier of a destination sub-chip; the foregoing first sub-chip and the foregoing destination sub-chip are sub-chips included in the chip system, and the multiple sub-chips in the foregoing chip system are arranged in a matrix form, and each of the multiple sub-chips is connected to adjacent surrounding sub-chips;

[0006] The foregoing first sub-chip sends the data in the foregoing first data packet to the foregoing destination sub-chip based on a direction coordinate system according to a principle of consuming less bandwidth, and the principle of consuming less bandwidth is a principle of delivering the foregoing data to the foregoing destination sub-chip with less transmission bandwidth;

[0007] The foregoing direction coordinate system is constructed with the foregoing first sub-chip as the center, and the foregoing direction coordinate system includes a first direction axis, a second direction axis, a third direction axis, and a fourth direction axis; the row where the foregoing first sub-chip is located is on at least one of the foregoing first direction axis and the foregoing second direction axis with opposite directions; the column where the foregoing first sub-chip is located is on at least one of the foregoing third direction axis and the foregoing fourth direction axis with opposite directions.

[0008] In the present application, by constructing the foregoing direction coordinate system with the sub-chip that currently needs to send data as the center in the chip system, and then, the sub-chip transmits the received data based on the direction coordinate system according to the principle of consuming less bandwidth, thereby the data transmission efficiency can be improved, and further the processing performance of the chip system can be improved.

[0009] In a possible implementation manner, the first sub-chip sends the data in the first data packet to the target sub-chip based on the direction coordinate system according to the principle of relatively small bandwidth consumption, including: when the target sub-chip is on the target direction axis, the first sub-chip sends the data along the direction of the target direction axis; the target direction axis is the first direction axis, the second direction axis, the third direction axis or the fourth direction axis.

[0010] In a possible implementation manner, the direction coordinate system further includes a first area, a second area, a third area and a fourth area; the first area is bounded by the first direction axis and the third direction axis, the second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the fourth direction axis;

[0011] The first data packet includes the identifiers of the first target sub-chip and the second target sub-chip; the first sub-chip sends the data in the first data packet to the target sub-chip based on the direction coordinate system according to the principle of relatively small bandwidth consumption, including:

[0012] When the first target sub-chip and the second target sub-chip are respectively in two adjacent areas among the first area, the second area, the third area and the fourth area, the first sub-chip sends a second data packet along the direction of the common direction axis; the second data packet includes the data, the identifiers of the first target sub-chip and the second target sub-chip; the common direction axis is the direction axis of the common boundary of the two adjacent areas.

[0013] In a possible implementation manner, the direction coordinate system further includes a first area, a second area, a third area and a fourth area; the first area is bounded by the first direction axis and the third direction axis, the second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the fourth direction axis;

[0014] The first data packet includes the identifiers of the first target sub-chip and the second target sub-chip; the first sub-chip sends the data in the first data packet to the target sub-chip based on the direction coordinate system according to the principle of relatively small bandwidth consumption, including:

[0015] When the foregoing first-purpose sub-chip is in the foregoing first region and the foregoing second-purpose sub-chip is in the foregoing third region, the foregoing first sub-chip sends a third data packet along one of the direction axes of the two boundary direction axes of the foregoing first region, and sends a fourth data packet along one of the direction axes of the two boundary direction axes of the foregoing third region; the foregoing third data packet includes the foregoing data and the identifier of the foregoing first-purpose sub-chip, and the foregoing fourth data packet includes the foregoing data and the identifier of the foregoing second-purpose sub-chip.

[0016] In a possible implementation manner, the foregoing direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the foregoing first region is bounded by the foregoing first direction axis and the foregoing third direction axis, the foregoing second region is bounded by the foregoing second direction axis and the foregoing third direction axis, the foregoing third region is bounded by the foregoing second direction axis and the foregoing fourth direction axis, and the foregoing fourth region is bounded by the foregoing first direction axis and the foregoing fourth direction axis;

[0017] The foregoing first data packet includes the identifiers of the first-purpose sub-chip and the second-purpose sub-chip; the foregoing first sub-chip sends the data in the foregoing first data packet to the foregoing purpose sub-chip based on the direction coordinate system according to the principle of consuming less bandwidth, including:

[0018] When the foregoing first-purpose sub-chip is in the target region and the foregoing second-purpose sub-chip is on the direction axis of the boundary of the foregoing target region, the foregoing first sub-chip sends a fifth data packet along the direction axis of the boundary of the foregoing target region, and the foregoing fifth data packet includes the foregoing data and the identifiers of the foregoing first-purpose sub-chip and the second-purpose sub-chip; the foregoing target region is the first region, the second region, the third region, or the fourth region.

[0019] In the above several possible implementation manners, the orientation of the purpose sub-chip relative to the foregoing first sub-chip is determined based on the above-constructed direction coordinate system, and the shortest transmission path from the first sub-chip to the purpose sub-chip is quickly determined based on the determined orientation, thereby realizing the rapid forwarding of data, saving the transmission bandwidth resources, and improving the transmission efficiency.

[0020] In a possible implementation manner, the foregoing first sub-chip includes a plurality of ports, each of the foregoing plurality of ports is connected to another sub-chip, and each of the foregoing ports corresponds to a transmission buffer for storing data to be sent; the foregoing method further includes: when there are at least two ports sending the foregoing data, the foregoing first sub-chip selects a first port to send the foregoing data; the foregoing first port is the port with the least amount of data to be sent in the transmission buffer among the foregoing at least two ports.

[0021] In this application, by sending data through a port with a smaller amount of data to be sent, the time for data queuing and waiting can be reduced, and the efficiency of data sending can be improved.

[0022] In a possible implementation manner, the identifier of the destination sub-chip included in the foregoing first data packet is multiple, and the identifier of the foregoing first sub-chip is included in the identifiers of the foregoing multiple destination sub-chips; the foregoing method further includes:

[0023] The foregoing first sub-chip stores the data in the foregoing first data packet;

[0024] The foregoing first sub-chip repackages the foregoing data to obtain a sixth data packet;

[0025] The foregoing first sub-chip sends the foregoing sixth data packet to the destination sub-chips other than the foregoing first sub-chip.

[0026] In this application, the data packet can carry the identifiers of multiple destination sub-chips. Compared with the existing situation where a data packet is sent to each destination, the number of data packets to be sent can be reduced, and the transmission bandwidth can be saved.

[0027] In a second aspect, this application provides a sub-chip, which is a first sub-chip. The foregoing first sub-chip includes:

[0028] A receiving unit, configured to receive a first data packet; wherein, the foregoing first data packet includes the identifier of a destination sub-chip; the foregoing first sub-chip and the foregoing destination sub-chip are sub-chips included in a chip system, and multiple sub-chips in the foregoing chip system are arranged in a matrix form, and each sub-chip in the foregoing multiple sub-chips is connected to the adjacent sub-chips around;

[0029] A sending unit, configured to send the data in the foregoing first data packet to the foregoing destination sub-chip based on a direction coordinate system according to the principle of consuming less bandwidth. The foregoing principle of consuming less bandwidth is the principle of delivering the foregoing data to the foregoing destination sub-chip with less transmission bandwidth;

[0030] The foregoing direction coordinate system is constructed with the foregoing first sub-chip as the center. The foregoing direction coordinate system includes a first direction axis, a second direction axis, a third direction axis, and a fourth direction axis; the row where the foregoing first sub-chip is located is on at least one of the direction axes of the foregoing first direction axis and the foregoing second direction axis with opposite directions; the column where the foregoing first sub-chip is located is on at least one of the direction axes of the foregoing third direction axis and the foregoing fourth direction axis with opposite directions.

[0031] In a possible implementation manner, the foregoing sending unit is specifically configured to:

[0032] When the foregoing destination sub-chip is on the target direction axis, transmit the foregoing data along the direction of the foregoing target direction axis; the foregoing target direction axis is the foregoing first direction axis, the foregoing second direction axis, the foregoing third direction axis, or the foregoing fourth direction axis.

[0033] In a possible implementation manner, the foregoing direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the foregoing first region is bounded by the foregoing first direction axis and the foregoing third direction axis, the foregoing second region is bounded by the foregoing second direction axis and the foregoing third direction axis, the foregoing third region is bounded by the foregoing second direction axis and the foregoing fourth direction axis, and the foregoing fourth region is bounded by the foregoing first direction axis and the foregoing fourth direction axis;

[0034] The foregoing first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip; the foregoing sending unit is specifically configured to:

[0035] When the foregoing first destination sub-chip and the second destination sub-chip are respectively in two adjacent regions among the foregoing first region, the second region, the third region, and the fourth region, transmit a second data packet along the direction of the common direction axis; the foregoing second data packet includes the foregoing data, the identifiers of the first destination sub-chip and the second destination sub-chip; the foregoing common direction axis is the direction axis of the common boundary of the foregoing two adjacent regions.

[0036] In a possible implementation manner, the foregoing direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the foregoing first region is bounded by the foregoing first direction axis and the foregoing third direction axis, the foregoing second region is bounded by the foregoing second direction axis and the foregoing third direction axis, the foregoing third region is bounded by the foregoing second direction axis and the foregoing fourth direction axis, and the foregoing fourth region is bounded by the foregoing first direction axis and the foregoing fourth direction axis;

[0037] The foregoing first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip; the foregoing sending unit is specifically configured to:

[0038] When the foregoing first destination sub-chip is in the foregoing first region and the foregoing second destination sub-chip is in the foregoing third region, transmit a third data packet along the direction of one of the direction axes of the two boundaries of the foregoing first region, and transmit a fourth data packet along the direction of one of the direction axes of the two boundaries of the foregoing third region; the foregoing third data packet includes the foregoing data and the identifier of the foregoing first destination sub-chip, and the foregoing fourth data packet includes the foregoing data and the identifier of the foregoing second destination sub-chip.

[0039] In a possible implementation manner, the foregoing direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the foregoing first region is bounded by the foregoing first direction axis and the foregoing third direction axis, the foregoing second region is bounded by the foregoing second direction axis and the foregoing third direction axis, the foregoing third region is bounded by the foregoing second direction axis and the foregoing fourth direction axis, and the foregoing fourth region is bounded by the foregoing first direction axis and the foregoing fourth direction axis;

[0040] The foregoing first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip; the foregoing sending unit is specifically configured to:

[0041] When the foregoing first destination sub-chip is in the target region and the foregoing second destination sub-chip is on the direction axis of the boundary of the foregoing target region, send a fifth data packet along the direction of the direction axis of the boundary of the foregoing target region, where the fifth data packet includes the foregoing data and the identifiers of the foregoing first destination sub-chip and the second destination sub-chip; the foregoing target region is the first region, the second region, the third region, or the fourth region.

[0042] In a possible implementation manner, the foregoing first sub-chip includes a plurality of ports, each port in the foregoing plurality of ports is connected to another sub-chip, and each port corresponds to a sending buffer for storing data to be sent;

[0043] The foregoing first sub-chip further includes a selection unit for:

[0044] When there are at least two ports sending the foregoing data, select the first port to send the foregoing data; the first port is the port with the least amount of data to be sent in the sending buffer among the foregoing at least two ports.

[0045] In a possible implementation manner, the identifiers of the destination sub-chips included in the foregoing first data packet are multiple, and the identifier of the foregoing first sub-chip is included in the identifiers of the foregoing multiple destination sub-chips; the foregoing first sub-chip further includes:

[0046] A storage unit for storing the data in the foregoing first data packet;

[0047] An encapsulation unit for re-encapsulating the foregoing data to obtain a sixth data packet;

[0048] The foregoing sending unit is further configured to send the foregoing sixth data packet to destination sub-chips other than the foregoing first sub-chip.

[0049] In a third aspect, the present application provides a sub-chip, which includes a processor, a memory, and a communication port; wherein, the aforementioned memory and communication port are coupled to the aforementioned processor, the aforementioned communication port is used for receiving and transmitting data, the aforementioned memory is used for storing computer programs, and the aforementioned processor is used for calling the aforementioned computer programs so that the aforementioned sub-chip executes the method according to any one of the first aspect; the aforementioned sub-chip is a sub-chip included in a chip system, and multiple sub-chips in the aforementioned chip system are arranged in a matrix, and each sub-chip in the aforementioned multiple sub-chips is connected to adjacent sub-chips around it.

[0050] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the aforementioned computer program is executed by a processor, the method according to any one of the first aspect is implemented.

[0051] In a fifth aspect, the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the method according to any one of the first aspect is implemented.

[0052] It can be understood that the above second aspect to fifth aspect are all applicable to execute the method provided in any one of the first aspect. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method, and will not be elaborated here. Description of the Drawings

[0053] The following will introduce the drawings required to be used in the embodiments of the present application.

[0054] Figure 1 Schematic diagram of the chip system provided by the present application;

[0055] Figure 2 Schematic diagram of the structure of the sub-chip provided by the present application;

[0056] Figures 3 to 6 Schematic diagram of the chip system provided by the present application;

[0057] Figure 7 Schematic diagram of the division of the sub-chip group provided by the present application;

[0058] Figure 8 Schematic diagram of the flow of the data transmission and processing method in the chip system provided by the present application;

[0059] Figure 9 Schematic diagram of the data packet structure provided by the present application;

[0060] Figure 10 Schematic diagram of the direction coordinate system provided by the present application;

[0061] Figure 11Schematic diagram of constructing a direction coordinate system based on sub - chips provided by this application;

[0062] Figure 12 Schematic diagram of the structure of the virtual device provided by this application;

[0063] Figure 13 Schematic diagram of the structure of the physical device provided by this application. Detailed implementation manners

[0064] The embodiments of this application will be described below with reference to the accompanying drawings.

[0065] Figure 1 Shown is a schematic diagram of the structure of a chip system provided by an embodiment of this application. The chip system 110 includes multiple sub - chips ( Figure 1 16 sub - chips are exemplarily shown), and the multiple sub - chips are connected according to a preset topological connection relationship. For example, Figure 1 the 16 sub - chips in it can be arranged in the form of a matrix, and then, each individual sub - chip is respectively connected to two, three or four surrounding sub - chips.

[0066] Each sub - chip has its own memory, Figure 1 the memories of some sub - chips are exemplarily drawn in it. The memory can be, for example, synchronous dynamic random access memory (SDRAM) or Double Data Rate SDRAM (DDRSDRAM), and DDRSDRAM can be abbreviated as DDR.

[0067] Each sub - chip in the chip system 100 has complete processing capabilities and can execute tasks independently. Of course, the multiple sub - chips in the chip system 100 can cooperate with each other to execute large - scale processing tasks.

[0068] Refer to Figure 2 , Figure 2 which exemplarily shows a schematic diagram of the structure of the sub - chips in the above - mentioned chip system 110. The structure of the sub - chip can be presented in the form of a network - on - chip (NoC). It can be seen that the sub - chip can include a processing module, a routing module, a static memory, a memory controller, and four ports (d0, d1, d2, and d3).

[0069] The above - mentioned processing module is the control unit (CU) in the sub - chip, which is responsible for the management of each processing process in the sub - chip.

[0070] The above-mentioned routing module is responsible for data synchronization within the sub-chip, data synchronization between sub-chips, data broadcasting, and data transmission. Among them, the routing module also includes a control unit, which is used to manage the routing process in the routing module. The routing module also includes a local buffer, which can be used to temporarily store data to be processed. The routing module also includes a forwarding-port mapper (FPM). The FPM can be a hardware module or a software module. A port forwarding mapping table is stored in the FPM. The port forwarding mapping table includes the mapping relationship between the destination sub-chip and the sending port, and can be used to map data packets to the corresponding ports for sending. A stream in table (SIT) and a stream out table (SOT) are stored in the routing module. The SIT and SOT are used for data transmission between sub-chips, which will be introduced in detail later and will not be elaborated here for the time being.

[0071] The above-mentioned static memory can be a static random-access memory (SRAM), etc., and is used to store data in the sub-chip.

[0072] The above-mentioned memory controller is connected to the memory corresponding to the sub-chip. The memory controller can be a DDR controller, etc.

[0073] The above four ports (d0, d1, d2, and d3) are the network interfaces of the sub-chip, and can realize data transmission between the above-mentioned sub-chips. The connection between the above-mentioned sub-chips is realized through these four ports. Optionally, the sub-chip can also include two such ports, such as Figure 1 sub-chip 0, sub-chip 3, sub-chip 12, and sub-chip 15 in Figure 1 Or, optionally, the sub-chip can also include three such ports, such as

[0074] The chip system provided by the embodiments of the present application is not limited to the above Figure 1 shown structure, and can also be other structures, such as referring to Figure 3 . Figure 3 Exemplarily shows a chip system 120. The chip system 120 also includes multiple sub-chips ( Figure 2 8 sub-chips are exemplarily shown in Figure 2 . The structure of the sub-chips in the chip system 120 can refer to the corresponding description in the above

[0075] In a possible implementation, for an extremely large task, more sub-chips are required to process together to improve the task processing efficiency. Then, the above chip system 110 or chip system 120 can be used as a subsystem of a chip, and a larger chip system can be composed of multiple such subsystems. Exemplarily, reference can be made to Figure 4 the shown chip system 130.

[0076] The chip system 130 may include multiple subsystems of the above chips. Figure 4 Taking 8 subsystems as an example, each of the multiple subsystems may be the above chip system 110 or chip system 120. Each subsystem can be regarded as a whole. Then, the multiple subsystems can be connected through a preset topological connection relationship. For example, they can be arranged and connected in the form of a cuboid, as shown in Figure 4 shown. To facilitate understanding of the connection manner of each subsystem in the chip system 130, exemplarily, taking the subsystem as the above chip system 110 as an example, the schematic connection structure diagram of each subsystem in the chip system 130 is shown, and reference can be made to Figure 5 .

[0077] In Figure 5 it can be seen that the chip system 130 includes 8 subsystems. Each of the 8 subsystems includes 16 sub-chips, and the 16 sub-chips can be arranged and connected in the form of a matrix. Between two adjacent subsystems, the connection between the two subsystems can be achieved by connecting any one sub-chip in one subsystem to any one sub-chip in the other subsystem. Figure 5 In the example, the sub-chips arranged at the corners of the matrix in each subsystem are used as the sub-chips connected to another subsystem. For example, in subsystem 0, the connection between subsystem 0 and subsystem 1 is established through sub-chip 3 in subsystem 0 and sub-chip 0 in subsystem 1. The connection between subsystem 0 and subsystem 2 is established through sub-chip 12 in subsystem 0 and sub-chip 0 in subsystem 2. The connection between subsystem 0 and subsystem 4 is established through sub-chip 0 in subsystem 0 and sub-chip 0 in subsystem 4.

[0078] In a possible implementation, a control bus may also be included between the above subsystems. For example, reference can be made to Figure 6The chip system 140 shown. The D-type bus shown in the chip system 140 is the control bus. The chip system 140 includes a central controller (the central controller can be a sub-chip or a control module in the chip system 140, etc.). The central controller can manage the task processing flow in the chip system 140. The control bus is connected to the central controller for each subsystem to receive control instructions from the central controller. In a specific implementation, each subsystem can be connected to the control line by a sub-chip. After receiving the control instruction, the sub-chip can forward it on behalf of the corresponding sub-chip within the same subsystem. Alternatively, each sub-chip in each subsystem is connected to the control line to directly receive control instructions. This application does not limit the specific connection of the controller.

[0079] In addition to the above chip system 140, the chip systems provided in the embodiments of this application (such as the above chip systems 110, 120, and 130, etc.) also include a central controller for managing the task processing flow of the entire chip system. Similarly, the central controller can be a sub-chip or a control module in the chip system, etc. The central controller can obtain the load conditions and resource usage conditions of all sub-chips in the chip system, etc., so as to allocate tasks to each sub-chip based on these conditions. Exemplarily, a task scheduler in the central controller can allocate tasks to these sub-chips based on information such as the load conditions and resource usage conditions of each sub-chip.

[0080] The above central controller can also be responsible for data scheduling in the chip system. Specifically, the central controller obtains the data transmission conditions of each sub-chip through the control bus. By analyzing these data transmission conditions, it can learn about the congestion conditions of each transmission path and / or the port congestion conditions of each sub-chip, so as to formulate a data transmission strategy based on these conditions and issue it to each sub-chip in the form of scheduling information. Each sub-chip sends data correspondingly based on the scheduling information issued by the controller, thereby reducing the probability of congestion and improving the data transmission efficiency.

[0081] In the chip system provided in the embodiments of this application, each sub-chip has the ability to independently process data. However, in the case of large data tasks, the processing efficiency of a single sub-chip is relatively low. To improve the task processing efficiency, multiple sub-chips included in the above chip system can be divided into multiple sub-chip groups, and each sub-chip group includes at least one sub-chip. In this way, data tasks can be processed with the sub-chip group as the processing unit, thereby improving the processing efficiency. To facilitate understanding of the chip group, refer to Figure 7 .

[0082] Figure 7Taking the above chip system 110 as an example, the 16 sub-chips in the chip system are divided into 9 sub-chip groups. For the specific division, please refer to Figure 7 the division shown. Each sub-chip group includes at least one sub-chip. In addition, multiple sub-chips in the same sub-chip group can be adjacent sub-chips, such as sub-chip groups 3, 4, 7, and 8. Or, multiple sub-chips in the same sub-chip group can be non-adjacent sub-chips, such as sub-chip group 2, which is composed of non-adjacent sub-chips 1 and 12.

[0083] The chip system provided by the embodiments of the present application can implement the processing of data tasks in a data parallel, model parallel, or model parallel plus data parallel manner. Among them:

[0084] Data parallelism means dividing the data to be processed into several data blocks, and distributing the several data blocks to different sub-chip groups respectively. Each chip group runs the same processing program to process the assigned data. For example, assume that the data to be processed is divided into 3 data blocks, and there are 3 sub-chip groups that can run the same processing program to process the data blocks. Then, the first data block among the 3 data blocks can be sent to the first sub-chip group among the 3 sub-chip groups for processing, the second data block among the 3 data blocks can be sent to the second sub-chip group among the 3 sub-chip groups for processing, and the third data block among the 3 data blocks can be sent to the third sub-chip group among the 3 sub-chip groups for processing.

[0085] Model parallelism means that multiple sub-chip groups jointly complete a data processing task, and each sub-chip group in the multiple sub-chip groups only executes part of the steps of the entire data processing task (the part of the steps can be one or more processing steps). For example, assume that a data processing task needs to go through 3 steps to complete the processing. Then, two sub-chip groups can be configured to jointly complete the task. Among them, the first sub-chip group completes the processing of the first 2 steps among the 3 steps, and the second sub-chip group obtains the processed data from the first sub-chip group to complete the processing of the 3rd step. Or, three sub-chip groups can be configured to jointly complete the task. Among them, the first sub-chip group completes the processing of the first step among the 3 steps, the second sub-chip group obtains the processed data from the first sub-chip group to complete the processing of the second step, and the third sub-chip group obtains the processed data from the second sub-chip group to complete the processing of the third step. That is, the steps completed by each chip group can be one or more, and can be specifically determined according to the load situation and resource usage situation of the chip group.

[0086] The method of model parallelism plus data parallelism combines the above two methods of data parallelism and model parallelism to process data. For example, if a data processing task needs to go through 3 steps to complete the processing, then three sub-chip groups can be configured to jointly complete this task. Among them, the first sub-chip group completes the processing of the first step among the 3 steps, the second sub-chip group obtains the processed data from the first sub-chip group to complete the processing of the second step, and the third sub-chip group obtains the processed data from the second sub-chip group to complete the processing of the third step. However, since the processing of the first step is relatively complex and takes a relatively long time to complete, in order to improve the processing efficiency, one or more additional sub-chip groups can be configured to jointly execute the processing task of the first step. For example, a fourth sub-chip group can be configured to jointly execute the processing task of the first step with the aforementioned first sub-chip group. Specifically, the data used for the first-step processing can be divided into two parts, one part is sent to the first sub-chip group for processing, and the other part is sent to the fourth sub-chip group for processing. Then, the data processed by the first sub-chip group and the fourth sub-chip group is sent together to the second sub-chip group for the second-step processing.

[0087] It should be noted that in the above method of model parallelism plus data parallelism, each processing step can adopt the data parallel processing method for processing, or some processing steps can adopt the data parallel processing method for processing, which can be specifically determined according to the specific implementation, and the present application does not limit this.

[0088] In the specific implementation, the data processing task can be assigned to each sub-chip group through the central controller of the chip system. To implement the processing of data tasks using the method of model parallelism or model parallelism plus data parallelism, data transmission is required between sub-chips. Data transmission will cause time delay and reduce the processing efficiency. In order to achieve efficient data transmission between sub-chips in the chip system and improve the processing performance of the chip system, the embodiments of the present application provide a data transmission processing method in the chip system.

[0089] See Figure 8 , the data transmission processing method provided by the embodiments of the present application includes but is not limited to the following steps:

[0090] S801. The first sub-chip receives the first data packet; wherein, the first data packet includes the identifier of the destination sub-chip; the first sub-chip and the destination sub-chip are sub-chips included in the chip system, and the multiple sub-chips included in the chip system are connected in a preset topology structure.

[0091] The chip system may be the chip system 110, chip system 120, chip system 130, or chip system 140 introduced above, etc. The first sub-chip may be any sub-chip in any of these chip systems. For the convenience of subsequent description, the chip system where the first sub-chip is located is referred to as the first chip system. The first sub-chip receives the above-mentioned first data packet from another sub-chip in the first chip system.

[0092] In a specific implementation, the first data packet may include one or more of information such as the type of the packet, the identifier of the task, the identifier of the data stream, the identifier of the destination sub-chip, the packet number, and the data. Among them:

[0093] The type of the packet is used to indicate the specific type of a packet. The type of the packet may include a data packet (DATA), a header packet (Header), or an unblock packet (UB), etc. The packet type of the above-mentioned first data packet is DATA.

[0094] The identifier of the task refers to the identifier of the data processing task corresponding to the packet. Multiple data processing tasks can be processed simultaneously in the chip system, and each data processing task has its corresponding identifier. The identifier of the task may be, for example, 1 or other identifier symbols, and the present application does not limit this. The above-mentioned first data packet is the carrier for the transmission of data in a data processing task between sub-chips. Therefore, the identifier of the task in the first data packet is the identifier of the certain data processing task.

[0095] The identifier of the data stream: Regarding the data stream, a sub-chip sends data to another sub-chip. These data are encapsulated into multiple data packets, these data packets are numbered in sequence and sent, and these continuously sent data packets form a data stream. In a possible implementation, each data packet may carry 1 kb of data. If the total size of the data to be transmitted is 64 kb, then these data can be split and encapsulated into 64 data packets for transmission, and these 64 data packets can form a data stream. Each data stream is configured with an identifier, and this identifier is the identifier of the data stream. The identifier of the data stream included in the above-mentioned first data packet is the identifier of the data stream where the first data packet is located.

[0096] The identifier of the destination sub-chip is used to indicate the destination of the packet. The identifier of the destination sub-chip in the above-mentioned first data packet can be the identifier of one or more destination sub-chips. If the data in the first data packet corresponds to one destination sub-chip, the identifier of the destination sub-chip in the first data packet is the identifier of the one destination sub-chip. If the data in the first data packet corresponds to multiple destination sub-chips, the identifier of the destination sub-chip in the first data packet is the identifier of the multiple destination sub-chips. For example, if there are two destination sub-chips in the data packet, namely sub-chip 0 and sub-chip 9, then the data packet includes the identifiers of sub-chip 0 and sub-chip 9.

[0097] The packet number refers to the sequence number of a packet in the data stream to which it belongs.

[0098] Data is the load (layout) in the packet, which is the actual content transmitted.

[0099] In a possible implementation, the first data packet may also carry sideband information, which may include one or more of the following: a task identifier, a data stream identifier, or an identifier of a destination sub-chip. These sideband information may not be encapsulated in the first data packet, but may be sent along with the first data packet. In a specific implementation, the information included in the first data packet is only available to the routing module of the sub-chip, and other modules such as ports in the sub-chip are not aware of it. Therefore, in order to facilitate the rapid forwarding of the first data packet, the first data packet may be configured to carry the above-mentioned sideband information. In order to facilitate understanding of the format of the first data packet and the format of the sideband information, it may be exemplified by referring to Figure 9 . Figure 9 The format of the first data packet and the corresponding sideband information shown are only examples. In a specific implementation, the first data packet may also include other information, and the sideband information may also include more information. This application does not impose any restrictions on this.

[0100] S802. The first sub-chip sends the data in the first data packet to the destination sub-chip based on the direction coordinate system and the principle of smaller bandwidth consumption. The principle of smaller bandwidth consumption is the principle of delivering the data to the destination sub-chip with smaller transmission bandwidth. The direction coordinate system is constructed with the first sub-chip as the center.

[0101] First, let me introduce the direction coordinate system built around the first sub-chip. Figure 10An exemplary schematic diagram of a direction coordinate system constructed centered on the first sub-chip is shown. It can be seen that this direction coordinate system includes four direction axes: the first direction axis, the second direction axis, the third direction axis, and the fourth direction axis. These four direction axes all diverge outward centered on the first sub-chip. Among them, the first direction axis and the second direction axis are collinear and opposite in direction; the third direction axis and the fourth direction axis are collinear and opposite in direction. This direction coordinate system also includes four regions: the first region, the second region, the third region, and the fourth region. Among them, the first region is bounded by the first direction axis and the third direction axis; the second region is bounded by the second direction axis and the third direction axis; the third region is bounded by the second direction axis and the fourth direction axis, and the fourth region is bounded by the first direction axis and the fourth direction axis.

[0102] In the chip system, the row where the first sub-chip is located is on at least one of the first direction axis and the second direction axis, and the column where the first sub-chip is located is on at least one of the third direction axis and the fourth direction axis. Exemplarily, it can be seen that Figure 11 . Suppose sub-chip 5 in the chip system is the first sub-chip. Then, a direction coordinate system is established centered on this sub-chip 5. In this direction coordinate system, the second row of this sub-chip 5 is on the first direction axis and the second direction axis, and the second column of this sub-chip 5 is on the third direction axis and the fourth direction axis. Then, sub-chip 2 and sub-chip 3 are in the first region of this direction coordinate system. Sub-chip 0 is in the second region of this direction coordinate system. Sub-chip 8 and sub-chip 12 are in the third region of this direction coordinate system. Sub-chip 10, sub-chip 11, sub-chip 14, and sub-chip 15 are in the fourth region of this direction coordinate system.

[0103] In a possible implementation manner, if in the above Figure 11 chip system, sub-chip 0 is the first sub-chip, then a direction coordinate system is established centered on this sub-chip 0. In this direction coordinate system, the first row of this sub-chip 0 is on the first direction axis, and the first column of this sub-chip 0 is on the fourth direction axis. Then, except for the sub-chips in the row and column where sub-chip 0 is located, the remaining sub-chips are all in the fourth region of this direction coordinate system.

[0104] In a possible implementation manner, the first sub-chip sending the data in the first data packet to the destination sub-chip based on the direction coordinate system according to the principle of consuming less bandwidth includes: when the destination sub-chip included in the first data packet is on the target direction axis, the first sub-chip sends the data in the first data packet along the direction of this target direction axis; this target direction axis is the first direction axis, the second direction axis, the third direction axis, or the fourth direction axis. For the sake of easy understanding, taking the above Figure 11 as an example for illustration.

[0105] In Figure 11 , assume that sub-chip 5 is the above-mentioned first sub-chip, and it receives a data packet. The identification of the destination sub-chip in the data packet indicates that the destination sub-chip is sub-chip 7. If the data packet only includes the identification of one destination sub-chip, then, since sub-chip 7 is located on the first direction axis, sub-chip 5 sends the data packet along the direction of the first direction axis. That is, sub-chip 5 first sends the data packet to sub-chip 6, and then sub-chip 6 forwards it to sub-chip 7. If the data packet includes the identifications of multiple destination sub-chips, and sub-chip 7, as one of the destination sub-chips, is located on the first direction axis. Therefore, sub-chip 5 copies the data in the data packet to newly generate a data packet and sends the new data packet along the direction of the first direction axis. That is, sub-chip 5 first sends the new data packet to sub-chip 6, and then sub-chip 6 forwards it to sub-chip 7. The newly generated data packet includes the identification of sub-chip 7.

[0106] In a possible implementation manner, the above-mentioned first data packet includes the identifications of the first destination sub-chip and the second destination sub-chip. The above-mentioned first sub-chip sends the data in the above-mentioned first data packet to the above-mentioned destination sub-chip based on the direction coordinate system with the principle of consuming less bandwidth, including: in the direction coordinate system established with the above-mentioned first sub-chip as the center, when the first destination sub-chip and the second destination sub-chip are respectively in two adjacent regions among the first region, the second region, the third region, and the fourth region of the coordinate system, the first sub-chip sends the second data packet along the direction of the common direction axis. The second data packet includes the data, the identifications of the first destination sub-chip and the second destination sub-chip. The common direction axis is the direction axis of the common boundary of the two adjacent regions. For the convenience of understanding, taking the above-mentioned Figure 11 as an example for illustration.

[0107] In Figure 11 , assume that sub-chip 5 is the above-mentioned first sub-chip, and it receives a data packet. The identifications of the destination sub-chips in the data packet indicate that the destination sub-chips are sub-chip 8 and sub-chip 14. Sub-chip 8 is located in the third region, and sub-chip 14 is located in the fourth region. These two regions are adjacent regions, and the common boundary is the fourth direction axis. Therefore, sub-chip 5 sends the data packet along the direction of the fourth direction axis. That is, sub-chip 5 first sends the data packet to sub-chip 9, and then sub-chip 9 makes further forwarding. Specifically, sub-chip 9 can also be regarded as the above-mentioned first sub-chip, a direction coordinate system is established with sub-chip 9 as the center, and then the data is forwarded based on the above-mentioned principle of consuming less bandwidth.

[0108] In a possible implementation manner, the above-mentioned first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip. The above-mentioned first sub-chip sends the data in the above-mentioned first data packet to the above-mentioned destination sub-chip based on the direction coordinate system according to the principle of consuming less bandwidth, including: in the direction coordinate system established with the above-mentioned first sub-chip as the center, when the first destination sub-chip is in the first area of the coordinate system and the second destination sub-chip is in the third area, the first sub-chip sends a third data packet along one of the direction axes of the two boundaries of the first area, and sends a fourth data packet along one of the direction axes of the two boundaries of the third area. The third data packet includes the data and the identifier of the first destination sub-chip. The fourth data packet includes the data and the identifier of the second destination sub-chip. For the convenience of understanding, in combination with the above Figure 11 as an example for illustration.

[0109] In Figure 11 , assume that sub-chip 5 is the above-mentioned first sub-chip, and it receives a data packet. The identifier of the destination sub-chip in the data packet indicates that the destination sub-chips are sub-chip 2 and sub-chip 12. Sub-chip 2 is located in the first area, and sub-chip 12 is located in the third area. Then, sub-chip 5 can regenerate two data packets based on the data in the received data packet: data packet A and data packet B. Data packet A includes the data and the identifier of sub-chip 2, and data packet B includes the data and the identifier of sub-chip 12. Then, send data packet A along the direction of the first direction axis or the third direction axis. For example, send data packet A along the direction of the first direction axis, that is, first send data packet A to sub-chip 6, and then sub-chip 6 forwards data packet A to sub-chip 2. In addition, sub-chip 5 sends data packet B along the direction of the second direction axis or the fourth direction axis. For example, send data packet B along the direction of the fourth direction axis, that is, first send data packet B to sub-chip 9, and then sub-chip 9 continues to forward it further.

[0110] In a possible implementation manner, the above-mentioned first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip. The above-mentioned first sub-chip sends the data in the above-mentioned first data packet to the above-mentioned destination sub-chip based on the direction coordinate system according to the principle of consuming less bandwidth, including: in the direction coordinate system established with the above-mentioned first sub-chip as the center, when the first destination sub-chip is in the second area of the coordinate system and the second destination sub-chip is in the fourth area, the first sub-chip sends a third data packet along one of the direction axes of the two boundaries of the second area, and sends a fourth data packet along one of the direction axes of the two boundaries of the fourth area. The third data packet includes the data and the identifier of the first destination sub-chip. The fourth data packet includes the data and the identifier of the second destination sub-chip. For the convenience of understanding, in combination with the above Figure 11 as an example for illustration.

[0111] In Figure 11 , assume that sub-chip 5 is the above-mentioned first sub-chip, and it receives a data packet. The identifier of the destination sub-chip in the data packet indicates that the destination sub-chips are sub-chip 0 and sub-chip 10. Sub-chip 0 is located in the second area, and sub-chip 10 is located in the fourth area. Then, sub-chip 5 can regenerate two data packets based on the data in the received data packet: data packet C and data packet D. Data packet C includes data and the identifier of sub-chip 0, and data packet D includes data and the identifier of sub-chip 10. Then, send data packet C along the direction of the second axis or the third axis. For example, send data packet C along the direction of the second axis, that is, first send data packet C to sub-chip 4, and then sub-chip 4 forwards data packet C to sub-chip 0. In addition, sub-chip 5 sends data packet D along the direction of the first axis or the fourth axis. For example, send data packet D along the direction of the first axis, that is, first send data packet D to sub-chip 6, and then sub-chip 6 forwards it to sub-chip 10.

[0112] In a possible implementation manner, the above-mentioned first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip. The above-mentioned first sub-chip sends the data in the above-mentioned first data packet to the above-mentioned destination sub-chip based on the direction coordinate system with the principle of consuming less bandwidth, including: in the direction coordinate system established with the above-mentioned first sub-chip as the center, when the first destination sub-chip is in the target area and the second destination sub-chip is on the direction axis of the boundary of the target area, the first sub-chip sends the fifth data packet along the direction axis of the boundary of the target area. The fifth data packet includes the data and the identifiers of the first destination sub-chip and the second destination sub-chip. The target area is the first area, the second area, the third area or the fourth area. For the sake of understanding, combined with the above Figure 11 as an example for illustration.

[0113] In Figure 11 , assume that sub-chip 5 is the above-mentioned first sub-chip, and it receives a data packet. The identifier of the destination sub-chip in the data packet indicates that the destination sub-chips are sub-chip 14 and sub-chip 9. Sub-chip 14 is located in the fourth area, and sub-chip 9 is on the fourth axis. The fourth axis is the boundary direction axis of the fourth area. Then, sub-chip 5 can send the received data packet along the direction of the fourth axis, that is, send it to sub-chip 9. After receiving the data packet, sub-chip 9 stores the data in the data packet. And copy the data to regenerate a data packet. The new data packet includes the identifier of sub-chip 14, and then sends the new data packet to sub-chip 13 or sub-chip 10, and then sub-chip 13 or sub-chip 10 forwards it to sub-chip 14.

[0114] In a possible implementation manner, the above-mentioned first sub-chip can also send the data in the above-mentioned first data packet based on the congestion condition of its own port.

[0115] Specifically, based on the above introduction to the chip system, each sub-chip includes multiple ports for communicating with other sub-chips. Among them, each port is configured with a corresponding transmission buffer, and the transmission buffer is used to store data to be transmitted.

[0116] After the first sub-chip receives the first data packet, it parses the first data packet to obtain the identifier of the destination sub-chip in the first data packet. If the identifier of the destination sub-chip indicates that the first sub-chip is the destination sub-chip, then the first sub-chip extracts and stores the data in the first data packet for subsequent processing. Otherwise, the first sub-chip uses the identifier of the destination sub-chip as an index to search for the transmission port of the first data packet in its own forwarding mapping table. For the introduction of the forwarding mapping table, reference can be made to the corresponding description in the foregoing description of Figure 2 and details are not repeated here. If multiple found transmission ports exist, then the specific transmission port can be determined based on the congestion conditions of the transmission buffers of the multiple transmission ports. Specifically, to improve the data transmission efficiency, the port with the least amount of data to be transmitted in the transmission buffers of the multiple transmission ports can be selected to transmit the first data packet.

[0117] Optionally, the forwarding mapping table in the first sub-chip can be initialized based on the above direction coordinate system and the above principle of less bandwidth consumption. Exemplarily, taking Figure 11 as an example, assume that sub-chip 5 is the first sub-chip, and assume that sub-chip 2 is the destination sub-chip. Then, based on the constructed direction coordinate system and the principle of less bandwidth consumption, sub-chip 5 can determine that a data packet destined for sub-chip 2 can be sent through its own port d0 or d1. Therefore, in the forwarding mapping table of sub-chip 5, the transmission port corresponding to the destination of sub-chip 2 is port d0 or d1. The situations of other destination sub-chips can refer to the description here and are not repeated.

[0118] In a possible implementation manner, if the first data packet includes identifiers of multiple destination sub-chips, and the first sub-chip is one of the destination sub-chips, then the first sub-chip extracts and stores the data in the first data packet for subsequent processing. And the first sub-chip will use the identifiers of the remaining destination sub-chips as an index to search for the transmission port of the data in the first data packet in its own forwarding mapping table.

[0119] If the identifier of the remaining destination sub-chip is one, then, similarly, after finding the corresponding sending port, select the port with the least amount of data to be sent in the sending buffer of the sending port to send the data in the first data packet. Specifically, the data will be repackaged into a data packet for sending. The identifier of the destination sub-chip in the repackaged data packet no longer includes the identifier of the first sub-chip, but only includes the identifier of the remaining destination sub-chip.

[0120] If there are multiple identifiers of the remaining destination sub-chips, then the first sub-chip searches for the corresponding sending ports in its own forwarding mapping table respectively. If the found sending ports are the same, then a new data packet can be generated by copying the data included in the first data packet. The newly generated data packet includes the identifiers of the multiple remaining destination sub-chips. And send the newly generated data packet from the same found sending port. Similarly, the sending port can be the port with the least amount of data to be sent in the sending buffer among the found sending ports.

[0121] Or, if there are multiple identifiers of the remaining destination sub-chips, taking two as an example, assume the remaining destination sub-chips are sub-chip A and sub-chip B. The first sub-chip searches in its own forwarding mapping table for the sending port mapped by the identifier of sub-chip A and the sending port mapped by the identifier of sub-chip B. Assume the found sending ports are different, then the first sub-chip can generate two new data packets: data packet A and data packet B. Both data packets include the data included in the first data packet. Among them, the identifier of the destination sub-chip included in data packet A is the identifier of sub-chip A, and the identifier of the destination sub-chip included in data packet B is the identifier of sub-chip B. Then, send data packet A and data packet B through their respective found sending ports. Similarly, the sending port can be the port with the least amount of data to be sent in the sending buffer among the found sending ports.

[0122] In summary, the embodiments of the present application transmit the received data based on the data transmission situation within the chip system, so as to flexibly schedule the sending of data, improve the data transmission efficiency, and further improve the processing performance of the chip system.

[0123] The above mainly introduces the data transmission processing method in the chip system provided by the embodiments of the present application. It can be understood that in order to implement the corresponding functions, each device includes the corresponding hardware structure and / or software module for executing each function. Combining the units and steps of each example described in the embodiments disclosed in this article, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0124] The embodiments of the present application can divide the functions of the device according to the above method examples. For example, each function module can be divided corresponding to each function, or two or more functions can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software function module. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical function division, and there may be other division methods in actual implementation.

[0125] In the case of dividing each function module corresponding to each function, Figure 12 FIG. shows a specific schematic diagram of the logical structure of the device, and the device may be the above-mentioned first sub-chip. The device 1200 includes:

[0126] A receiving unit 1201, configured to receive a first data packet; wherein, the foregoing first data packet includes an identifier of a destination sub-chip; the foregoing device 1200 and the foregoing destination sub-chip are sub-chips included in the chip system, and the multiple sub-chips in the foregoing chip system are arranged in a matrix, and each sub-chip in the foregoing multiple sub-chips is connected to the adjacent sub-chips around;

[0127] A sending unit 1202, configured to send the data in the foregoing first data packet to the foregoing destination sub-chip based on the direction coordinate system according to the principle of consuming less bandwidth, and the principle of consuming less bandwidth is the principle of delivering the foregoing data to the foregoing destination sub-chip with less transmission bandwidth;

[0128] The foregoing direction coordinate system is constructed with the foregoing device 1200 as the center, and the foregoing direction coordinate system includes a first direction axis, a second direction axis, a third direction axis, and a fourth direction axis; the row where the foregoing device 1200 is located is located on at least one of the foregoing first direction axis and the foregoing second direction axis with opposite directions; the column where the foregoing device 1200 is located is located on at least one of the foregoing third direction axis and the foregoing fourth direction axis with opposite directions.

[0129] In a possible implementation manner, the foregoing sending unit 1202 is specifically configured to:

[0130] When the foregoing destination sub-chip is on the target direction axis, transmit the foregoing data along the direction of the foregoing target direction axis; the foregoing target direction axis is the foregoing first direction axis, the foregoing second direction axis, the foregoing third direction axis, or the foregoing fourth direction axis.

[0131] In a possible implementation, the foregoing direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the foregoing first region is bounded by the foregoing first direction axis and the foregoing third direction axis, the foregoing second region is bounded by the foregoing second direction axis and the foregoing third direction axis, the foregoing third region is bounded by the foregoing second direction axis and the foregoing fourth direction axis, and the foregoing fourth region is bounded by the foregoing first direction axis and the foregoing fourth direction axis;

[0132] The foregoing first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip; the foregoing sending unit 1202 is specifically configured to:

[0133] When the foregoing first destination sub-chip and the second destination sub-chip are respectively in two adjacent regions among the foregoing first region, the second region, the third region, and the fourth region, transmit a second data packet along the direction of the common direction axis; the foregoing second data packet includes the foregoing data, the identifiers of the first destination sub-chip and the second destination sub-chip; the foregoing common direction axis is the direction axis of the common boundary of the foregoing two adjacent regions.

[0134] In a possible implementation, the foregoing direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the foregoing first region is bounded by the foregoing first direction axis and the foregoing third direction axis, the foregoing second region is bounded by the foregoing second direction axis and the foregoing third direction axis, the foregoing third region is bounded by the foregoing second direction axis and the foregoing fourth direction axis, and the foregoing fourth region is bounded by the foregoing first direction axis and the foregoing fourth direction axis;

[0135] The foregoing first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip; the foregoing sending unit 1202 is specifically configured to:

[0136] When the foregoing first destination sub-chip is in the foregoing first region and the foregoing second destination sub-chip is in the foregoing third region, transmit a third data packet along one of the direction axes of the two boundaries of the foregoing first region, and transmit a fourth data packet along one of the direction axes of the two boundary direction axes of the foregoing third region; the foregoing third data packet includes the foregoing data and the identifier of the foregoing first destination sub-chip, and the foregoing fourth data packet includes the foregoing data and the identifier of the foregoing second destination sub-chip.

[0137] In a possible implementation, the aforementioned direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the aforementioned first region is bounded by the aforementioned first direction axis and the aforementioned third direction axis, the aforementioned second region is bounded by the aforementioned second direction axis and the aforementioned third direction axis, the aforementioned third region is bounded by the aforementioned second direction axis and the aforementioned fourth direction axis, and the aforementioned fourth region is bounded by the aforementioned first direction axis and the aforementioned fourth direction axis;

[0138] The aforementioned first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip; the aforementioned sending unit 1202 is specifically configured to:

[0139] When the aforementioned first destination sub-chip is in the target region and the aforementioned second destination sub-chip is on the direction axis of the boundary of the aforementioned target region, send a fifth data packet along the direction of the direction axis of the boundary of the aforementioned target region, and the aforementioned fifth data packet includes the aforementioned data and the identifiers of the aforementioned first destination sub-chip and the second destination sub-chip; the aforementioned target region is the first region, the second region, the third region, or the fourth region.

[0140] In a possible implementation, the aforementioned device 1200 includes multiple ports, each port in the aforementioned multiple ports is connected to another sub-chip, and each port corresponds to a sending buffer, and the sending buffer is used to store the data to be sent;

[0141] The aforementioned device 1200 further includes a selection unit, configured to:

[0142] When there are at least two ports sending the aforementioned data, select the first port to send the aforementioned data; the aforementioned first port is the port with the least amount of data to be sent in the sending buffer among the aforementioned at least two ports.

[0143] In a possible implementation, the identifiers of the destination sub-chips included in the aforementioned first data packet are multiple, and the identifier of the aforementioned device 1200 is included in the identifiers of the aforementioned multiple destination sub-chips; the aforementioned device 1200 further includes:

[0144] A storage unit, configured to store the data in the aforementioned first data packet;

[0145] An encapsulation unit, configured to re-encapsulate the aforementioned data to obtain a sixth data packet;

[0146] The aforementioned sending unit 1202 is further configured to send the aforementioned sixth data packet to the destination sub-chips other than the aforementioned device 1200.

[0147] Figure 13The figure shows a specific hardware structure diagram of the device provided by this application. The device 1300 may be the above-mentioned first sub-chip. The device 1300 includes: a processor 1301, a memory 1302, and a communication port 1303. The processor 1301, the communication port 1303, and the memory 1302 may be connected to each other or connected to each other through a bus 1304.

[0148] Exemplarily, the memory 1302 is used to store the computer programs and data of the device 1300. The memory 1302 may include, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a compact disc read-only memory (CD-ROM), etc. Exemplarily, the memory 1302 may be the static memory shown in the above Figure 2 figure.

[0149] The communication port 1303 includes a sending port and a receiving port. The number of communication ports 1303 may be multiple, and is used to support the device 1300 to communicate, such as receiving or sending data or messages, etc. Exemplarily, the communication port 1303 may be the ports d0, d1, d2, and d3 shown in the above Figure 2 figure.

[0150] Exemplarily, the processor 1301 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination for implementing computing functions, such as a combination including one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc. Exemplarily, the processor 1301 may be the processing module shown in the above Figure 2 figure. The processor 1301 may be used to read the programs stored in the above-mentioned memory 1302, so that the device 1300 executes the operations performed by the first sub-chip described in the above Figure 8 and its specific embodiments.

[0151] Figure 13 For the specific operations and beneficial effects of each unit in the shown device 1300, reference may be made to the corresponding descriptions in the above Figure 8 and its specific method embodiments, which will not be elaborated here.

[0152] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program, and the computer program is executed by a processor to perform the operations performed by the first sub-chip in any one of the above Figure 8 and its possible method embodiments.

[0153] The embodiment of the present application further provides a computer program product. When the computer program product is read and executed by a computer, the operations performed by the first sub-chip in any one of the above Figure 8 and its possible method embodiments will be implemented.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data transmission and processing method in a chip system, characterized in that, the method includes: A first sub-chip receives a first data packet; wherein, the first data packet includes an identifier of a destination sub-chip; the first sub-chip and the destination sub-chip are sub-chips included in the chip system, and multiple sub-chips in the chip system are arranged in a matrix, and each sub-chip in the multiple sub-chips is connected to adjacent surrounding sub-chips; The first sub-chip sends the data in the first data packet to the destination sub-chip based on a direction coordinate system according to the principle of consuming less bandwidth, and the principle of consuming less bandwidth is the principle of delivering the data to the destination sub-chip with less transmission bandwidth; The direction coordinate system is constructed with the first sub-chip as the center, and the direction coordinate system includes a first direction axis, a second direction axis, a third direction axis, and a fourth direction axis; the row where the first sub-chip is located is on at least one of the first direction axis and the second direction axis with opposite directions; the column where the first sub-chip is located is on at least one of the third direction axis and the fourth direction axis with opposite directions.

2. The method according to claim 1, characterized in that, the first sub-chip sending the data in the first data packet to the destination sub-chip based on a direction coordinate system according to the principle of consuming less bandwidth includes: When the destination sub-chip is on a target direction axis, the first sub-chip sends the data along the direction of the target direction axis; the target direction axis is the first direction axis, the second direction axis, the third direction axis, or the fourth direction axis.

3. The method according to claim 1, characterized in that, the direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the first area is bounded by the first direction axis and the third direction axis, the second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the fourth direction axis; the first data packet includes identifiers of a first destination sub-chip and a second destination sub-chip; the first sub-chip sending the data in the first data packet to the destination sub-chip based on a direction coordinate system according to the principle of consuming less bandwidth includes: When the first destination sub-chip and the second destination sub-chip are respectively in two adjacent areas among the first area, the second area, the third area, and the fourth area, the first sub-chip sends a second data packet along the direction of a common direction axis; the second data packet includes the data, the identifier of the first destination sub-chip, and the identifier of the second destination sub-chip; the common direction axis is the direction axis of the common boundary of the two adjacent areas.

4. The method according to claim 1, characterized in that, The direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the first region is bounded by the first direction axis and the third direction axis, the second region is bounded by the second direction axis and the third direction axis, the third region is bounded by the second direction axis and the fourth direction axis, and the fourth region is bounded by the first direction axis and the fourth direction axis; The first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip; The first sub-chip sends the data in the first data packet to the destination sub-chip based on the direction coordinate system according to the principle of consuming less bandwidth, including: When the first destination sub-chip is in the first region and the second destination sub-chip is in the third region, the first sub-chip sends a third data packet along one of the direction axes of the two boundaries of the first region, and sends a fourth data packet along one of the direction axes of the two boundaries of the third region; the third data packet includes the data and the identifier of the first destination sub-chip, and the fourth data packet includes the data and the identifier of the second destination sub-chip.

5. The method according to claim 1, wherein, The direction coordinate system further includes a first region, a second region, a third region, and a fourth region; the first region is bounded by the first direction axis and the third direction axis, the second region is bounded by the second direction axis and the third direction axis, the third region is bounded by the second direction axis and the fourth direction axis, and the fourth region is bounded by the first direction axis and the fourth direction axis; The first data packet includes the identifiers of the first destination sub-chip and the second destination sub-chip; The first sub-chip sends the data in the first data packet to the destination sub-chip based on the direction coordinate system according to the principle of consuming less bandwidth, including: When the first destination sub-chip is in the target region and the second destination sub-chip is on the direction axis of the boundary of the target region, the first sub-chip sends a fifth data packet along the direction axis of the boundary of the target region, and the fifth data packet includes the data and the identifiers of the first destination sub-chip and the second destination sub-chip; the target region is the first region, the second region, the third region, or the fourth region.

6. The method according to claim 1, wherein, The first sub-chip includes a plurality of ports, each of the plurality of ports is connected to another sub-chip, and each port corresponds to a transmission buffer for storing data to be transmitted; The method further includes: When there are at least two ports sending the data, the first sub-chip selects a first port to send the data; the first port is the port with the least amount of data to be transmitted in the transmission buffer among the at least two ports.

7. The method according to any one of claims 1-6, wherein, The first data packet includes multiple identifiers of destination sub-chips, and the identifier of the first sub-chip is included in the multiple identifiers of the destination sub-chips; the method further includes: The first sub-chip stores the data in the first data packet; The first sub-chip repackages the data to obtain a sixth data packet; The first sub-chip sends the sixth data packet to destination sub-chips other than the first sub-chip.

8. A sub-chip, characterized in that, The sub-chip is a first sub-chip, and the first sub-chip includes: A receiving unit, configured to receive a first data packet; wherein, the first data packet includes an identifier of a destination sub-chip; the first sub-chip and the destination sub-chip are sub-chips included in a chip system, and multiple sub-chips in the chip system are arranged in a matrix form, and each sub-chip in the multiple sub-chips is connected to adjacent surrounding sub-chips; A sending unit, configured to send the data in the first data packet to the destination sub-chip based on a direction coordinate system according to the principle of consuming less bandwidth, and the principle of consuming less bandwidth is the principle of delivering the data to the destination sub-chip with less transmission bandwidth; The direction coordinate system is constructed with the first sub-chip as the center, and the direction coordinate system includes a first direction axis, a second direction axis, a third direction axis, and a fourth direction axis; the row where the first sub-chip is located is on at least one of the first direction axis and the second direction axis with opposite directions; the column where the first sub-chip is located is on at least one of the third direction axis and the fourth direction axis with opposite directions.

9. A sub-chip, characterized in that, It includes a processor, a memory, and a communication port; wherein, the memory and the communication port are coupled to the processor, the communication port is used for receiving and sending data, the memory is used for storing a computer program, and the processor is used for calling the computer program so that the sub-chip executes the method according to any one of claims 1-7; The sub-chip is a sub-chip included in a chip system, and multiple sub-chips in the chip system are arranged in a matrix form, and each sub-chip in the multiple sub-chips is connected to adjacent surrounding sub-chips.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1-7 is implemented.

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