Physical unclonable function circuit based on fuzzy feedback shift register

Abstract

The application provides a physical unclonable function circuit based on a fuzzy feedback shift register, the physical unclonable function circuit based on the fuzzy feedback shift register comprises an excitation processing module, a shift register module, an entropy source module, an AND gate processing module, an XOR processing module and a nonlinear fuzzy module. The physical unclonable function circuit based on the fuzzy feedback shift register provided by the application realizes resistance to machine learning modeling attacks, generates a high-security key, and meets actual application requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of physically unclonable circuit, and particularly relates to a physically unclonable function circuit based on fuzzy feedback shift register. BACKGROUND

[0002] In the field of unclonable circuits, silicon-based physically unclonable functions (Silicon-PUF) as a new hardware security primitive rely on integrated circuit process variations, can determine the "challenge-response" mapping relationship, and inherit the randomness, uncontrollability and uniqueness of process variations.

[0003] Compared with traditional cryptographic schemes, PUF has the characteristics of no key storage, on-demand generation and low overhead, and is more suitable for limited device resources in Internet of Things, edge computing and other scenarios. Existing PUFs can be divided into strong PUFs and weak PUFs according to the size of the challenge-response pair (CRP) space. Among them, strong PUFs have a large number of CRPs and are widely used in Internet of Things device authentication. Weak PUFs only have limited CRPs and are not suitable for authentication but for key generation.

[0004] Although PUF shows better performance than traditional security schemes, strong PUFs are vulnerable to machine learning-based modeling attacks, while weak PUFs only provide fixed and limited CRPs for key generation. However, in practical applications, a PUF that can generate a large number of CRPs and resist machine learning modeling attacks is needed. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a physically unclonable function circuit based on fuzzy feedback shift register, which can generate a large number of CRPs and resist machine learning modeling attacks.

[0006] The present application provides a physically unclonable function circuit based on fuzzy feedback shift register, wherein the physically unclonable function circuit based on fuzzy feedback shift register comprises a challenge processing module, a shift register module, an entropy source module, an AND gate processing module, an XOR processing module and a nonlinear fuzzy module.

[0007] The challenge processing module is configured to:

[0008] receive a challenge signal sent by a server, and receive an initialization signal, a fuzzy selection signal and a complement signal to generate a shift selection signal;

[0009] The shift register module is configured to:

[0010] receive the complement signal and the shift selection signal generated by the challenge processing module, and shift according to a clock signal to generate a response signal.

[0011] The entropy source module is used for:

[0012] According to the clock signal and the shift signal generated by the shift register module, an entropy source output signal is obtained;

[0013] The AND gate processing module is used for:

[0014] According to the configuration signal and the entropy source output signal, a configured entropy source output signal is generated;

[0015] The XOR processing module is used for:

[0016] The configured entropy source output signal generated by the AND gate processing module is XOR processed to obtain a complement bit signal;

[0017] The non-linear fuzzy module is used for:

[0018] The configured entropy source output signal is decoded to generate a fuzzy selection signal and output to the excitation processing module.

[0019] The physically unclonable function circuit based on the fuzzy feedback shift register, wherein the excitation processing module comprises a plurality of excitation processing units, and each excitation processing unit comprises:

[0020] an inverter I0, a first AND gate A1, a second AND gate A2, and a data selector D1; wherein an input end of the inverter I0 is connected with an initialization signal init , an output end of the inverter I0 is connected with one input end of the first AND gate A1;

[0021] one input end of the first AND gate A1 is connected with the output end of the inverter I0, and the other input end is connected with a fuzzy selection signal sel , an output end of the first AND gate A1 is connected with a data selection input end of the data selector D1;

[0022] one input end of the second AND gate A2 is connected with an initialization signal init , the other input end is connected with an excitation signal C [i] , an output end of the second AND gate A2 is connected with one data input end of the data selector D1;

[0023] a data selection input end of the data selector D1 is connected with the output end of the first AND gate A1, one data input end of the data selector D1 is connected with a complement bit signal FB , the other data input end of the data selector D1 is connected with the output end of the second AND gate A2, and an output end of the data selector D1 is connected with a shift selection signalR are connected.

[0024] The fuzzy feedback shift register based physically unclonable function circuit, wherein the shift register module comprises a plurality of shift register units, each of the shift register units respectively comprises:

[0025] an XOR gate and a flip-flop; wherein one input end of the XOR gate is connected with a shift selection signal R , the other input end of the XOR gate is connected with the data output signal of the previous flip-flop, and the output end of the XOR gate is connected with the data input end of the flip-flop; wherein when the XOR gate is the first stage, the XOR gate of the first stage is connected with a complement bit signal FB ;

[0026] the data input end of the flip-flop is connected with the output end of the XOR gate, and the data output end of the flip-flop is connected with one input end of the XOR gate in the next shift register unit.

[0027] The fuzzy feedback shift register based physically unclonable function circuit, wherein the entropy source module comprises a plurality of entropy source unit circuits, each of the entropy source unit circuits comprises:

[0028] an inverter I1, an inverter I2, an inverter I3, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube and a seventeenth NMOS tube.

[0029] The fuzzy feedback shift register based physically unclonable function circuit, wherein the input end of the inverter I1 is connected with the fifth PMOS tube drain, the sixth PMOS tube drain, the seventh PMOS tube gate, the fifth NMOS tube drain, the sixth NMOS tube drain, the ninth NMOS tube gate and the tenth NMOS tube gate, and the output end of the inverter I1 is connected with an entropy source output signal OUT ;

[0030] The input end of the inverter I2 is connected with the input end of a clock signal CLK , and the output end of the inverter I2 is connected with the seventeenth NMOS tube gate;

[0031] The input terminal of inverter I3 is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor, the gate of the sixth PMOS transistor, the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor. The output terminal of inverter I3 is connected to the non-signal output of the entropy source.

[0032] The physically unclonable function circuit based on the fuzzy feedback shift register, wherein the gate of the first PMOS transistor is connected to the inverted logic signal. The first PMOS transistor is connected to the power supply terminal, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor.

[0033] The gate of the second PMOS transistor and the clock signal CLK The input terminal is connected, the source of the second PMOS is connected to the drain of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the fifth PMOS transistor.

[0034] The gate of the third PMOS transistor and the entropy source input signal The third PMOS transistor's source is connected to the power supply terminal, and the third PMOS transistor's drain is connected to the fourth PMOS transistor's source.

[0035] The gate of the fourth PMOS transistor and the clock signal CLK The input terminal is connected, the source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor and the gate of the fifth PMOS transistor.

[0036] The gate of the fifth PMOS transistor is connected to the drain of the second PMOS transistor, the drain of the first NMOS transistor, the drain of the fourth PMOS transistor, and the drain of the third NMOS transistor. The source of the fifth PMOS transistor is connected to the power supply terminal. The drain of the fifth PMOS transistor is connected to the input terminal of the inverter I1 and the drain of the fifth NMOS transistor.

[0037] The gate of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor, and the input terminal of the inverter I3. The source of the sixth PMOS transistor is connected to the power supply terminal. The drain of the sixth PMOS transistor is connected to the gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor.

[0038] The gate of the seventh PMOS transistor is connected to the input terminal of inverter I1, the source of the seventh PMOS transistor is connected to the input terminal, and the drain of the seventh PMOS transistor is connected to the input terminal of inverter I3.

[0039] The gate of the eighth PMOS transistor is connected to the drain of the tenth PMOS transistor and the drain of the twelfth PMOS transistor. The source of the eighth PMOS transistor is connected to the power supply terminal. The drain of the eighth PMOS transistor is connected to the input terminal of inverter I3.

[0040] The gate of the ninth PMOS transistor and the entropy source input signal The source of the ninth PMOS transistor is connected to the power supply terminal, and the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor.

[0041] The gate and clock signal of the tenth PMOS transistor CLK The input terminal of the tenth PMOS transistor is connected to the source of the ninth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the gate of the eighth PMOS transistor.

[0042] The gate of the eleventh PMOS transistor and the inverted logic signal The eleventh PMOS transistor's source is connected to the power supply terminal, and the eleventh PMOS transistor's drain is connected to the twelfth PMOS transistor's source.

[0043] The gate of the twelfth PMOS transistor and the clock signal CLK The input terminal is connected, the source of the twelfth PMOS transistor is connected to the drain of the eleventh PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the gate of the eighth PMOS transistor.

[0044] The physically unclonable function circuit based on the fuzzy feedback shift register, wherein the gate of the first NMOS transistor is connected to the clock signal. CLK The input terminals are connected, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the first NMOS transistor is connected to the gate of the fifth PMOS transistor.

[0045] The gate of the second NMOS transistor and the entropy source input signal The second NMOS transistor is connected to the source terminal of the first NMOS transistor, and the drain terminal of the second NMOS transistor is connected to the source terminal of the first NMOS transistor.

[0046] The gate of the third NMOS transistor and the clock signal CLK The input terminal is connected, the source of the third NMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the third NMOS transistor is connected to the gate of the fifth PMOS transistor.

[0047] The gate of the fourth NMOS transistor and the inverted logic signal The fourth NMOS transistor is connected to the source terminal of the third NMOS transistor, and the drain of the fourth NMOS transistor is connected to the source terminal of the third NMOS transistor.

[0048] The gate of the fifth NMOS transistor is connected to the input terminal of inverter I3, the source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the fifth NMOS transistor is connected to the input terminal of inverter I1.

[0049] The gate of the sixth NMOS transistor is connected to the input terminal of inverter I3, the source of the sixth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the drain of the sixth NMOS transistor is connected to the input terminal of inverter I1.

[0050] The gate of the seventh NMOS transistor and the entropy source input signal The source of the seventh NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the seventh NMOS transistor is connected to the source of the fifth NMOS transistor.

[0051] The gate of the eighth NMOS transistor and the inverted logic signal The source of the eighth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the eighth NMOS transistor is connected to the source of the sixth NMOS transistor.

[0052] The gate of the ninth NMOS transistor is connected to the input terminal of inverter I1, the source of the ninth NMOS transistor is connected to the drain of the eleventh NMOS transistor, and the drain of the ninth NMOS transistor is connected to the input terminal of inverter I3.

[0053] The gate of the tenth NMOS transistor is connected to the input terminal of inverter I1, the source of the tenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the drain of the tenth NMOS transistor is connected to the input terminal of inverter I3.

[0054] The gate of the eleventh NMOS transistor and the inverted logic signal The eleventh NMOS transistor's source is connected to the seventeenth NMOS transistor's drain, and the eleventh NMOS transistor's drain is connected to the ninth NMOS transistor's source.

[0055] The gate of the twelfth NMOS transistor and the entropy source input signal The source of the twelfth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the twelfth NMOS transistor is connected to the source of the tenth NMOS transistor.

[0056] The gate and clock signal of the thirteenth NMOS transistor CLK The input terminal is connected, the source of the thirteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, and the drain of the thirteenth NMOS transistor is connected to the gate of the eighth PMOS transistor.

[0057] The gate of the fourteenth NMOS transistor and the clock signal CLKThe input terminal is connected, the source of the fourteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, and the drain of the fourteenth NMOS transistor is connected to the gate of the eighth PMOS transistor;

[0058] The gate of the fifteenth NMOS transistor and the inverted logic signal The source of the fifteenth NMOS transistor is connected to the ground terminal, and the drain of the fifteenth NMOS transistor is connected to the source of the thirteenth NMOS transistor.

[0059] The gate of the sixteenth NMOS transistor and the entropy source input signal The source of the sixteenth NMOS transistor is connected to the ground terminal, and the drain of the sixteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor.

[0060] The gate of the seventeenth NMOS transistor is connected to the output terminal of inverter I2, the source of the seventeenth NMOS transistor is connected to the ground terminal, and the drain of the seventeenth NMOS transistor is connected to the source of the seventh NMOS transistor, the source of the eighth NMOS transistor, the source of the eleventh NMOS transistor, and the source of the twelfth NMOS transistor.

[0061] The physically unclonable function circuit based on the fuzzy feedback shift register includes an AND gate processing module comprising multiple AND gate units, one input of which is connected to the entropy source output signal of the entropy source module. OUT Connected, the other input of the AND gate unit is connected to the configuration signal. S The output of the AND gate unit is connected to the input of the XOR module.

[0062] The physically non-cloning function circuit based on the fuzzy feedback shift register, wherein the input terminal of the XOR processing module is connected to the output terminal of the AND gate processing module, and the output terminal of the XOR processing module is connected to the complement signal. FB Connected.

[0063] The physically unclonable function circuit based on fuzzy feedback shift register includes a nonlinear fuzzy module comprising multiple pre-addressing circuits and multiple decoder circuits. The input of each pre-addressing circuit is connected to the corresponding configured entropy source output signal t, and the output of each pre-addressing circuit is connected to the corresponding decoder circuit. The input of each decoder circuit is connected to the output of the corresponding pre-addressing circuit, and the output of each decoder circuit is connected to the excitation processing module.

[0064] Other features and advantages of the invention will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0065] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0066] Figure 1 This is a schematic diagram of the structure of an m*n bit physically unclonable function circuit based on a fuzzy feedback shift register in a specific embodiment of the present invention;

[0067] Figure 2 This is a schematic diagram of the circuit structure of the excitation processing unit in the excitation processing module in a specific embodiment of the present invention;

[0068] Figure 3 This is a schematic diagram of the circuit structure of the shift register unit in the shift register module in a specific embodiment of the present invention;

[0069] Figure 4 This is a schematic diagram of the circuit structure of the entropy source unit in the entropy source module in a specific embodiment of the present invention;

[0070] Figure 5 This is a schematic diagram of the circuit structure of the AND gate processing module and the XOR processing module in a specific embodiment of the present invention;

[0071] Figure 6 This is a schematic diagram of the circuit structure of the nonlinear fuzzy module in a specific embodiment of the present invention.

[0072] Explanation of key symbols:

[0073] C [1]~ C

[64] Excitation signal;

[0074] S [1]~ S

[16] Configure signals;

[0075] R [1]~ R

[64] Shift selection signal;

[0076] Q [1]~ Q

[64] Shift signal;

[0077] sel[1] ~ sel

[64] Fuzzy selection signal;

[0078] ES cell[1]~ES cell

[16] Entropy source units;

[0079] t [1]~ t

[16] The configured entropy source selection signal;

[0080] Response Response signal;

[0081] CLK Clock signal;

[0082] FB Replacement signal;

[0083] init Initialize signals;

[0084] Pre-address operation;

[0085] Inverters I0~I3;

[0086] AND gates A1~A2;

[0087] D1 Data Selector;

[0088] OUT Entropy source output signal;

[0089] The entropy source outputs a non-signal;

[0090] PM1~PM12 PMOS;

[0091] NM1~NM17 NMOS;

[0092] ~ Invert logic signals;

[0093] ~ Entropy source input signal. Detailed Implementation

[0094] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0095] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0096] Please see Figure 1This invention proposes a physically unclonable function circuit based on a fuzzy feedback shift register, wherein the physically unclonable function circuit based on the fuzzy feedback shift register includes an excitation processing module, a shift register module, an entropy source module, an AND gate processing module, an XOR processing module, and a nonlinear fuzzy module.

[0097] Specifically, the stimulus processing module is used for:

[0098] Receive excitation signals sent by the server C[i] and receiving initialization signals inti Fuzzy selection signal sel , Complementary signal FB And generate a shift selection signal R ;

[0099] The shift register module is used for:

[0100] Receive complement signal FB and the shift selection signal generated by the excitation processing module R And according to the clock signal CLK Perform shifting to generate a response signal Response ;

[0101] The entropy source module is used for:

[0102] According to the clock signal CLK and the shift signal generated by the shift register module Q To obtain the entropy source output signal OUT ;

[0103] The AND gate processing module is used for:

[0104] According to the configuration signal S and the entropy source output signal to generate the configured entropy source output signal. t ;

[0105] The XOR processing module is used for:

[0106] The configured entropy source output signal generated by the AND gate processing module t Perform an XOR operation to obtain the replacement signal. FB ;

[0107] The nonlinear fuzzy module is used for:

[0108] Output signal for the configured entropy source t Decoding is performed to generate a fuzzy selection signal, which is then output to the excitation processing module.

[0109] The aforementioned nonlinear fuzzy module includes multiple pre-addressing circuits and multiple decoder circuits, with the input of each pre-addressing circuit corresponding to the output signal of a pre-configured entropy source.t The output of each pre-addressing circuit is connected to a corresponding decoder circuit. The input of each decoder circuit is connected to the output of its corresponding pre-addressing circuit, and the output of each decoder circuit is connected to the excitation processing module. Each decoder circuit input receives a signal generated by its corresponding pre-addressing circuit and generates a fuzzy selection signal based on the decoded signal. sel Simultaneously, the fuzzy selection signal sel Output to the stimulus processing module.

[0110] Please see Figure 2 The aforementioned stimulus processing module includes multiple stimulus processing units, wherein each of the stimulus processing units includes:

[0111] The inverter I0, the first AND gate A1, the second AND gate A2, and the data selector D1; wherein, the input of the inverter I0 is connected to the initialization signal. init The output of inverter I0 is connected to one input of the first AND gate A1.

[0112] One input of the first AND gate A1 is connected to the output of the inverter I0, and the other input is connected to the fuzzy selection signal. sel The output of the first AND gate A1 is connected to the data selection input of the data selector D1.

[0113] One input of the second AND gate A2 is connected to the initialization signal. init Connected to the other input terminal, and connected to the excitation signal. C[i] The output of the second AND gate A2 is connected to one of the data inputs of the data selector D1.

[0114] The data selection input of data selector D1 is connected to the output of the first AND gate A1, and one data input of data selector D1 is connected to the complement signal. FB The other data input terminal of data selector D1 is connected to the output terminal of the second AND gate A2, and the output terminal of data selector D1 is connected to the shift selection signal. R Connected.

[0115] When the initialization signal init is 1, the inverter I0 outputs 0, the AND gate A1 outputs 0, and the AND gate A2 outputs the excitation signal. C[i] When the data selection terminal of data selector D1 is 0, data selector D1 will select the excitation signal. C[i] Output, i.e., receiving the excitation signal sent by the server. C[i] When the initialization signal init is 0, the inverter I0 outputs 1, AND gate A1 outputs sel, AND gate A2 outputs 0, and the data selector D1 selects sel. When sel is 1, the data selector D1 outputs a filler signal. FBWhen sel is 0, the data selector D1 outputs 0.

[0116] Please see Figure 3 The aforementioned shift register module includes multiple shift register units, each of which includes:

[0117] An XOR gate and a flip-flop; wherein one input of the XOR gate is connected to a shift selection signal. R The XOR gate is connected to the data output signal of the previous flip-flop, and its output is connected to the data input of the flip-flop. Specifically, when the XOR gate is in its first stage, the XOR gate in the first stage is connected to the complement signal. FB Connected.

[0118] It should also be noted that the data input of the flip-flop is connected to the output of the XOR gate, and the data output of the flip-flop is connected to one input of the XOR gate in the next shift register unit.

[0119] In this embodiment, the input of each shift register unit is connected to the output of an AND-XOR gate, and the two inputs of the XOR gate are respectively connected to the shift signal of the previous stage. Q and shift selection signal R When the shift selection signal R When the value is 0, the XOR gate output is the shift signal from the previous stage. Q ,when R When the value is 1, the XOR gate output is the shift signal of the previous stage. Q The illogical, whenever CLK The shift occurs when the rising edge arrives.

[0120] Please see Figure 4 The aforementioned entropy source module includes multiple entropy source unit circuits, each of which includes:

[0121] Inverter I1, inverter I2, inverter I3, first PMOS transistor, second PMOS transistor, third PMOS transistor, fourth PMOS transistor, fifth PMOS transistor, sixth PMOS transistor, seventh PMOS transistor, eighth PMOS transistor, ninth PMOS transistor, tenth PMOS transistor, eleventh PMOS transistor, twelfth PMOS transistor, first NMOS transistor, second NMOS transistor, third NMOS transistor, fourth NMOS transistor, fifth NMOS transistor, sixth NMOS transistor, seventh NMOS transistor, eighth NMOS transistor, ninth NMOS transistor, tenth NMOS transistor, eleventh NMOS transistor, twelfth NMOS transistor, thirteenth NMOS transistor, fourteenth NMOS transistor, fifteenth NMOS transistor, sixteenth NMOS transistor, and seventeenth NMOS transistor.

[0122] The input terminal of inverter I1 is connected to the drain of the fifth PMOS transistor, the drain of the sixth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the gate of the ninth NMOS transistor, and the gate of the tenth NMOS transistor. The output terminal of inverter I1 is connected to the entropy source output signal. OUT Connected;

[0123] The input of inverter I2 is connected to the clock signal. CLK The input terminal of the inverter I2 is connected to the input terminal, and the output terminal of the inverter I2 is connected to the gate of the seventeenth NMOS transistor.

[0124] The input terminal of inverter I3 is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor, the gate of the sixth PMOS transistor, the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor. The output terminal of inverter I3 is connected to the entropy source output NOT signal. Connected.

[0125] Furthermore, the gate of the first PMOS transistor is connected to the inverted logic signal. The first PMOS transistor's source is connected to the power supply terminal, and the first PMOS transistor's drain is connected to the second PMOS transistor's source.

[0126] Second PMOS transistor gate and clock signal CLK The input terminal is connected, the source of the second PMOS is connected to the drain of the first PMOS, and the drain of the second PMOS is connected to the drain of the first NMOS and the gate of the fifth PMOS.

[0127] The gate of the third PMOS transistor and the entropy source input signal The third PMOS transistor's source is connected to the power supply terminal, and the third PMOS transistor's drain is connected to the fourth PMOS transistor's source.

[0128] Fourth PMOS transistor gate and clock signal CLK The input terminals are connected, the source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor and the gate of the fifth PMOS transistor.

[0129] The gate of the fifth PMOS transistor is connected to the drain of the second PMOS transistor, the drain of the first NMOS transistor, the drain of the fourth PMOS transistor, and the drain of the third NMOS transistor. The source of the fifth PMOS transistor is connected to the power supply terminal. The drain of the fifth PMOS transistor is connected to the input terminal of the inverter I1 and the drain of the fifth NMOS transistor.

[0130] The gate of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor, and the input terminal of inverter I3. The source of the sixth PMOS transistor is connected to the power supply terminal. The drain of the sixth PMOS transistor is connected to the gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor.

[0131] The gate of the seventh PMOS transistor is connected to the input terminal of inverter I1, the source of the seventh PMOS transistor is connected to the input terminal, and the drain of the seventh PMOS transistor is connected to the input terminal of inverter I3.

[0132] The gate of the eighth PMOS transistor is connected to the drain of the tenth PMOS transistor and the drain of the twelfth PMOS transistor. The source of the eighth PMOS transistor is connected to the power supply terminal. The drain of the eighth PMOS transistor is connected to the input terminal of inverter I3.

[0133] Gate and entropy source input signal of the ninth PMOS transistor The source of the ninth PMOS transistor is connected to the power supply terminal, and the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor.

[0134] Gate and clock signal of the 10th PMOS transistor CLK The input terminals are connected, the source of the tenth PMOS transistor is connected to the drain of the ninth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the gate of the eighth PMOS transistor.

[0135] Eleventh PMOS transistor gate and invert logic signal The eleventh PMOS transistor's source is connected to the power supply terminal, and the eleventh PMOS transistor's drain is connected to the twelfth PMOS transistor's source.

[0136] The gate and clock signal of the twelfth PMOS transistor CLK The input terminals are connected, the source of the twelfth PMOS transistor is connected to the drain of the eleventh PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the gate of the eighth PMOS transistor.

[0137] Gate of the first NMOS transistor and clock signal CLK The input terminals are connected, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the first NMOS transistor is connected to the gate of the fifth PMOS transistor.

[0138] The gate of the second NMOS transistor and the entropy source input signal The second NMOS transistor is connected to the source terminal of the first NMOS transistor, and the drain terminal of the second NMOS transistor is connected to the source terminal of the first NMOS transistor.

[0139] Third NMOS transistor gate and clock signal CLK The input terminals are connected, the source of the third NMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the third NMOS transistor is connected to the gate of the fifth PMOS transistor.

[0140] Gate and inverted logic signal of the fourth NMOS transistor The fourth NMOS transistor is connected to the source terminal of the third NMOS transistor, and the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor.

[0141] The gate of the fifth NMOS transistor is connected to the input terminal of inverter I3, the source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the fifth NMOS transistor is connected to the input terminal of inverter I1.

[0142] The gate of the sixth NMOS transistor is connected to the input terminal of inverter I3, the source of the sixth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the drain of the sixth NMOS transistor is connected to the input terminal of inverter I1.

[0143] Gate and entropy source input signal of the seventh NMOS transistor The source of the seventh NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the seventh NMOS transistor is connected to the source of the fifth NMOS transistor.

[0144] Gate and Invert Logic Signal of the Eighth NMOS Transistor The source of the eighth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the eighth NMOS transistor is connected to the source of the sixth NMOS transistor.

[0145] The gate of the ninth NMOS transistor is connected to the input terminal of inverter I1, the source of the ninth NMOS transistor is connected to the drain of the eleventh NMOS transistor, and the drain of the ninth NMOS transistor is connected to the input terminal of inverter I3.

[0146] The gate of the tenth NMOS transistor is connected to the input terminal of inverter I1, the source of the tenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the drain of the tenth NMOS transistor is connected to the input terminal of inverter I3.

[0147] Gate and Inverting Logic Signal of the Eleventh NMOS Transistor The eleventh NMOS transistor's source is connected to the seventeenth NMOS transistor's drain, and the eleventh NMOS transistor's drain is connected to the ninth NMOS transistor's source.

[0148] Gate and entropy source input signals of the twelfth NMOS transistor The source of the twelfth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the twelfth NMOS transistor is connected to the source of the tenth NMOS transistor.

[0149] The gate and clock signal of the thirteenth NMOS transistor CLK The input terminals are connected, the source of the thirteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, and the drain of the thirteenth NMOS transistor is connected to the gate of the eighth PMOS transistor.

[0150] The gate and clock signal of the fourteenth NMOS transistor CLK The input terminals are connected, the source of the fourteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, and the drain of the fourteenth NMOS transistor is connected to the gate of the eighth PMOS transistor.

[0151] Gate and invert logic signal of the fifteenth NMOS transistor The source of the fifteenth NMOS transistor is connected to the ground terminal, and the drain of the fifteenth NMOS transistor is connected to the source of the thirteenth NMOS transistor.

[0152] The gate and entropy source input signals of the sixteenth NMOS transistor The source of the sixteenth NMOS transistor is connected to the ground terminal, and the drain of the sixteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor.

[0153] The gate of the seventeenth NMOS transistor is connected to the output terminal of inverter I2, the source of the seventeenth NMOS transistor is connected to the ground terminal, and the drain of the seventeenth NMOS transistor is connected to the source of the seventh NMOS transistor, the source of the eighth NMOS transistor, the source of the eleventh NMOS transistor, and the source of the twelfth NMOS transistor.

[0154] In this embodiment, when the clock signal CLK When the value is 1, the entropy source module is configured with an initial value. OUT = =0; when CLK When the falling edge arrives, the circuit receives the clock signal simultaneously from both the left and right sides to the entropy source unit circuit. Due to process variations, the clock signals on both sides... CLK The delay time from input to output is different; if the delay time from input to output on the left is shorter, then... OUT =1, due to the cross-coupling structure, this result will... Keep the original value of 0; conversely, if the input-to-output delay time on the right is shorter, then... =1, due to the cross-coupling structure, this result will... OUT Keep the original value of 0. This achieves the result that the entropy source output signal OUT is determined by process deviation, and the entropy source output signal has randomness and unpredictability.

[0155] Please see Figure 5 The AND gate processing module includes multiple AND gate units, one input of which is connected to the entropy source output signal of the entropy source module. OUT Connected, the other input of the AND gate unit is connected to the configuration signal. S The output of the AND gate unit is connected to the input of the XOR module.

[0156] Specifically, such as Figure 5The diagram shows the circuits for the AND gate processing module and the XOR processing module. The input terminal of the AND processing module receives the output signal from the entropy source module and processes it according to the corresponding configuration signal. S The process involves performing operations and processing to obtain the configured entropy source output signal. t The XOR processing module input receives the configured entropy source output signal generated by the processing module. t Output signals of all configured entropy sources t XOR processing yields the complement signal FB .

[0157] Please see Figure 6 The input of the XOR processing module is connected to the output of the AND gate processing module, and the output of the XOR processing module is connected to the complement signal. FB Connected.

[0158] Specifically, such as Figure 6 The diagram shows a nonlinear fuzzy logic module circuit, where the input of the pre-addressing circuit receives the configured entropy source output signal generated by the AND gate processing module. t The pre-addressing circuit outputs a signal to the configured entropy source. t The address fetch operation is performed, and the address is input to the decoder circuit. The decoder circuit decodes every 6 consecutive bits of the address, and when decoding to the highest 5 bits of the address, any remaining bits are padded from the least significant bit to obtain the address. m A fuzzy selection signal sel and fuzzy selection signal sel Output to the stimulus processing module.

[0159] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A physically unclonable function circuit based on a fuzzy feedback shift register, characterized in that, The physical non-clonable function circuit based on fuzzy feedback shift register includes an excitation processing module, a shift register module, an entropy source module, an AND gate processing module, an XOR processing module, and a nonlinear fuzzy module. The stimulus processing module is used for: It receives excitation signals sent by the server, as well as initialization signals, fuzzy selection signals, and fill signals, and generates shift selection signals. The shift register module is used for: It receives the complement signal and the shift selection signal generated by the excitation processing module, and shifts according to the clock signal to generate a response signal; The entropy source module is used for: The entropy source output signal is obtained based on the clock signal and the shift signal generated by the shift register module; The AND gate processing module is used for: The configured entropy source output signal is generated based on the configuration signal and the entropy source output signal. The XOR processing module is used for: The configured entropy source output signal generated by the AND gate processing module is XORed to obtain the complement signal; The nonlinear fuzzy module is used for: The configured entropy source output signal is decoded to generate a fuzzy selection signal, which is then output to the excitation processing module.

2. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 1, characterized in that, The stimulus processing module includes multiple stimulus processing units, wherein each stimulus processing unit includes: The inverter I0, the first AND gate A1, the second AND gate A2, and the data selector D1; wherein, the input of the inverter I0 is connected to the initialization signal. init The output of inverter I0 is connected to one input of the first AND gate A1. One input of the first AND gate A1 is connected to the output of the inverter I0, and the other input is connected to the fuzzy selection signal. sel The output of the first AND gate A1 is connected to the data selection input of the data selector D1. One input of the second AND gate A2 is connected to the initialization signal. init Connected to the other input terminal, and connected to the excitation signal. C[i] The output of the second AND gate A2 is connected to one of the data inputs of the data selector D1. The data selection input terminal of the data selector D1 is connected to the output terminal of the first AND gate A1. One data input terminal of the data selector D1 is connected to the complement signal. FB The other data input terminal of the data selector D1 is connected to the output terminal of the second AND gate A2, and the output terminal of the data selector D1 is connected to the shift selection signal. R Connected.

3. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 1, characterized in that, The shift register module includes multiple shift register units, each of which includes: An XOR gate and a flip-flop; wherein one input of the XOR gate is connected to a shift selection signal. R The XOR gate is connected to the data output signal of the previous flip-flop, and its output is connected to the data input of the flip-flop. When the XOR gate is in its first stage, the XOR gate in the first stage is connected to the complement signal. FB Connected; The data input terminal of the flip-flop is connected to the output terminal of the XOR gate, and the data output terminal of the flip-flop is connected to one input terminal of the XOR gate in the next shift register unit.

4. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 1, characterized in that, The entropy source module includes multiple entropy source unit circuits, and each entropy source unit circuit includes: Inverter I1, inverter I2, inverter I3, first PMOS transistor, second PMOS transistor, third PMOS transistor, fourth PMOS transistor, fifth PMOS transistor, sixth PMOS transistor, seventh PMOS transistor, eighth PMOS transistor, ninth PMOS transistor, tenth PMOS transistor, eleventh PMOS transistor, twelfth PMOS transistor, first NMOS transistor, second NMOS transistor, third NMOS transistor, fourth NMOS transistor, fifth NMOS transistor, sixth NMOS transistor, seventh NMOS transistor, eighth NMOS transistor, ninth NMOS transistor, tenth NMOS transistor, eleventh NMOS transistor, twelfth NMOS transistor, thirteenth NMOS transistor, fourteenth NMOS transistor, fifteenth NMOS transistor, sixteenth NMOS transistor, and seventeenth NMOS transistor.

5. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 4, characterized in that, The input terminal of inverter I1 is connected to the drain of the fifth PMOS transistor, the drain of the sixth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the gate of the ninth NMOS transistor, and the gate of the tenth NMOS transistor. The output terminal of inverter I1 is connected to the entropy source output signal. OUT Connected; The input terminal of the inverter I2 is connected to the clock signal. CLK The input terminal of the inverter I2 is connected to the input terminal, and the output terminal of the inverter I2 is connected to the gate of the seventeenth NMOS transistor. The input terminal of inverter I3 is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor, the gate of the sixth PMOS transistor, the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor. The output terminal of inverter I3 is connected to the non-signal output of the entropy source.

6. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 5, characterized in that, The gate of the first PMOS transistor and the inverted logic signal The first PMOS transistor is connected to the power supply terminal, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The gate of the second PMOS transistor and the clock signal CLK The input terminal is connected, the source of the second PMOS is connected to the drain of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the fifth PMOS transistor. The gate of the third PMOS transistor and the entropy source input signal The third PMOS transistor's source is connected to the power supply terminal, and the third PMOS transistor's drain is connected to the fourth PMOS transistor's source. The gate of the fourth PMOS transistor and the clock signal CLK The input terminal is connected, the source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor and the gate of the fifth PMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the second PMOS transistor, the drain of the first NMOS transistor, the drain of the fourth PMOS transistor, and the drain of the third NMOS transistor. The source of the fifth PMOS transistor is connected to the power supply terminal. The drain of the fifth PMOS transistor is connected to the input terminal of the inverter I1 and the drain of the fifth NMOS transistor. The gate of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor, and the input terminal of the inverter I3. The source of the sixth PMOS transistor is connected to the power supply terminal. The drain of the sixth PMOS transistor is connected to the gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor. The gate of the seventh PMOS transistor is connected to the input terminal of inverter I1, the source of the seventh PMOS transistor is connected to the input terminal, and the drain of the seventh PMOS transistor is connected to the input terminal of inverter I3. The gate of the eighth PMOS transistor is connected to the drain of the tenth PMOS transistor and the drain of the twelfth PMOS transistor. The source of the eighth PMOS transistor is connected to the power supply terminal. The drain of the eighth PMOS transistor is connected to the input terminal of inverter I3. The gate of the ninth PMOS transistor and the entropy source input signal The source of the ninth PMOS transistor is connected to the power supply terminal, and the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor. The gate and clock signal of the tenth PMOS transistor CLK The input terminal of the tenth PMOS transistor is connected to the source of the ninth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the gate of the eighth PMOS transistor. The gate of the eleventh PMOS transistor and the inverted logic signal The eleventh PMOS transistor's source is connected to the power supply terminal, and the eleventh PMOS transistor's drain is connected to the twelfth PMOS transistor's source. The gate of the twelfth PMOS transistor and the clock signal CLK The input terminal is connected, the source of the twelfth PMOS transistor is connected to the drain of the eleventh PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the gate of the eighth PMOS transistor.

7. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 6, characterized in that, The gate of the first NMOS transistor and the clock signal CLK The input terminals are connected, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the first NMOS transistor is connected to the gate of the fifth PMOS transistor. The gate of the second NMOS transistor and the entropy source input signal The second NMOS transistor is connected to the source terminal of the first NMOS transistor, and the drain terminal of the second NMOS transistor is connected to the source terminal of the first NMOS transistor. The gate of the third NMOS transistor and the clock signal CLK The input terminal is connected, the source of the third NMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the third NMOS transistor is connected to the gate of the fifth PMOS transistor. The gate of the fourth NMOS transistor and the inverted logic signal The fourth NMOS transistor is connected to the source terminal of the third NMOS transistor, and the drain of the fourth NMOS transistor is connected to the source terminal of the third NMOS transistor. The gate of the fifth NMOS transistor is connected to the input terminal of inverter I3, the source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the fifth NMOS transistor is connected to the input terminal of inverter I1. The gate of the sixth NMOS transistor is connected to the input terminal of inverter I3, the source of the sixth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the drain of the sixth NMOS transistor is connected to the input terminal of inverter I1. The gate of the seventh NMOS transistor and the entropy source input signal The source of the seventh NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the seventh NMOS transistor is connected to the source of the fifth NMOS transistor. The gate of the eighth NMOS transistor and the inverted logic signal The source of the eighth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the eighth NMOS transistor is connected to the source of the sixth NMOS transistor. The gate of the ninth NMOS transistor is connected to the input terminal of inverter I1, the source of the ninth NMOS transistor is connected to the drain of the eleventh NMOS transistor, and the drain of the ninth NMOS transistor is connected to the input terminal of inverter I3. The gate of the tenth NMOS transistor is connected to the input terminal of inverter I1, the source of the tenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the drain of the tenth NMOS transistor is connected to the input terminal of inverter I3. The gate of the eleventh NMOS transistor and the inverted logic signal The eleventh NMOS transistor's source is connected to the seventeenth NMOS transistor's drain, and the eleventh NMOS transistor's drain is connected to the ninth NMOS transistor's source. The gate of the twelfth NMOS transistor and the entropy source input signal The source of the twelfth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the drain of the twelfth NMOS transistor is connected to the source of the tenth NMOS transistor. The gate and clock signal of the thirteenth NMOS transistor CLK The input terminal is connected, the source of the thirteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, and the drain of the thirteenth NMOS transistor is connected to the gate of the eighth PMOS transistor. The gate of the fourteenth NMOS transistor and the clock signal CLK The input terminal is connected, the source of the fourteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, and the drain of the fourteenth NMOS transistor is connected to the gate of the eighth PMOS transistor; The gate of the fifteenth NMOS transistor and the inverted logic signal The source of the fifteenth NMOS transistor is connected to the ground terminal, and the drain of the fifteenth NMOS transistor is connected to the source of the thirteenth NMOS transistor. The gate of the sixteenth NMOS transistor and the entropy source input signal The source of the sixteenth NMOS transistor is connected to the ground terminal, and the drain of the sixteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor. The gate of the seventeenth NMOS transistor is connected to the output terminal of inverter I2, the source of the seventeenth NMOS transistor is connected to the ground terminal, and the drain of the seventeenth NMOS transistor is connected to the source of the seventh NMOS transistor, the source of the eighth NMOS transistor, the source of the eleventh NMOS transistor, and the source of the twelfth NMOS transistor.

8. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 1, characterized in that, The AND gate processing module includes multiple AND gate units, one input of each AND gate unit being connected to the entropy source output signal of the entropy source module. OUT Connected, the other input of the AND gate unit is connected to the configuration signal. S The output of the AND gate unit is connected to the input of the XOR module.

9. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 1, characterized in that, The input terminal of the XOR processing module is connected to the output terminal of the AND gate processing module, and the output terminal of the XOR processing module is connected to the complement signal. FB Connected.

10. The physically unclonable function circuit based on a fuzzy feedback shift register according to claim 1, characterized in that, The nonlinear fuzzy module includes multiple pre-addressing circuits and multiple decoder circuits, with the input of each pre-addressing circuit corresponding to the output signal of a pre-configured entropy source. OUT The output of the pre-address circuit is connected to the corresponding decoder circuit; the input of each decoder circuit is connected to the output of the corresponding pre-address circuit, and the output of each decoder circuit is connected to the excitation processing module.

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