A gate-controlled fast ionization transistor and its symmetrical structure

Abstract

The present invention discloses a gate-controlled fast ionization transistor, which comprises, from bottom to top, a cathode metal, a substrate, an epitaxial layer, an anode metal, and a gate metal; wherein a first doping region, a second doping region, a third doping region, and a fourth doping region are provided within the epitaxial layer; wherein the first doping region and the second doping region are adjacent, the third doping region is located within the second doping region, and the fourth doping region is located within the third doping region; the anode metal is located above the fourth doping region; the gate metal is located above the epitaxial layer between the third doping region and the first doping region, and a gate and a gate dielectric layer are further provided between the gate metal and the epitaxial layer. The present invention reduces the device breakdown voltage through gate control, and the device undergoes reversible avalanche breakdown to generate plasma device conduction. This design greatly improves the device input impedance, reduces leakage, and lowers the requirements for the trigger signal. It also reduces the interference between the trigger signal and the operating current, reducing the complexity of the peripheral circuit design.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a gate-controlled fast ionization transistor and a symmetrical structure thereof. Background Art

[0002] With the advancement of technological research, pulsed power technology has gradually emerged in industrial production. Currently, pulsed power is widely used in a wide range of fields, including environmental protection, aerospace, biomedicine, resource extraction, military industry, and national defense. Pulsed power switches are the core of pulsed power technology. With the deepening of semiconductor theoretical research and the maturity of semiconductor manufacturing processes, semiconductor switches have occupied a key position in pulsed power switching. Semiconductor switches used in pulsed power technology are called semiconductor pulsed power devices.

[0003] Traditional semiconductor pulse power devices primarily include GTOs (Gate-Turn-Off Thyristors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors). In recent years, with the continued advancement of pulse power technology research, several new devices have emerged. Among them, the fast ionization dynamo (FID), a new type of semiconductor pulse power device, has significant application value in numerous fields.

[0004] The existing FID device is a two-terminal device with a basic structure as follows Figure 1 As shown in the figure, its operating characteristics are: a positive voltage is applied to the anode and a negative voltage is applied to the cathode, biasing the intermediate PN junction near critical breakdown. At this time, a strong positive pulse applied to the anode causes the device to undergo reversible breakdown, generating plasma. The device then quickly turns on, and the latch effect allows the device to remain on continuously. However, because the trigger signal and the operating current are coupled together, the FID has high requirements for the trigger signal strength and speed. The device also has a relatively low input impedance, requiring specific circuit design to avoid interference between the trigger signal and the operating current. This increases circuit complexity and results in high energy loss during the triggering process. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a gate-controlled fast ionization transistor and its symmetrical structure. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a gate-controlled fast ionization transistor, which comprises, from bottom to top, a cathode metal, a substrate, an epitaxial layer, an anode metal, and a gate metal; wherein,

[0007] A first doping region, a second doping region, a third doping region and a fourth doping region are provided inside the epitaxial layer;

[0008] The first doped region starts from the upper surface of the epitaxial layer and extends downward to the interior of the epitaxial layer;

[0009] The second doping region is located in the epitaxial layer to the left of the first doping region and is adjacent to the first doping region, and has the same thickness as that of the first doping region;

[0010] The third doping region starts from the upper left corner of the second doping region and extends to the lower right into the second doping region;

[0011] The fourth doping region starts from the upper left corner of the third doping region and extends to the lower right into the third doping region;

[0012] The anode metal is located above the fourth doping region;

[0013] The gate metal is located above the epitaxial layer between the third doping region and the first doping region, and a gate electrode and a gate dielectric layer are provided between the gate metal and the epitaxial layer.

[0014] In one embodiment of the present invention, the epitaxial layer and the substrate are heterotype doped.

[0015] In one embodiment of the present invention, the first doping region, the second doping region, and the third doping region have the same doping type, and the fourth doping region has the same doping type as the epitaxial layer.

[0016] In one embodiment of the present invention, the first doping region and the fourth doping region are heavily doped regions, the second doping region is a lightly doped region, and the doping concentration of the third doping region is higher than that of the second doping region.

[0017] In one embodiment of the present invention, the gate is made of polysilicon.

[0018] In one embodiment of the present invention, the substrate is N+ doped, the epitaxial layer is P doped, the first doping region is N+ doped, the second doping region is N- doped, the third doping region is N doped, and the fourth doping region is P+ doped.

[0019] In a second aspect, the present invention further provides a symmetrical structure of a gate-controlled fast ionization transistor, comprising a gate-controlled fast ionization transistor as described in the above embodiment, wherein two first doped regions are adjacent and symmetrically arranged; wherein a gate dielectric layer, a gate electrode and a gate metal are sequentially arranged above the first doped regions.

[0020] Beneficial effects of the present invention:

[0021] The gate-controlled fast ionization transistor provided by the present invention reduces the device's breakdown voltage through gate control, causing the device to undergo reversible avalanche breakdown, generate plasma, and conduct. This design significantly improves the device's input impedance, reduces leakage, and lowers trigger signal requirements. It also minimizes interference between the trigger signal and the operating current, reducing the complexity of peripheral circuit design.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of an existing fast ionization transistor;

[0024] Figure 2 1 is a schematic structural diagram of a gate-controlled fast ionization transistor provided by an embodiment of the present invention;

[0025] Figure 3 1 is a schematic structural diagram of a gate-controlled fast ionization transistor with an N+ substrate provided by an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the symmetrical structure of a gate-controlled fast ionization transistor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0028] Example 1

[0029] See Figure 2 , Figure 2 : is a schematic structural diagram of a gate-controlled fast ionization transistor provided by an embodiment of the present invention; it comprises, from bottom to top, a cathode metal 1, a substrate 2, an epitaxial layer 3, an anode metal 4, and a gate metal 5; wherein,

[0030] The epitaxial layer 3 is provided with a first doping region 31, a second doping region 32, a third doping region 33 and a fourth doping region 34;

[0031] The first doped region 31 starts from the upper surface of the epitaxial layer 3 and extends downward to the interior of the epitaxial layer 3;

[0032] The second doping region 32 is located in the epitaxial layer 3 on the left side of the first doping region 31 and is adjacent to the first doping region 31 , and has the same thickness as that of the first doping region 31 ;

[0033] The third doping region 33 starts from the upper left corner of the second doping region 32 and extends to the lower right into the second doping region 32;

[0034] The fourth doping region 34 starts from the upper left corner of the third doping region 33 and extends to the lower right into the third doping region 33;

[0035] The anode metal 4 is located above the fourth doping region 34;

[0036] The gate metal 5 is located above the epitaxial layer 3 between the third doping region 33 and the first doping region 31 , and a gate 6 and a gate dielectric layer 7 are further provided between the gate metal 5 and the epitaxial layer 3 .

[0037] The second doped region 32 extends from the left side of the epitaxial layer 3 to the right to connect with the first doped region 31, while forming a drift region in the underlying epitaxial layer 3. The third doped region 33 is located within the second doped region 32 and forms a drift region therein.

[0038] Furthermore, the epitaxial layer 3 and the substrate 2 are heterotype doped. The first doping region 31 , the second doping region 32 and the third doping region 33 have the same doping type, and the fourth doping region 34 has the same doping type as the epitaxial layer 3 .

[0039] Furthermore, the first doping region 31 and the fourth doping region 34 are heavily doped regions, the second doping region 32 is a lightly doped region, and the doping concentration of the third doping region 33 is higher than that of the second doping region 32 .

[0040] Generally, the substrate can be N-type doped or P-type doped. Considering that N-type substrates are mainly used in practical applications, this embodiment preferably uses an N+ substrate and a P-epitaxial layer to realize the device structure. Among them, the material of the N+ substrate is a semiconductor material such as silicon or silicon carbide, and the interface between the cathode metal 1 and the substrate 2 forms an ohmic contact. Correspondingly, the epitaxial layer 3 is lightly P-doped, recorded as a P-epitaxial layer, which can be formed by homoepitaxial growth on the basis of the substrate, and the drift region 35 is a P-drift region. The first doping region 31 is N+ doped, the second doping region 32 is N- doped, the third doping region (33) is N-type doped, and the fourth doping region 34 is P+ doped. The interface between the anode metal 4 and the second doping region 32 forms an ohmic contact, and the gate 6 is formed of polysilicon material.

[0041] It should be noted that the doping concentrations of the epitaxial layer 3, the first doping region 31, the second doping region 32, the third doping region 33 and the fourth doping region 34 in the gate-controlled fast ionization transistor provided in this embodiment can be appropriately adjusted according to the device's withstand voltage and the required turn-on gate voltage, and this embodiment does not make specific limitations.

[0042] The principle of the gate-controlled fast ionization transistor provided in this embodiment is described below by taking a gate-controlled fast ionization transistor with an N+ substrate as an example.

[0043] See Figure 3 , Figure 3 This is a schematic diagram of the structure of a gate-controlled fast ionization transistor with an N+ substrate, provided by an embodiment of the present invention. The N+ first doped region serves as the device's N+ trigger region, the fourth doped region forms the device's P+ region, and an N-type base region is formed within the third doped region. The third doped region is located within the second doped region, and an N-drift region is formed within the second doped region. Below the second doped region and the first doped region is a P-drift region.

[0044] Specifically, the gate-controlled fast ionization device has three operating modes: reverse cutoff state; forward cutoff state; closed state. The device can switch between these operating states during operation. The working process and principle are as follows:

[0045] Process 1: The cathode metal is grounded, no voltage is applied to the gate metal, and a positive voltage is applied to the anode metal. The voltage is slightly lower than the static breakdown voltage of the device. At this time, the device is not turned on and is in the forward cutoff state. The applied voltage is borne by the N-type base region, N-drift region and P-drift region. At this moment, the N-drift region is in a depleted pressure state.

[0046] Process 2: Positive voltage is applied to the gate metal. At this time, the N-drift region under the gate dielectric layer changes from a depletion pressure-bearing state to an accumulation state. The voltage applied in process 1 is gradually borne by the N+ trigger region and the P-drift region. The voltage exceeds the voltage they can bear, and reversible avalanche breakdown occurs, and plasma is generated inside the device.

[0047] Process three: The electrons in the generated plasma drift toward the anode and the holes drift toward the cathode, causing the holes in the P+ region to diffuse toward the N+ trigger region and the N-drift region, and the electrons in the N+ substrate to diffuse toward the P-drift region, generating positive feedback. When the loop gain is greater than 1, the device is continuously turned on and in a closed state. At this time, removing the positive voltage on the gate metal will not affect the on-state of the device.

[0048] Process 4: Remove the positive voltage of the gate metal, ground the cathode metal, apply negative voltage to the anode metal, and reverse the polarity. As the carriers are extracted, the positive feedback path is cut off and the device enters the reverse cutoff state. At this time, the polarity can be reversed again to return to process 1.

[0049] The gate-controlled fast ionization transistor provided in this embodiment reduces the device's breakdown voltage through gate control, causing the device to undergo reversible avalanche breakdown, generate plasma, and conduct. This design significantly improves the device's input impedance, reduces leakage, and lowers trigger signal requirements. It also minimizes interference between the trigger signal and the operating current, reducing the complexity of peripheral circuit design.

[0050] Example 2

[0051] Based on the above embodiment 1, this embodiment provides a symmetrical structure of a gate-controlled fast ionization transistor. Figure 4 , Figure 4 2 is a schematic diagram of a symmetrical structure of a gate-controlled fast ionization transistor provided in an embodiment of the present invention, which includes the gate-controlled fast ionization transistor provided in the above-mentioned embodiment 1 in which two first doping regions 31 are adjacent and symmetrically arranged; wherein a gate dielectric layer 7, a gate 6 and a gate metal 5 are sequentially provided above the first doping regions 31.

[0052] It can be seen that the gate-controlled avalanche trigger structure provided in this embodiment is symmetrically formed by the gate-controlled avalanche trigger structure provided in the above-mentioned embodiment 1, and a MOS structure is also formed above the first doped region. Therefore, the gate-controlled avalanche trigger structure of this embodiment also has the advantages of the above-mentioned embodiment 1. Its specific working principle can be found in the above-mentioned embodiment 1 and will not be described in detail here.

[0053] Based on the above-mentioned embodiment 1, this embodiment enables both sides to be turned on simultaneously through a gate control, thereby increasing the current density during conduction and improving the chip utilization efficiency without bringing about additional process complexity.

[0054] It should be noted that, in this embodiment, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0055] In addition, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0056] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0057] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A gate-controlled fast ionization transistor, characterized in that: From bottom to top, it includes: cathode metal (1), substrate (2), epitaxial layer (3), anode metal (4) and gate metal (5); wherein, The epitaxial layer (3) and the substrate (2) are heterotype doped; a first doping region (31), a second doping region (32), a third doping region (33) and a fourth doping region (34) are provided inside the epitaxial layer (3); the first doping region (31), the second doping region (32) and the third doping region (33) have the same doping type, and the fourth doping region (34) has the same doping type as the epitaxial layer (3); the first doping region (31) and the fourth doping region (34) are heavily doped regions, the second doping region (32) is a lightly doped region, and the doping concentration of the third doping region (33) is higher than that of the second doping region (32); The first doping region (31) starts from the upper surface of the epitaxial layer (3) and extends downward to the interior of the epitaxial layer (3); The second doping region (32) is located in the epitaxial layer (3) on the left side of the first doping region (31) and is adjacent to the first doping region (31), and has the same thickness as the first doping region (31); The third doping region (33) starts from the upper left corner of the second doping region (32) and extends to the lower right into the second doping region (32); The fourth doping region (34) starts from the upper left corner of the third doping region (33) and extends to the lower right into the third doping region (33); The anode metal (4) is located above the fourth doping region (34); The gate metal (5) is located above the epitaxial layer (3) between the third doping region (33) and the first doping region (31), and a gate (6) and a gate dielectric layer (7) are further provided between the gate metal (5) and the epitaxial layer (3).

2. The gate-controlled fast ionization transistor according to claim 1, characterized in that: The gate (6) is made of polysilicon.

3. The gate-controlled fast ionization transistor according to claim 1, characterized in that: The substrate (2) is N+ doped, the epitaxial layer (3) is P doped, the first doping region (31) is N+ doped, the second doping region (32) is N- doped, the third doping region (33) is N doped, and the fourth doping region (34) is P+ doped.

4. A symmetrical structure of a gate-controlled fast ionization transistor, characterized in that: A gate-controlled fast ionization transistor according to any one of claims 1 to 3, comprising two first doping regions (31) adjacent to and symmetrically arranged; wherein a gate dielectric layer (7), a gate electrode (6) and a gate metal (5) are sequentially arranged above the first doping regions (31).

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