Power converter

Abstract

The present application provides a small volume and temperature uniform power converter, which comprises a PCB with opposite first side and second side, and a plurality of first commutation units and first capacitors arranged on the PCB. Each first commutation unit comprises a first discrete device and a second discrete device, the second end of the first discrete device and the first end of the second discrete device are electrically coupled, and the first capacitors are respectively electrically coupled with the first end of the first discrete device and the second end of the second discrete device in the plurality of first commutation units. Wherein the first discrete device and the second discrete device in the plurality of first commutation units are arranged in a row, and the first discrete device and the second discrete device in each first commutation unit and the first capacitor constitute a commutation loop.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more particularly to a power converter. Background Technology

[0002] With the widespread application of renewable energy and the rapid development of the electric vehicle industry, energy storage technology will become a key link in promoting energy development. The rapid development of energy storage demand also puts forward higher requirements for the design of power converters in energy storage systems.

[0003] Existing power converters, including IGBT modules or SiC MOS modules, use modules as switching devices, which usually have the problem of large size, especially the difficulty in reducing the height of the modules; at the same time, they are prone to local overheating and heat dissipation difficulties.

[0004] In addition, to improve the power rating of the converter, a design scheme of interleaved parallel connection of multiphase converters or parallel connection of devices is usually adopted. Traditional parallel device schemes place parallel devices together, such as... Figure 1 The half-bridge circuit topology shown includes a bus capacitor C1, an upper transistor, and a lower transistor. The upper transistor consists of parallel-connected switches Q11, Q12, and Q13, while the lower transistor consists of parallel-connected switches Q21, Q22, and Q23. In this parallel connection scheme, the poor consistency of the commutation loops (loops 1, 2, and 3) leads to problems such as high voltage stress on the switches and poor current consistency across the parallel switches. Summary of the Invention

[0005] The purpose of this invention is to propose a power converter with a small and symmetrical commutation circuit, which is also beneficial for heat dissipation design.

[0006] According to one aspect of the present invention, a power converter includes a PCB having opposing first and second sides, and a plurality of first commutation units and a first capacitor disposed on the PCB. Each first commutation unit includes a first discrete device and a second discrete device, the second terminal of the first discrete device and the first terminal of the second discrete device being electrically coupled, and the first capacitor being electrically coupled to the first terminal of the first discrete device and the second terminal of the second discrete device in the plurality of first commutation units, respectively; wherein the first discrete device and the second discrete device in the plurality of first commutation units are arranged in a row, and the first discrete device and the second discrete device in each first commutation unit and the first capacitor form a commutation circuit.

[0007] According to one embodiment of the present invention, the first discrete devices in the plurality of first converter units are electrically coupled in parallel, and the second discrete devices in the plurality of first converter units are electrically coupled in parallel.

[0008] According to one embodiment of the present invention, the first discrete devices and the second discrete devices in the plurality of first converter units are arranged alternately in a row.

[0009] According to one embodiment of the present invention, the first discrete device and the second discrete device in the plurality of first converter units are located on the first side of the PCB.

[0010] According to one embodiment of the present invention, the PCB further includes a plurality of second commutation units; the plurality of second commutation units are symmetrically arranged with the plurality of first commutation units, each second commutation unit including a third discrete device and a fourth discrete device; the second terminal of the third discrete device and the first terminal of the fourth discrete device are electrically coupled; the first terminal of the third discrete device in the plurality of second commutation units is electrically coupled to the first terminal of the first discrete device in the plurality of first commutation units, and the second terminal of the fourth discrete device in the plurality of second commutation units is electrically coupled to the second terminal of the second discrete device in the plurality of first commutation units; wherein the third discrete device and the fourth discrete device in the plurality of second commutation units are arranged in a row, and the third discrete device and the fourth discrete device in each second commutation unit form a commutation circuit with the first capacitor.

[0011] According to one embodiment of the present invention, the PCB further includes a plurality of second commutation units and a second capacitor; the plurality of second commutation units are symmetrically arranged with the plurality of first commutation units, each second commutation unit including a third discrete device and a fourth discrete device; the second terminal of the third discrete device and the first terminal of the fourth discrete device are electrically coupled; the second capacitor is electrically coupled to the first terminal of the third discrete device and the second terminal of the fourth discrete device in the plurality of second commutation units respectively; the first capacitor and the second capacitor are connected in series, and the second terminal of the second discrete device in the plurality of first commutation units is electrically coupled to the first terminal of the third discrete device in the plurality of second commutation units; wherein the third discrete device and the fourth discrete device in the plurality of second commutation units are arranged in a row, and the third discrete device and the fourth discrete device in each second commutation unit and the second capacitor form a commutation circuit.

[0012] According to one embodiment of the present invention, the PCB further includes a plurality of second commutation units and a second capacitor; each second commutation unit includes a third discrete device and a fourth discrete device; the first terminal of the third discrete device in the plurality of second commutation units is electrically coupled to the first terminal of the second capacitor, the second terminal of the third discrete device in the plurality of second commutation units is electrically coupled to the first terminal of the first capacitor, the second terminal of the fourth discrete device in the plurality of second commutation units is electrically coupled to the second terminal of the second capacitor, and the first terminal of the fourth discrete device in the plurality of second commutation units is electrically coupled to the second terminal of the first capacitor; wherein the third discrete device and the fourth discrete device in the plurality of second commutation units are arranged in a row, and the third discrete device and the fourth discrete device in each second commutation unit, together with the second capacitor and the first capacitor, form a commutation circuit.

[0013] According to one embodiment of the present invention, the third discrete devices in the plurality of second converter units are electrically coupled in parallel, the fourth discrete devices in the plurality of second converter units are electrically coupled in parallel, and the plurality of second capacitors are electrically coupled in parallel.

[0014] According to one embodiment of the present invention, the third and fourth discrete devices in the plurality of second converter units are arranged alternately in a row.

[0015] According to one embodiment of the present invention, the plurality of first converter units are located on a first side of the PCB, the plurality of second converter units are located on a second side of the PCB, and the first capacitor is located between the first converter units and the second converter units.

[0016] According to one embodiment of the present invention, the first capacitor includes a plurality of first capacitors; the plurality of first capacitors are arranged in two rows side by side.

[0017] According to one embodiment of the present invention, the first discrete device and the second discrete device in the plurality of first converter units, as well as the third discrete device and the fourth discrete device in the plurality of second converter units, are arranged in a row and located on the first side of the PCB.

[0018] According to one embodiment of the present invention, the first capacitor includes a plurality of first capacitors; the plurality of first capacitors are arranged in a row.

[0019] According to one embodiment of the present invention, the first commutator unit is located on a first side of the PCB, the second commutator unit is located on a second side of the PCB, and the first capacitor and the second capacitor are located between the plurality of first commutator units and the plurality of second commutator units.

[0020] According to one embodiment of the present invention, the first capacitor includes a plurality of first capacitors; the second capacitor includes a plurality of second capacitors; the plurality of first capacitors are arranged in a row, the plurality of second capacitors are arranged in a row, and the first capacitors and the second capacitors are arranged side by side; wherein the plurality of first capacitors are close to the first converter unit, and the plurality of second capacitors are close to the second converter unit.

[0021] According to one embodiment of the present invention, the first capacitor includes a plurality of first capacitors; the second capacitor includes a plurality of second capacitors; a first portion of the plurality of first capacitors is arranged in a row, and a second portion of the plurality of first capacitors is alternately arranged in a row with the plurality of second capacitors and is arranged side by side with the first portion of the plurality of first capacitors; wherein the first portion of the plurality of first capacitors is close to a first discrete device and a second discrete device in the first converter unit, and the second portion of the plurality of first capacitors and the plurality of second capacitors are close to a third discrete device and a fourth discrete device in the second converter unit.

[0022] According to one embodiment of the present invention, the first capacitor and the second capacitor are arranged in a row, and the first discrete device and the second discrete device in the first converter unit, as well as the third discrete device and the fourth discrete device in the plurality of second converter units, are arranged in a row and located on the first side of the PCB.

[0023] According to one embodiment of the present invention, the first capacitor includes a plurality of first capacitors; the second capacitor includes a plurality of second capacitors; the plurality of first capacitors and the plurality of second capacitors are arranged in a row; wherein the plurality of first capacitors are close to the first discrete device and the second discrete device in the first converter unit, and the plurality of second capacitors are close to the third discrete device and the fourth discrete device in the plurality of second converter units.

[0024] According to one embodiment of the present invention, the first capacitor includes a plurality of first capacitors; the second capacitor includes a plurality of second capacitors; the plurality of first capacitors and the plurality of second capacitors are arranged in a row; wherein a first portion of the plurality of first capacitors is close to a first discrete device and a second discrete device in the first converter unit, and a second portion of the plurality of first capacitors and the plurality of second capacitors are alternately arranged in a row and close to a third discrete device and a fourth discrete device in the plurality of second converter units.

[0025] According to one embodiment of the present invention, the PCB further includes a plurality of third commutation units, a third capacitor, and a plurality of fourth commutation units. The plurality of third commutation units and the plurality of fourth commutation units are symmetrically arranged with respect to the plurality of first commutation units and the plurality of second commutation units. Each third commutation unit includes a fifth discrete device and a sixth discrete device. The second terminal of the fifth discrete device is electrically coupled to the first terminal of the sixth discrete device. The third capacitor is electrically coupled to the first terminal of the fifth discrete device and the second terminal of the sixth discrete device, respectively. The fifth discrete device and the sixth discrete device in the plurality of third commutation units are arranged in a row, and the fifth discrete device and the sixth discrete device in each third commutation unit and the third capacitor form a commutation circuit.

[0026] Each of the fourth converter units includes a seventh discrete device and an eighth discrete device. The third capacitor is electrically coupled to the second terminal of the seventh discrete device and the first terminal of the eighth discrete device, respectively. The second capacitor is electrically coupled to the first terminal of the seventh discrete device and the second terminal of the eighth discrete device, respectively. The seventh discrete device and the eighth discrete device in the plurality of fourth converter units are arranged in a row, and the seventh discrete device and the eighth discrete device in each fourth converter unit, together with the second capacitor and the third capacitor, form a converter circuit.

[0027] According to one embodiment of the present invention, the fifth discrete device in the plurality of third converter units is electrically coupled in parallel, and the sixth discrete device in the plurality of third converter units is electrically coupled in parallel; the seventh discrete device in the plurality of fourth converter units is electrically coupled in parallel, and the eighth discrete device in the plurality of fourth converter units is electrically coupled in parallel.

[0028] According to one embodiment of the present invention, the fifth and sixth discrete devices in the plurality of third converter units are arranged alternately in a row; the seventh and eighth discrete devices in the plurality of fourth converter units are arranged alternately in a row.

[0029] According to one embodiment of the present invention, the first capacitor includes a plurality of first capacitors; the second capacitor includes a plurality of second capacitors; the third capacitor includes a plurality of third capacitors; wherein the first and second discrete devices in the plurality of first converter units, and the third and fourth discrete devices in the plurality of second converter units are located on the first side of the PCB, and the fifth and sixth discrete devices in the plurality of third converter units, and the seventh and eighth discrete devices in the plurality of fourth converter units are located on the second side of the PCB; the first and second portions of the plurality of first capacitors are arranged in a row with the first portions of the plurality of second capacitors, and the second portions of the plurality of first capacitors are alternately arranged with the first portions of the plurality of second capacitors. The first portion of a plurality of first capacitors is close to the first and second discrete devices in the plurality of first converter units. The second portion of the plurality of first capacitors and the first portion of the plurality of second capacitors are close to the third and fourth discrete devices in the plurality of second converter units. The first and second portions of the plurality of third capacitors are arranged in a row with the second portions of the plurality of second capacitors, and the second portions of the plurality of third capacitors are alternately arranged with the second portions of the plurality of second capacitors. The first portion of the plurality of third capacitors is close to the fifth and sixth discrete devices in the plurality of third converter units. The second portion of the plurality of third capacitors and the second portion of the plurality of second capacitors are close to the seventh and eighth discrete devices in the plurality of fourth converter units.

[0030] According to one embodiment of the present invention, the first capacitor includes a plurality of first capacitors; the second capacitor includes a plurality of second capacitors; the third capacitor includes a plurality of third capacitors; wherein the plurality of first converter units and the plurality of third converter units are located on a first side of the PCB, and the plurality of second converter units and the plurality of fourth converter units are located on a second side of the PCB; the first portions of the plurality of first capacitors and the first portions of the plurality of third capacitors are arranged in a row, the first portions of the plurality of first capacitors are close to the first discrete device and the second discrete device in the plurality of first converter units, and the first portions of the plurality of third capacitors are close to the fifth discrete device and the sixth discrete device in the plurality of third converter units; the second portions of the plurality of first capacitors and the first portions of the ... and the second portions of the third capacitors are close to the fifth discrete device and the sixth discrete device in the plurality of third converter units; the second portions of the plurality of first capacitors and the third portions of the third capacitors are arranged in a row, the first portions of the plurality of first capacitors and the third portions of the third capacitors are close to the fifth discrete device and the sixth discrete device in the plurality of third converter units, the second portions of the plurality of first capacitors and the third portions of the third capacitors are arranged in a row, the first portions of the plurality of first capacitors and the third portions of the third capacitors are close to the fifth discrete device and the sixth discrete device in the plurality of third converter units, the second portions of the plurality of first capacitors and the third portions of the third capacitors are close to the fifth discrete device and the sixth discrete device in the plurality of third converter units, the second portions of the plurality of first capacitors and the third portions The first portions of the plurality of second capacitors are alternately arranged in a row, and the second portions of the plurality of third capacitors are alternately arranged in a row. The second portions of the plurality of first capacitors, the first portions of the plurality of second capacitors, the second portions of the plurality of third capacitors, and the second portions of the plurality of second capacitors are arranged side by side with the first portions of the plurality of first capacitors and the first portions of the plurality of third capacitors. The second portions of the plurality of first capacitors and the first portions of the plurality of second capacitors are close to the third and fourth discrete devices in the plurality of second converter circuits, and the second portions of the plurality of third capacitors and the second portions of the plurality of second capacitors are close to the seventh and eighth discrete devices in the plurality of fourth converter circuits.

[0031] According to one embodiment of the present invention, a closed cavity is further included, the closed cavity comprising a central chamber and a first side chamber and a second side chamber, the first side chamber and the second side chamber being located on both sides of the central chamber and communicating with the central chamber; wherein the plurality of first capacitors, the plurality of second capacitors and the plurality of third capacitors are housed in the central chamber, the first discrete device and the second discrete device in the plurality of first converter units, and the third discrete device and the fourth discrete device in the plurality of second converter units are housed in the first side chamber, the fifth discrete device and the sixth discrete device in the plurality of third converter units, and the seventh discrete device and the eighth discrete device in the plurality of fourth converter units are housed in the second side chamber, the first side chamber being provided with a first heat sink, and the second side chamber being provided with a second heat sink.

[0032] According to one embodiment of the present invention, a closed cavity is further included, the closed cavity comprising a central chamber and a first side chamber and a second side chamber, the first side chamber and the second side chamber being located on both sides of the central chamber and communicating with the central chamber; wherein the plurality of first capacitors, the plurality of second capacitors and the plurality of third capacitors are housed in the central chamber, the first discrete device and the second discrete device in the plurality of first converter units and the fifth discrete device and the sixth discrete device in the plurality of third converter units are housed in the first side chamber, the third discrete device and the fourth discrete device in the plurality of second converter units and the seventh discrete device and the eighth discrete device in the plurality of fourth converter units are housed in the second side chamber, the first side chamber is provided with a first heat sink, and the second side chamber is provided with a second heat sink.

[0033] According to one embodiment of the present invention, the device further includes a closed cavity, the closed cavity comprising a central chamber and a first side chamber communicating with the central chamber; the first capacitor is housed in the central chamber, the first discrete device and the second discrete device are housed in the first side chamber, and the first side chamber is provided with a first heat sink.

[0034] The present invention has at least the following advantages or beneficial effects: In the power converter of the present invention, the commutation unit does not contain a module, but is composed of multiple discrete devices, which allows for flexible arrangement of the positions of each discrete device, thus helping to reduce the overall height of the power converter; furthermore, the first discrete device and the second discrete device in each first commutation unit form a commutation loop with the first capacitor, making the commutation loop smaller and symmetrical. The first discrete devices and the second discrete devices in multiple first commutation units are arranged in a row, and the first discrete devices and the second discrete devices in each first commutation unit operate in a complementary control manner. When multiple discrete devices are arranged in a row, multiple heat-generating discrete devices can be avoided from concentrating, thus preventing local overheating and aiding in heat dissipation design. Attached Figure Description

[0035] The above and other features and advantages of the present invention will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic diagram of the commutation circuit of a traditional power converter;

[0037] Figure 2A This is a schematic diagram of the structure of a power converter according to a first embodiment of the present invention;

[0038] Figure 2B This is a topology diagram of the first converter unit in Embodiment 1 of the power converter of the present invention;

[0039] Figure 3AThis is a schematic diagram of the power converter in Embodiment 2 of the present invention;

[0040] Figure 3B This is a topology diagram of a power converter according to a second embodiment of the present invention;

[0041] Figure 3C This is a schematic diagram of another structure of the power converter according to Embodiment 2 of the present invention;

[0042] Figure 4A This is a schematic diagram of the power converter of embodiment three of the present invention;

[0043] Figure 4B This is a topology diagram of a power converter embodiment three of the present invention;

[0044] Figure 4C This is a schematic diagram of another structure of the power converter according to Embodiment 3 of the present invention;

[0045] Figure 5A This is a schematic diagram of the power converter in embodiment four of the present invention;

[0046] Figure 5B This is a topology diagram of the power converter in embodiment four of the present invention;

[0047] Figure 5C This is a schematic diagram of another structure of the power converter in Embodiment 4 of the present invention;

[0048] Figure 6A This is a schematic diagram of the structure of the power converter in embodiment five of the present invention;

[0049] Figure 6B This is a topology diagram of the power converter of embodiment five of the present invention;

[0050] Figure 6C This is another structural schematic diagram of the power converter of the present invention, embodiment five;

[0051] Figure 7A This is an exploded perspective view of the power converter of the present invention;

[0052] Figure 7B This is a three-dimensional assembly diagram of the power converter of the present invention;

[0053] Figure 7C This is a perspective view of the enclosed cavity in the power converter of the present invention;

[0054] Figure 7D This is a perspective view of the protective casing in the power converter of the present invention;

[0055] Figure 8 A schematic diagram of the main air duct and the auxiliary air duct in the power converter of the present invention is shown. Detailed Implementation

[0056] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0057] See Figure 2A and Figure 2B , Figure 2A This is a schematic diagram of the structure of a power converter according to a first embodiment of the present invention. Figure 2B This is a topology diagram of the first converter unit in Embodiment 1 of the power converter of the present invention.

[0058] like Figure 2A As shown, the power converter embodiment of the present invention includes a PCB 1 and a plurality of first commutation units and a first capacitor C1 disposed on the PCB 1, such as a DC bus capacitor, a flying capacitor, or an input capacitor. The PCB 1 has a first side 11 and a second side 12 opposite to each other.

[0059] Each first commutation unit includes a first discrete device Q1 and a second discrete device Q2. In each first commutation unit, the second terminal of the first discrete device Q1 and the first terminal of the second discrete device Q2 are electrically coupled. A first capacitor C1 is electrically coupled to the first terminal of the first discrete device Q1 and the second terminal of the second discrete device Q2 in each first commutation unit. Specifically, the pins of the first capacitor C1 and the pins of the first discrete device Q1 and the second discrete device Q2 in each commutation unit are soldered onto PCB 1, and the pins of the first capacitor C1 are electrically connected to the corresponding first discrete device Q1 and the second discrete device Q2 in the first commutation unit through traces on PCB 1.

[0060] The first discrete components Q1 and Q2 of multiple first converter units are arranged in a row on PCB1. The arranged discrete components can be located on either the first side 11 or the second side 12 of PCB1. The centerline of the arranged discrete components can be parallel to the edge of either the first side 11 or the second side 12 of PCB1. When the arranged discrete components are located on the first side 11 of PCB1, the first capacitor C1 is closer to the second side 12 of PCB1; when the arranged discrete components are located on the second side 12 of PCB1, the first capacitor C1 is closer to the first side 11 of PCB1. The first capacitor C1 and the first discrete components Q1 and Q2 of the multiple first converter units are located on the same side of PCB1.

[0061] The first capacitor C1 forms a commutation circuit with the first discrete device Q1 and the second discrete device Q2 in each first commutation unit, thereby forming multiple relatively independent small commutation circuits. The multiple commutation circuits of the multiple first commutation units are basically the same and symmetrical to each other, thus reducing the voltage stress on each discrete device and ensuring good current consistency in the power converter.

[0062] In one embodiment, the first capacitor C1 may include a plurality of first capacitors C1, wherein the plurality of first capacitors C1 may be connected in parallel. The plurality of first capacitors C1 may be arranged in a row on PCB 1, and the center line of the row of first capacitors C1 may be parallel to the center line of the row of discrete components. In other embodiments, the first capacitor C1 may be a single capacitor.

[0063] In one embodiment, the first discrete devices Q1 in the plurality of first converter units are electrically coupled in parallel, and the second discrete devices Q2 in the plurality of first converter units are electrically coupled in parallel.

[0064] like Figure 2A As shown in this embodiment, in multiple first converter units, first discrete devices Q1 and second discrete devices Q2 are alternately arranged in a row. That is, in the multiple discrete devices arranged in a row, a second discrete device Q2 is sandwiched between any two adjacent first discrete devices Q1, and a first discrete device Q1 is sandwiched between any two adjacent second discrete devices Q2. The power converter also includes a heat sink. The pins of the first discrete devices Q1 and second discrete devices Q2 in the multiple first converter units are soldered to PCB 1. The bodies of the first discrete devices Q1 and second discrete devices Q2 in the multiple first converter units are parallel to PCB 1, and the first surface of the bodies of the first discrete devices Q1 and second discrete devices Q2 in the multiple first converter units is close to PCB 1, while the second surface of the bodies of the first discrete devices Q1 and second discrete devices Q2 in the multiple first converter units is attached to the surface of the heat sink. The heat sink is used to dissipate heat from the first discrete devices Q1 and second discrete devices Q2 in the multiple first converter units. The first discrete device Q1 and the second discrete device Q2 in each first converter unit operate in a complementary control manner. The discrete devices generate a lot of heat during operation. When multiple first discrete devices Q1 and multiple second discrete devices Q2 are arranged alternately, the temperature on the heat sink will be more uniform, effectively avoiding local overheating, and helping to reduce the difficulty of heat dissipation design and improve heat dissipation efficiency.

[0065] In other embodiments, the plurality of first discrete devices Q1 and the plurality of second discrete devices Q2 may not necessarily be arranged alternately. For example, there may be two first discrete devices Q1 adjacent to each other or two second discrete devices Q2 adjacent to each other.

[0066] See Figure 3A , Figure 3B and Figure 3C , Figure 3A This is a schematic diagram of the power converter in Embodiment 2 of the present invention. Figure 3B This is a topology diagram of the power converter in Embodiment 2 of the present invention. Figure 3C This is another structural schematic diagram of the power converter embodiment two of the present invention.

[0067] like Figure 3A As shown, the difference between Embodiment 2 and Embodiment 1 of the power converter of the present invention is that it further includes a plurality of second commutation units disposed on PCB 1. The plurality of second commutation units and the plurality of first commutation units are symmetrically arranged with respect to a center line X of PCB 1.

[0068] Each second commutator unit includes a third discrete device Q3 and a fourth discrete device Q4, and a first capacitor C1 forms a commutation loop with the third discrete device Q3 and the fourth discrete device Q4 in each second commutator unit. The third discrete devices Q3 and the fourth discrete devices Q4 in multiple second commutator units are arranged in a row on PCB 1.

[0069] In this second embodiment, the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units are arranged alternately in a row. In some other embodiments, the plurality of third discrete devices Q3 and fourth discrete devices Q4 may also be arranged in other ways.

[0070] like Figure 3A As shown, the first capacitor C1 is located in the middle of PCB 1, and discrete components are located on both sides of the capacitor. Specifically, all the first discrete components Q1 and the second discrete component Q2 are located on the first side 11 of PCB 1, and all the third discrete components Q3 and the fourth discrete component Q4 are located on the second side 12 of PCB 1. That is, the first and second commutation units are symmetrically arranged on PCB 1, with the first commutation unit located in the lower half of PCB 1 and the second commutation unit located in the upper half of PCB 1. The first capacitor C1 can include multiple first capacitors C1, and these multiple first capacitors C1 can be arranged in two rows side-by-side on PCB 1. Each row of first capacitors C1 is close to the discrete components connected to it, minimizing the path length of the commutation loop formed by the discrete components in each commutation unit and the corresponding first capacitor C1.

[0071] like Figure 3CAs shown, all the first discrete devices Q1 and Q2, along with all the third discrete devices Q3 and Q4, are arranged in a row on the first side 11 of PCB 1, and the first capacitor C1 is located near the second side 12 of PCB 1. That is, the first and second commutation units are symmetrically arranged on PCB 1, with the first commutation unit located on the right half of PCB 1 and the second commutation unit located on the left half of PCB 1. The first capacitor C1 can include multiple first capacitors C1, and these multiple first capacitors C1 can be arranged in a row on PCB 1. The first capacitor C1 is located close to the discrete devices connected to it, minimizing the path length of the commutation loop formed by the discrete device in each commutation unit and the corresponding first capacitor C1.

[0072] like Figure 3B As shown, the first capacitor C1 is electrically coupled to the first terminal of the third discrete device Q3 and the second terminal of the fourth discrete device Q4 in each second converter unit, and the second terminal of the third discrete device Q3 and the first terminal of the fourth discrete device Q4 are electrically coupled.

[0073] The first terminal of the third discrete device Q3 is electrically coupled to the first terminal of the first discrete device Q1, and the second terminal of the fourth discrete device Q4 is electrically coupled to the second terminal of the second discrete device Q2, thereby forming a full-bridge circuit topology.

[0074] In this second embodiment, the third discrete device Q3 in the plurality of second converter units is electrically coupled in parallel, and the fourth discrete device Q4 in the plurality of second converter units is electrically coupled in parallel.

[0075] See Figure 4A , Figure 4B and Figure 4C , Figure 4A This is a schematic diagram of the power converter in Embodiment 3 of the present invention. Figure 4B This is a topology diagram of the power converter in Embodiment 3 of the present invention. Figure 4C This is another structural schematic diagram of the power converter of the present invention, embodiment three.

[0076] like Figure 4A As shown, the difference between Embodiment 3 and Embodiment 1 of the power converter of the present invention is that it further includes multiple second commutation units and a second capacitor C2 disposed on PCB 1. The multiple second commutation units are symmetrically arranged with the multiple first commutation units.

[0077] Each second converter unit includes a third discrete device Q3 and a fourth discrete device Q4. The second capacitor C2, together with the third discrete device Q3 and the fourth discrete device Q4 in each second converter unit, forms a converter circuit. The third discrete device Q3 and the fourth discrete device Q4 in multiple second converter units are arranged in a row.

[0078] In this third embodiment, the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units are arranged alternately in a row. In some other embodiments, the plurality of third discrete devices Q3 and fourth discrete devices Q4 may also be arranged in other ways.

[0079] like Figure 4A As shown, the first capacitor C1 and the second capacitor C2 are located in the middle of PCB 1, and discrete components are located on both sides of the first capacitor C1 and the second capacitor C2. Specifically, all the first discrete components Q1 and the second discrete components Q2 are located on the first side 11 of PCB 1, and all the third discrete components Q3 and the fourth discrete components Q4 are located on the second side 12 of PCB 1. The first capacitors C1 are arranged in a row and are arranged side-by-side with the second capacitors C2 arranged in a row. That is, the first commutation unit and the second commutation unit are symmetrically arranged on PCB 1 with respect to the first capacitors C1 and the second capacitors C2. The first commutation unit is located in the lower half of PCB 1, and the second commutation unit is located in the upper half of PCB 1. The first capacitor C1 may include multiple first capacitors C1, and the second capacitor C2 may include multiple second capacitors C2. Multiple first capacitors C1 and multiple second capacitors C2 can be arranged in a row on PCB 1. The first capacitor C1 in each row is close to the first discrete device Q1 and the second discrete device Q2 in each first converter unit connected to it, and the second capacitor C2 in each row is close to the third discrete device Q3 and the fourth discrete device Q4 in each second converter unit connected to it, so that the path of the converter loop formed by the discrete device in each first converter unit and the corresponding first capacitor C1 is minimized, and the path of the converter loop formed by the discrete device in each second converter unit and the corresponding second capacitor C2 is minimized.

[0080] like Figure 4CAs shown, all the first discrete components Q1 and Q2, along with all the third discrete components Q3 and Q4, are arranged in a row on the first side 11 of PCB 1. The first capacitor C1 and the second capacitor C2 are arranged in a row on the second side 12 of PCB 1, between the discrete components. That is, the first commutation unit and the second commutation unit are symmetrically arranged on PCB 1, with the first commutation unit located on the right half of PCB 1 and the second commutation unit located on the left half of PCB 1. The first capacitor C1 can include multiple first capacitors C1, and these multiple first capacitors C1 can be arranged in a row on PCB 1. Similarly, the second capacitor C2 can include multiple second capacitors C2, and these multiple second capacitors C2 can be arranged in a row on PCB 1. Multiple first capacitors C1 and multiple second capacitors C2 are arranged in a row on PCB 1. The first capacitor C1 is placed close to the first discrete device Q1 and the second discrete device Q2 in each first converter unit connected to it, such that the path of the converter loop formed by the first discrete device Q1 and the second discrete device Q2 in each first converter unit and the corresponding first capacitor C1 is minimized; and the second capacitor C2 is placed close to the third discrete device Q3 and the fourth discrete device Q4 in each second converter unit connected to it, such that the path of the converter loop formed by the third discrete device Q3 and the fourth discrete device Q4 in each second converter unit and the corresponding second capacitor C2 is minimized.

[0081] like Figure 4B As shown, the second terminal of the third discrete device Q3 and the first terminal of the fourth discrete device Q4 in each second converter unit are electrically coupled, and the second capacitor C2 is electrically coupled to the first terminal of the third discrete device Q3 and the second terminal of the fourth discrete device Q4 in each second converter unit.

[0082] The first capacitor C1 and the second capacitor C2 are connected in series and electrically coupled. The second end of the second discrete device Q2 in each first converter unit is electrically coupled to the first end of the third discrete device Q3 in each second converter unit, thereby forming a bridge arm series circuit topology.

[0083] In this third embodiment, multiple third discrete devices Q3 in multiple second converter units are electrically coupled in parallel, and multiple fourth discrete devices Q4 in multiple second converter units are electrically coupled in parallel.

[0084] The other structures of the power converter in Embodiment 3 of the present invention are basically the same as those in Embodiment 1, and will not be described again here.

[0085] See Figure 5A , Figure 5B and Figure 5C , Figure 5A This is a schematic diagram of the power converter in embodiment four of the present invention. Figure 5B This is a topology diagram of the power converter in embodiment four of the present invention. Figure 5C This is another structural schematic diagram of the power converter of the present invention, embodiment four.

[0086] See Figure 5A , Figure 5A This is a schematic diagram of the power converter in embodiment four of the present invention.

[0087] like Figure 5A As shown, the power converter embodiment four of the present invention differs from embodiment one in that it further includes multiple second commutation units and a second capacitor C2 disposed on PCB 1. The multiple second commutation units are symmetrically arranged with the multiple first commutation units.

[0088] Each second converter unit includes a third discrete device Q3 and a fourth discrete device Q4. A first capacitor C1 and a second capacitor C2, together with the third discrete device Q3 and the fourth discrete device Q4 in each second converter unit, form a converter circuit. The third discrete device Q3 and the fourth discrete device Q4 in multiple second converter units are arranged in a row.

[0089] In this fourth embodiment, the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units are arranged alternately in a row. In some other embodiments, the plurality of third discrete devices Q3 and fourth discrete devices Q4 may also be arranged in other ways.

[0090] like Figure 5AAs shown, the first capacitor C1 and the second capacitor C2 are located in the middle of PCB 1, and discrete components are located on both sides of the first capacitor C1 and the second capacitor C2. Specifically, all the first discrete components Q1 and the second discrete components Q2 are located on the first side 11 of PCB 1, and all the third discrete components Q3 and the fourth discrete components Q4 are located on the second side 12 of PCB 1. The first capacitor C1 and the second capacitor C2 are arranged side-by-side. That is, the first commutation unit and the second commutation unit are symmetrically arranged on PCB 1, with the first commutation unit located in the lower half of PCB 1 and the second commutation unit located in the upper half of PCB 1. The first capacitor C1 may include multiple first capacitors C1, and the second capacitor C2 may include multiple second capacitors C2. The first portions of the multiple first capacitors C1 can be arranged in a row on PCB 1, and the second portions of the multiple first capacitors C1 and the multiple second capacitors C2 can be alternately arranged in a row on PCB 1. The first portion of the plurality of first capacitors C1 is close to the first discrete device Q1 and the second discrete device Q2 in each first converter unit connected thereto, and the second portion of the plurality of second capacitors C2 and the plurality of first capacitors C1 is close to the third discrete device Q3 and the fourth discrete device Q4 in each second converter unit connected thereto, such that the path of the converter loop formed by the discrete device in each first converter unit and the corresponding first capacitor C1 is minimized, and the path of the converter loop formed by the discrete device in each second converter unit and the corresponding first capacitor C1 and the corresponding second capacitor C2 is minimized.

[0091] like Figure 5CAs shown, all the first discrete components Q1 and Q2, along with all the third discrete components Q3 and Q4, are arranged in a row on the first side 11 of PCB 1. The first capacitor C1 and the second capacitor C2 are arranged in a row between the second side 12 of PCB 1 and the discrete components. That is, the first commutation unit and the second commutation unit are symmetrically arranged on PCB 1, with the first commutation unit located on the right half of PCB 1 and the second commutation unit located on the left half of PCB 1. The first capacitor C1 may include multiple first capacitors C1, and the second capacitor C2 may include multiple second capacitors C2, with the multiple first capacitors C1 and multiple second capacitors C2 arranged in a row on PCB 1. Specifically, the first portions of the multiple first capacitors C1 can be arranged in a row on PCB 1, and the second portions of the multiple first capacitors C1 and the multiple second capacitors C2 can be alternately arranged in a row on PCB 1. The first portion of each of the first capacitors C1 is brought close to the first discrete device Q1 and the second discrete device Q2 in each of the first converter units connected thereto, such that the path of the converter loop formed by the first discrete device Q1 and the second discrete device Q2 in each of the first converter units and the corresponding first capacitor C1 is minimized; and the second portion of each of the first capacitors C1 and the second capacitors C2 are brought close to the third discrete device Q3 and the fourth discrete device Q4 in each of the second converter units connected thereto, such that the path of the converter loop formed by the third discrete device Q3 and the fourth discrete device Q4 in each of the second converter units and the corresponding second capacitor C2 and the corresponding first capacitor C1 is minimized.

[0092] like Figure 5BAs shown, the power converter embodiment four of the present invention differs from embodiment one in that the power converter further includes multiple second commutation units and a second capacitor C2 disposed on PCB 1, wherein the second capacitor C2 is an input capacitor or a DC bus capacitor, and each second commutation unit includes a third discrete device Q3 and a fourth discrete device Q4. The second capacitor C2 is electrically coupled to the first terminal of the third discrete device Q3 and the second terminal of the fourth discrete device Q4 in each second commutation unit, respectively. The first capacitor C1 is electrically coupled to the second terminal of the third discrete device Q3 and the first terminal of the fourth discrete device Q4 in each second commutation unit, respectively. The first capacitor C1 is also electrically coupled to the first terminal of the first discrete device Q1 and the second terminal of the second discrete device Q2 in the multiple first commutation units, wherein the first capacitor C1 can be a flying capacitor. The first capacitor C1, together with the first discrete device Q1 and the second discrete device Q2 in the multiple first converter units, forms a converter loop loop 1. The second capacitor C2 and the first capacitor C1, together with the third discrete device Q3 and the fourth discrete device Q4 in the multiple second converter units, form a converter loop loop 2. The converter loops in the multiple first converter units are symmetrical, and the converter loops in the multiple second converter units are symmetrical, which makes the current consistency on the discrete devices connected in parallel better.

[0093] The third discrete component Q3 in multiple second converter units is electrically coupled in parallel, and the fourth discrete component Q4 in multiple second converter units is electrically coupled in parallel. The output terminal of the power converter can be coupled in series with an inductor L and an output capacitor C0.

[0094] See Figure 6A , Figure 6B and Figure 6C , Figure 6A This is a schematic diagram of the structure of the power converter in embodiment five of the present invention. Figure 6B This is a topology diagram of the power converter in embodiment five of the present invention. Figure 6C This is another structural schematic diagram of the power converter embodiment five of the present invention.

[0095] like Figure 6A As shown, the difference between Embodiment 5 and Embodiment 4 of the power converter of the present invention is that Embodiment 5 further includes multiple third commutation units, a third capacitor C3, and multiple fourth commutation units disposed on PCB 1. The third capacitor C3 can be a flying capacitor. The structure of the third commutation unit is basically the same as that of the first commutation unit, and the structure of the fourth commutation unit is basically the same as that of the second commutation unit. The third and fourth commutation units are symmetrically arranged with respect to the first and second commutation units.

[0096] In this embodiment, the first converter unit and the second converter unit constitute phase A of the power converter, and the third converter unit and the fourth converter unit constitute phase B of the power converter, wherein phase A and phase B of the power converter are connected in parallel.

[0097] like Figure 6A As shown, each third converter unit includes a fifth discrete device Q5 and a sixth discrete device Q6. The fifth discrete devices Q5 and the sixth discrete devices Q6 in multiple third converter units are arranged in a row. The fifth discrete devices Q5 and the sixth discrete devices Q6 in multiple third converter units can be arranged alternately in a row. The third capacitor C3, together with the fifth discrete devices Q5 and the sixth discrete devices Q6 in each third converter unit, forms a converter circuit.

[0098] In this embodiment, the fifth discrete device Q5 in the plurality of third converter units is electrically coupled in parallel, and the sixth discrete device Q6 in the plurality of third converter units is electrically coupled in parallel.

[0099] Each fourth converter unit includes a seventh discrete device Q7 and an eighth discrete device Q8. The seventh discrete devices Q7 and the eighth discrete devices Q8 in multiple fourth converter units are arranged in a row. The seventh discrete devices Q7 and the eighth discrete devices Q8 in multiple fourth converter units can be arranged alternately in a row. The second capacitor C2 and the third capacitor C3, together with the seventh discrete devices Q7 and the eighth discrete devices Q8 in each fourth converter unit, form a converter loop.

[0100] In this fifth embodiment, the seventh discrete device Q7 in the plurality of fourth converter units is electrically coupled in parallel, and the eighth discrete device Q8 in the plurality of fourth converter units is electrically coupled in parallel.

[0101] The first capacitor C1 includes multiple first capacitors C1, the second capacitor C2 includes multiple second capacitors C2, and the third capacitor C3 includes multiple third capacitors C3.

[0102] The first discrete device Q1 and the second discrete device Q2 in the plurality of first converter units, as well as the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units, are located on the first side 11 of the PCB 1. The fifth discrete device Q5 and the sixth discrete device Q6 in the plurality of third converter units, as well as the seventh discrete device Q7 and the eighth discrete device Q8 in the plurality of fourth converter units, are located on the second side 12 of the PCB 1.

[0103] The first and second portions of the plurality of first capacitors C1 are arranged in a row with the first portions of the plurality of second capacitors C2, and the second portions of the plurality of first capacitors C1 and the first portions of the plurality of second capacitors C2 are alternately arranged. The first portions of the plurality of first capacitors C1 are close to the first discrete device Q1 and the second discrete device Q2 in the plurality of first converter units, so that the first discrete device Q1 and the second discrete device Q2 in the plurality of first converter units and the corresponding first capacitor C1 form the smallest converter loop.

[0104] The second part of the plurality of first capacitors C1 and the first part of the plurality of second capacitors C2 are close to the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units, so that the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units, together with the corresponding first capacitor C1 and the corresponding second capacitor C2, form the minimum converter circuit.

[0105] The first and second portions of the plurality of third capacitors C3 are arranged in a row with the second portions of the plurality of second capacitors C2, and the second portions of the plurality of third capacitors C3 and the second portions of the plurality of second capacitors C2 are alternately arranged.

[0106] The first portions of the plurality of first capacitors C1 and the plurality of second capacitors C2 are arranged side by side with the second portions of the plurality of third capacitors C3 and the plurality of second capacitors C2; the first portions of the plurality of third capacitors C3 are close to the fifth discrete device Q5 and the sixth discrete device Q6 in the plurality of third converter units, so that the fifth discrete device Q5 and the sixth discrete device Q6 in the plurality of third converter units and the corresponding third capacitors C3 form the smallest converter loop.

[0107] The second part of the plurality of third capacitors C3 and the second part of the plurality of second capacitors C2 are close to the seventh discrete device Q7 and the eighth discrete device Q8 in the plurality of fourth converter units, so that the seventh discrete device Q7 and the eighth discrete device Q8 in the plurality of fourth converter units, together with the corresponding second capacitor C2 and the corresponding third capacitor C3, form the minimum converter circuit.

[0108] like Figure 6C As shown, the first capacitor C1 includes multiple first capacitors C1; the second capacitor C2 includes multiple second capacitors C2; and the third capacitor C3 includes multiple third capacitors C3.

[0109] The first discrete device Q1 and the second discrete device Q2 in the plurality of first converter units, and the fifth discrete device Q5 and the sixth discrete device Q6 in the plurality of third converter units are located on the first side 11 of the PCB 1, and the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units, and the seventh discrete device Q7 and the eighth discrete device Q8 in the plurality of fourth converter units are located on the second side 12 of the PCB 1.

[0110] The first portions of the plurality of first capacitors C1 and the first portions of the plurality of third capacitors C3 are arranged in a row, with the first portions of the plurality of first capacitors C1 close to the first discrete device Q1 and the second discrete device Q2 in the plurality of first converter units, so that the first discrete device Q1 and the second discrete device Q2 in the plurality of first converter units and the corresponding first capacitor C1 form the smallest converter loop.

[0111] The first part of the plurality of third capacitors C3 is close to the fifth discrete device Q5 and the sixth discrete device Q6 in the plurality of third converter units, so that the fifth discrete device Q5 and the sixth discrete device Q6 in the plurality of third converter units and the corresponding third capacitor C3 form the smallest converter loop.

[0112] The second portions of the plurality of first capacitors C1 and the second portions of the plurality of third capacitors C3, and the first and second portions of the plurality of second capacitors C2 are arranged in a row; the first portions of the plurality of first capacitors C1 and the first portions of the plurality of third capacitors C3 are arranged side by side with the second portions of the plurality of first capacitors C1, the plurality of second capacitors C2 and the plurality of third capacitors C3, and the second portions of the plurality of first capacitors C1 and the first portions of the plurality of second capacitors C2 are arranged alternately, and the second portions of the plurality of third capacitors C3 and the second portions of the plurality of second capacitors C2 are arranged alternately.

[0113] The second part of the plurality of first capacitors C1 and the first part of the plurality of second capacitors C2 are close to the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units, so that the third discrete device Q3 and the fourth discrete device Q4 in the plurality of second converter units, together with the corresponding first capacitor C1 and the corresponding second capacitor C2, form the minimum converter circuit.

[0114] The second part of the plurality of third capacitors C3 and the second part of the plurality of second capacitors C2 are close to the seventh discrete device Q7 and the eighth discrete device Q8 in the plurality of fourth converter units, so that the seventh discrete device Q7 and the eighth discrete device Q8 in the plurality of fourth converter units, together with the corresponding second capacitor C2 and the corresponding third capacitor C3, form the minimum converter circuit.

[0115] refer to Figure 6BThe A-phase topology and B-phase topology shown are basically the same as the A-phase topology. In detail, each of the third converter units includes a fifth discrete device Q5 and a sixth discrete device Q6. The second terminal of the fifth discrete device Q5 is electrically coupled to the first terminal of the sixth discrete device Q6. The third capacitor C3 is electrically coupled to the first terminal of the fifth discrete device Q5 and the second terminal of the sixth discrete device Q6, respectively. The fifth discrete devices Q5 and the sixth discrete devices Q6 in the plurality of third converter units are arranged in a row, and the fifth discrete devices Q5 and the sixth discrete devices Q6 in each third converter unit and the third capacitor C3 form a converter circuit.

[0116] Each of the fourth converter units includes a seventh discrete device Q7 and an eighth discrete device Q8. The third capacitor C3 is electrically coupled to the second terminal of the seventh discrete device Q7 and the first terminal of the eighth discrete device Q8, respectively. The second capacitor C2 is electrically coupled to the first terminal of the seventh discrete device Q7 and the second terminal of the eighth discrete device Q8, respectively. The seventh discrete device Q7 and the eighth discrete device Q8 in the plurality of fourth converter units are arranged in a row, and the seventh discrete device Q7 and the eighth discrete device Q8 in each fourth converter unit, together with the second capacitor C2 and the third capacitor C3, form a converter circuit.

[0117] The other structures of the power converter in Embodiment 5 of the present invention are basically the same as those in Embodiment 4, and will not be described again here.

[0118] See Figure 7A , Figure 7A This is an exploded perspective view of the power converter of the present invention; Figure 7B This is a three-dimensional assembly diagram of the power converter of the present invention; Figure 7C This is a perspective view of the enclosed cavity in the power converter of the present invention; Figure 7D This is a perspective view of the protective casing in the power converter of this invention. (See diagram below.) Figure 7A and Figure 7B As shown, the power converter of the present invention further includes a closed cavity. The closed cavity includes a central chamber 100 and a first side chamber 101 and a second side chamber 102 communicating with the central chamber 100. The first side chamber 101 and the second side chamber 102 are located on opposite sides of the central chamber 100. A first heat sink 201 is installed at the bottom of the first side chamber 101; a second heat sink 202 is installed at the bottom of the second side chamber 102.

[0119] See Figure 7A and Figure 6AIn the power converter of the present invention, all capacitors, including the first capacitor C1, the second capacitor C2, and the third capacitor C3, are housed within the central chamber 100; all discrete devices located on one side of the capacitors, including the first discrete device Q1, the second discrete device Q2, the third discrete device Q3, and the fourth discrete device Q4, are housed within the first side chamber 101; and all discrete devices located on the other side of the capacitors, including the fifth discrete device Q5, the sixth discrete device Q6, the seventh discrete device Q7, and the eighth discrete device Q8, are housed within the second side chamber 102. Furthermore, the surfaces of the bodies of the first discrete device Q1, the second discrete device Q2, the third discrete device Q3, and the fourth discrete device Q4 are attached to the first heat sink 201, and the surfaces of the bodies of the fifth discrete device Q5, the sixth discrete device Q6, the seventh discrete device Q7, and the eighth discrete device Q8 are attached to the second heat sink 202.

[0120] The top openings of the central chamber 100, the first side chamber 101, and the second side chamber 102 are sealed with cover plates 103.

[0121] In this invention, a closed chamber is formed by a cover plate 103, a central chamber 100, a first side chamber 101, a second side chamber 102, a first radiator 201, and a second radiator 202. This closed chamber can achieve an IP65 protection level.

[0122] like Figure 7D As shown, a protective outer shell 1000 can be installed outside the closed cavity.

[0123] See Figure 7C In the power converter of the present invention, all capacitors, including the first capacitor C1, the second capacitor C2, and the third capacitor C3, are housed within the central chamber 100; all discrete devices located on one side of the capacitors, including the first discrete device Q1, the second discrete device Q2, the fifth discrete device Q5, and the sixth discrete device Q6, are housed within the first side chamber 101; and all discrete devices located on the other side of the capacitors, including the third discrete device Q3, the fourth discrete device Q4, the seventh discrete device Q7, and the eighth discrete device Q8, are housed within the second side chamber 102. Furthermore, the surfaces of the bodies of the first discrete device Q1, the second discrete device Q2, the fifth discrete device Q5, and the sixth discrete device Q6 are attached to the first heat sink 201, and the surfaces of the bodies of the third discrete device Q3, the fourth discrete device Q4, the seventh discrete device Q7, and the eighth discrete device Q8 are attached to the second heat sink 202.

[0124] like Figure 7D and Figure 8As shown, the front end of the enclosed cavity is spaced apart from the front end of the protective housing 1000. A cooling fan 200 can be installed in front of the central chamber 100 of the enclosed cavity. An inductor L is installed behind the enclosed cavity. Part of the cool air generated by the cooling fan 200 is supplied to the first heat sink 201, the second heat sink 202, and the inductor L via the main air duct 300, and the other part is supplied to the PCB 1 via the secondary air duct 400. The power converter of the present invention not only has a high protection level but also good heat dissipation performance.

[0125] In some other embodiments, the enclosed cavity includes a central chamber 100, a side chamber communicating therewith, such as a first side chamber 101, and a radiator, such as a first radiator 101. The openings at the top of the central chamber 100 and the first side chamber 101 are covered with cover plates 103.

[0126] like Figure 2A In the power converter embodiment shown, all the first capacitors C1 are housed in the central chamber 100, and all the first discrete devices Q1 and the second discrete devices Q2 are housed in the first side chamber 101.

[0127] In the embodiments of this application, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0128] In the description of the embodiments of the application, it should be understood that the terms "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of the application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the application.

[0129] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the claims. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0130] The above are merely preferred embodiments of the application examples and are not intended to limit the application examples. For those skilled in the art, the application examples can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the application examples should be included within the protection scope of the application examples.

Claims

1. A power converter, characterized in that, The device includes a PCB with opposing first and second sides, and a plurality of first commutation units and a plurality of first capacitors disposed on the PCB. Each first commutation unit includes a first discrete device and a second discrete device, the second end of the first discrete device and the first end of the second discrete device being electrically coupled. The plurality of first capacitors are respectively electrically coupled to the first end of the first discrete device and the second end of the second discrete device in the plurality of first commutation units. The first discrete device and the second discrete device in the plurality of first commutation units are arranged in a row. The first discrete device and the second discrete device in each first commutation unit, together with a first capacitor located on the PCB and physically closest to the first commutation unit, constitute a commutation loop. Furthermore, the first capacitor used in each commutation loop is different from the first capacitor in any other commutation loop.

2. The power converter as described in claim 1, characterized in that, The first discrete devices in the plurality of first converter units are electrically coupled in parallel, and the second discrete devices in the plurality of first converter units are electrically coupled in parallel.

3. The power converter as described in claim 1, characterized in that, The first discrete devices and second discrete devices in the plurality of first converter units are arranged alternately in a row.

4. The power converter as described in claim 1, characterized in that, The first discrete device and the second discrete device in the plurality of first converter units are located on the first side of the PCB.

5. The power converter as described in claim 1, characterized in that, It also includes a plurality of second commutation units disposed on the PCB; the plurality of second commutation units are symmetrically arranged with the plurality of first commutation units, each second commutation unit including a third discrete device and a fourth discrete device; the second terminal of the third discrete device and the first terminal of the fourth discrete device are electrically coupled; the first terminal of the third discrete device in the plurality of second commutation units is electrically coupled to the first terminal of the first discrete device in the plurality of first commutation units, and the second terminal of the fourth discrete device in the plurality of second commutation units is electrically coupled to the second terminal of the second discrete device in the plurality of first commutation units; wherein the third discrete device and the fourth discrete device in the plurality of second commutation units are arranged in a row, and the third discrete device and the fourth discrete device in each second commutation unit form a commutation circuit with the first capacitor.

6. The power converter as described in claim 1, characterized in that, It also includes a plurality of second commutation units and a second capacitor disposed on the PCB; the plurality of second commutation units are symmetrically arranged with the plurality of first commutation units, each second commutation unit including a third discrete device and a fourth discrete device; the second terminal of the third discrete device and the first terminal of the fourth discrete device are electrically coupled; the second capacitor is electrically coupled to the first terminal of the third discrete device and the second terminal of the fourth discrete device in the plurality of second commutation units respectively; the first capacitor and the second capacitor are connected in series, and the second terminal of the second discrete device in the plurality of first commutation units is electrically coupled to the first terminal of the third discrete device in the plurality of second commutation units; wherein the third discrete device and the fourth discrete device in the plurality of second commutation units are arranged in a row, and the third discrete device and the fourth discrete device in each second commutation unit and the second capacitor form a commutation circuit.

7. The power converter as described in claim 1, characterized in that, It also includes a plurality of second commutation units and a second capacitor disposed on the PCB; each second commutation unit includes a third discrete device and a fourth discrete device; the first terminal of the third discrete device in the plurality of second commutation units is electrically coupled to the first terminal of the second capacitor, the second terminal of the third discrete device in the plurality of second commutation units is electrically coupled to the first terminal of the first capacitor, the second terminal of the fourth discrete device in the plurality of second commutation units is electrically coupled to the second terminal of the second capacitor, and the first terminal of the fourth discrete device in the plurality of second commutation units is electrically coupled to the second terminal of the first capacitor; wherein the third discrete device and the fourth discrete device in the plurality of second commutation units are arranged in a row, and the third discrete device and the fourth discrete device in each second commutation unit, together with the second capacitor and the first capacitor, form a commutation circuit.

8. The power converter as described in claim 5, 6, or 7, characterized in that, It also includes a plurality of second capacitors disposed on the PCB, third discrete devices in the plurality of second converter units connected in parallel and electrically coupled, fourth discrete devices in the plurality of second converter units connected in parallel and electrically coupled, and the plurality of second capacitors connected in parallel and electrically coupled.

9. The power converter as described in claim 5, 6, or 7, characterized in that, The third and fourth discrete devices in the plurality of second converter units are arranged alternately in a row.

10. The power converter as described in claim 5, characterized in that, The plurality of first converter units are located on the first side of the PCB, the plurality of second converter units are located on the second side of the PCB, and the first capacitor is located between the first converter units and the second converter units.

11. The power converter as claimed in claim 10, characterized in that, The plurality of first capacitors are arranged in two rows side by side.

12. The power converter as described in claim 5, characterized in that, The first and second discrete devices in the plurality of first converter units, as well as the third and fourth discrete devices in the plurality of second converter units, are arranged in a row and located on the first side of the PCB.

13. The power converter as described in claim 12, characterized in that, The plurality of first capacitors are arranged in a row.

14. The power converter as described in claim 6 or 7, characterized in that, The first converter unit is located on the first side of the PCB, the second converter unit is located on the second side of the PCB, and the first capacitor and the second capacitor are located between the plurality of first converter units and the plurality of second converter units.

15. The power converter as described in claim 14, characterized in that, The second capacitor includes a plurality of second capacitors; the plurality of first capacitors are arranged in a row, the plurality of second capacitors are arranged in a row, and the first capacitors and the second capacitors are arranged side by side; wherein the plurality of first capacitors are close to the first converter unit, and the plurality of second capacitors are close to the second converter unit.

16. The power converter as described in claim 14, characterized in that, The second capacitor includes a plurality of second capacitors; a first portion of the plurality of first capacitors is arranged in a row, and a second portion of the plurality of first capacitors is alternately arranged in a row with the plurality of second capacitors and is arranged side by side with the first portion of the plurality of first capacitors; wherein the first portion of the plurality of first capacitors is close to the first discrete device and the second discrete device in the first converter unit, and the second portion of the plurality of first capacitors and the plurality of second capacitors are close to the third discrete device and the fourth discrete device in the second converter unit.

17. The power converter as described in claim 6 or 7, characterized in that, The first capacitor and the second capacitor are arranged in a row, and the first discrete device and the second discrete device in the first converter unit, as well as the third discrete device and the fourth discrete device in the plurality of second converter units, are arranged in a row and located on the first side of the PCB.

18. The power converter as claimed in claim 17, characterized in that, The second capacitor includes a plurality of second capacitors; the plurality of first capacitors and the plurality of second capacitors are arranged in a row; wherein the plurality of first capacitors are close to the first discrete device and the second discrete device in the first converter unit, and the plurality of second capacitors are close to the third discrete device and the fourth discrete device in the plurality of second converter units.

19. The power converter as claimed in claim 17, characterized in that, The second capacitor includes a plurality of second capacitors; the plurality of first capacitors and the plurality of second capacitors are arranged in a row; wherein the first portion of the plurality of first capacitors is close to the first discrete device and the second discrete device in the first converter unit, and the second portion of the plurality of first capacitors and the plurality of second capacitors are alternately arranged in a row and close to the third discrete device and the fourth discrete device in the plurality of second converter units.

20. The power converter as claimed in claim 7, characterized in that, It also includes multiple third converter units, a third capacitor, and multiple fourth converter units disposed on the PCB. The multiple third converter units and the multiple fourth converter units are symmetrically arranged with respect to the multiple first converter units and the multiple second converter units. Each third converter unit includes a fifth discrete device and a sixth discrete device. The second terminal of the fifth discrete device is electrically coupled to the first terminal of the sixth discrete device. The third capacitor is electrically coupled to the first terminal of the fifth discrete device and the second terminal of the sixth discrete device, respectively. The fifth and sixth discrete devices in the multiple third converter units are arranged in a row. The fifth and sixth discrete devices in the three-converter unit form a converter circuit with the third capacitor; each of the fourth converter units includes a seventh and an eighth discrete device, the third capacitor is electrically coupled to the second terminal of the seventh discrete device and the first terminal of the eighth discrete device, respectively, and the second capacitor is electrically coupled to the first terminal of the seventh discrete device and the second terminal of the eighth discrete device, respectively; wherein the seventh and eighth discrete devices in the plurality of fourth converter units are arranged in a row, and the seventh and eighth discrete devices in each of the fourth converter units form a converter circuit with the second capacitor and the third capacitor.

21. The power converter as claimed in claim 20, characterized in that, The fifth discrete device in the plurality of third converter units is electrically coupled in parallel, and the sixth discrete device in the plurality of third converter units is electrically coupled in parallel; the seventh discrete device in the plurality of fourth converter units is electrically coupled in parallel, and the eighth discrete device in the plurality of fourth converter units is electrically coupled in parallel.

22. The power converter as described in claim 20, characterized in that, The fifth and sixth discrete devices in the plurality of third converter units are arranged alternately in a row; the seventh and eighth discrete devices in the plurality of fourth converter units are arranged alternately in a row.

23. The power converter as described in claim 20, characterized in that, The second capacitor includes multiple second capacitors; the third capacitor includes multiple third capacitors; wherein the first and second discrete devices in the multiple first converter units, as well as the third and fourth discrete devices in the multiple second converter units, are located on the first side of the PCB; the fifth and sixth discrete devices in the multiple third converter units, as well as the seventh and eighth discrete devices in the multiple fourth converter units, are located on the second side of the PCB; the first and second portions of the multiple first capacitors are arranged in a row with the first portions of the multiple second capacitors, and the second portions of the multiple first capacitors are alternately arranged with the first portions of the multiple second capacitors, with the first portions of the multiple first capacitors close to each other. The plurality of first converter units contain first discrete devices and second discrete devices. The second part of the plurality of first capacitors and the first part of the plurality of second capacitors are close to the third and fourth discrete devices in the plurality of second converter units. The first and second parts of the plurality of third capacitors are arranged in a row with the second parts of the plurality of second capacitors, and the second parts of the plurality of third capacitors are alternately arranged with the second parts of the plurality of second capacitors. The first part of the plurality of third capacitors is close to the fifth and sixth discrete devices in the plurality of third converter units. The second part of the plurality of third capacitors and the second part of the plurality of second capacitors are close to the seventh and eighth discrete devices in the plurality of fourth converter units.

24. The power converter as claimed in claim 20, characterized in that, The second capacitor includes multiple second capacitors; the third capacitor includes multiple third capacitors; wherein the multiple first commutator units and the multiple third commutator units are located on the first side of the PCB, and the multiple second commutator units and the multiple fourth commutator units are located on the second side of the PCB; the first portions of the multiple first capacitors and the first portions of the multiple third capacitors are arranged in a row, the first portions of the multiple first capacitors are close to the first discrete device and the second discrete device in the multiple first commutator units, and the first portions of the multiple third capacitors are close to the fifth discrete device and the sixth discrete device in the multiple third commutator units; the second portions of the multiple first capacitors and the first portions of the multiple second capacitors intersect... The components are arranged alternately in a row, with the second portions of the plurality of third capacitors and the second portions of the plurality of second capacitors arranged alternately in a row, and the second portions of the plurality of first capacitors, the first portions of the plurality of second capacitors, the second portions of the plurality of third capacitors, and the second portions of the plurality of second capacitors arranged side by side with the first portions of the plurality of first capacitors and the first portions of the plurality of third capacitors; the second portions of the plurality of first capacitors and the first portions of the plurality of second capacitors are close to the third and fourth discrete devices in the plurality of second converter units, and the second portions of the plurality of third capacitors and the second portions of the plurality of second capacitors are close to the seventh and eighth discrete devices in the plurality of fourth converter units.

25. The power converter as described in claim 23, characterized in that, It also includes a closed cavity, which comprises a central chamber and a first side chamber and a second side chamber. The first side chamber and the second side chamber are located on both sides of the central chamber and communicate with the central chamber. The plurality of first capacitors, the plurality of second capacitors, and the plurality of third capacitors are housed in the central chamber. The first and second discrete devices of the plurality of first converter units, as well as the third and fourth discrete devices of the plurality of second converter units, are housed in the first side chamber. The fifth and sixth discrete devices of the plurality of third converter units, as well as the seventh and eighth discrete devices of the plurality of fourth converter units, are housed in the second side chamber. The first side chamber is provided with a first heat sink, and the second side chamber is provided with a second heat sink.

26. The power converter as described in claim 24, characterized in that, It also includes a closed cavity, which comprises a central chamber and a first side chamber and a second side chamber. The first side chamber and the second side chamber are located on both sides of the central chamber and communicate with the central chamber. The plurality of first capacitors, the plurality of second capacitors, and the plurality of third capacitors are housed in the central chamber. The first discrete device and the second discrete device in the plurality of first converter units, as well as the fifth discrete device and the sixth discrete device in the plurality of third converter units, are housed in the first side chamber. The third discrete device and the fourth discrete device in the plurality of second converter units, as well as the seventh discrete device and the eighth discrete device in the plurality of fourth converter units, are housed in the second side chamber. The first side chamber is provided with a first heat sink, and the second side chamber is provided with a second heat sink.

27. The power converter according to any one of claims 1-4, characterized in that, It also includes a closed cavity, which includes a central chamber and a first side chamber communicating with the central chamber; the first capacitor is housed in the central chamber, and the first discrete device and the second discrete device are housed in the first side chamber, which is provided with a first heat sink.

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